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You will strengthen Synopsys&#39; reputation as a trusted partner and thought leader in the semiconductor industry.</p>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.</li>\n<li>Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).</li>\n<li>Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place &amp; Route, and timing analysis.</li>\n<li>Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.</li>\n<li>Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.</li>\n<li>Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.</li>\n<li>Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent communicator able to build trust and rapport with diverse stakeholders.</li>\n<li>Analytical thinker with strong troubleshooting and debugging skills.</li>\n<li>Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.</li>\n<li>Highly collaborative team player who thrives in fast-paced, multicultural environments.</li>\n<li>Self-motivated, innovative, and passionate about continuous learning and process improvement.</li>\n<li>Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, expert team within the Silicon Design &amp; Verification business at Synopsys, based in Hyderabad. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</li>\n<li>Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.</li>\n<li>Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.</li>\n<li>Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power &amp; IR drop signoff to debug and resolve critical implementation bottlenecks.</li>\n<li>Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.</li>\n<li>Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock &amp; reset architecture improvements for enabling high speed timing closure, PPA improvements.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. 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You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.</p>\n<p>You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.</p>\n<p>You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.</p>\n<p>You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.</p>\n<p>You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.</p>\n<p>You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15995</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>03/05/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff ASIC Digital Design Engineer</li>\n</ul>\n<ul>\n<li>Staff DFT Engineer</li>\n</ul>\n<ul>\n<li>Staff SoC Testability Engineer</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. 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You enjoy teamwork, learning, and solving complex challenges in digital design.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Define and implement DFT architecture for IP designs</li>\n</ul>\n<ul>\n<li>Perform SCAN insertion and ATPG simulation</li>\n</ul>\n<ul>\n<li>Analyze and improve test coverage</li>\n</ul>\n<ul>\n<li>Develop STA DFT timing constraints</li>\n</ul>\n<ul>\n<li>Prepare DFT integration guidelines for SoC</li>\n</ul>\n<ul>\n<li>Conduct quality checks and FMEDA/DFMEA analysis</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhance product reliability and quality</li>\n</ul>\n<ul>\n<li>Support functional safety standards (ISO26262, FUSA)</li>\n</ul>\n<ul>\n<li>Streamline SoC integration</li>\n</ul>\n<ul>\n<li>Reduce debug cycles and time-to-market</li>\n</ul>\n<ul>\n<li>Mentor peers</li>\n</ul>\n<ul>\n<li>Drive innovation in test methodology</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics or related field</li>\n</ul>\n<ul>\n<li>5+ years DFT design experience</li>\n</ul>\n<ul>\n<li>Expertise in Scan insertion, ATPG, JTAG</li>\n</ul>\n<ul>\n<li>Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)</li>\n</ul>\n<ul>\n<li>Scripting (Perl, TCL, Python) is a plus</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Responsible and collaborative</li>\n</ul>\n<ul>\n<li>Excellent English communication</li>\n</ul>\n<ul>\n<li>Team player and problem solver</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. 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We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4e4a0dc-158","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/dft-staff-engineer-in-hcmc-hanoi/44408/92454718736","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DFT design experience","Scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","Scripting (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:19:13.522Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DFT design experience, Scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), Scripting (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ee07646c-bcc"},"title":"Application Engineering Staff Engineer","description":"<p>We are seeking an experienced Application Engineering Staff Engineer to join our team. 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