We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.

Responsibilities:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

Requirements:

• Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.

Who You Are:

• Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.
• Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
• Collaborative team player who builds productive relationships and networks effectively.
• Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.
• Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.
• Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:

You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.

What You’ll Be Doing:

• Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.

• Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.

• Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.

• Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.

• Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.

• Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.

The Impact You Will Have:

• Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.

• Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.

• Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.

• Drive advancements in deep submicron CMOS technology adoption and integration.

• Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.

• Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.

What You’ll Need:

• MSc in Electrical/Computer Engineering (or equivalent).

• Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.

• Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).

• Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.

• Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.

• Strong skills in UNIX environments, including shell scripting and command-line operations.

• Familiarity with scripting languages such as TCL and Python.

Who You Are:

• Excellent problem-solving, organizational, and communication skills.

• Self-motivated and proactive, with the ability to work independently and as part of a team.

• Effective collaborator who values diverse perspectives and fosters inclusive teamwork.

• Adaptable and open to new challenges, with a commitment to continuous improvement.

• Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.

The Team You’ll Be A Part Of:

You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.

Collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.

Enable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.

Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.

Collaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.

You’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 4 to 7+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

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What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 7 to 10+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

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What you'll do

• Understanding and documenting project scope, requirements, and deliverable dependencies across multiple cross-functional teams.
• Leading regular and ad hoc sync-up meetings with internal teams and customers to align goals, clarify requirements, and drive progress.

What you need

• MSEE/BSEE or MSCE/BSCE with 15+ years' experience in ASIC design and project management.
• Deep understanding of ASIC design flow (RTL to physical implementation) and familiarity with advanced EDA tools (e.g., Synopsys EDA tools).

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