Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nWe are seeking a highly skilled Layout Design Senior Engineer to join our team. As a Layout Design Senior Engineer, you will be responsible for developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below).
\nResponsibilities
\nImpact
\nRequirements
\nTeam
\nYou will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nYou are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification. You thrive in dynamic environments, bringing a collaborative spirit and a growth mindset to every project. You value diversity and inclusion, recognizing the importance of varied perspectives in driving innovation. With a commitment to accountability, you consistently deliver quality results, demonstrating ownership and initiative in your work. Your communication skills,both verbal and written,enable you to effectively share ideas, provide feedback, and partner with cross-functional teams. You are motivated by the opportunity to work on cutting-edge technologies, always seeking to expand your knowledge and make a meaningful impact. Whether solving complex problems or optimizing layouts for performance, power, and area, you approach challenges with creativity and perseverance. You are ready to join Synopsys in shaping the future of silicon IP, contributing to products that empower customers to succeed in the Era of Smart Everything.
\nDeveloping high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.
\nXML job scraping automation by YubHub
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\nYou are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.
\nDesigning and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.
\nDeveloping cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.
\nApplying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.
\nCollaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.
\nConducting design reviews and offering constructive feedback to enhance quality and performance.
\nUtilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.
\nAccelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.
\nEnsuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.
\nEnhancing productivity and efficiency through workflow automation and quality assurance initiatives.
\nDriving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.
\nFostering collaboration across global teams, leading to improved methodologies and best practices.
\nMaintaining the highest standards of quality, compliance, and performance in every design delivered.
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\nAs a Layout Design Senior Engineer, you will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.
\nResponsibilities:
\nImpact:
\nRequirements:
\nTeam:
\nYou will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world's most advanced chips and devices.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
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\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.
\nDeveloping high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.
\nAccelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products. Ensuring robust and reliable IP performance through meticulous layout design and physical verification. Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more. Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader. Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements. Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization. Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally.
\nBTech/MTech degree in Electronics, Electrical, or related engineering discipline. 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below). Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies. Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies. Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation. Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms. Ability to work independently and collaboratively, managing multiple tasks and priorities.
\nAnalytical thinker with strong problem-solving and debugging skills. Self-motivated, accountable, and results-driven. Collaborative team player who fosters trust and open communication. Adaptable and eager to learn new technologies and methodologies. Effective communicator with excellent interpersonal skills. Committed to diversity, inclusion, and continuous improvement.
\nYou will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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\nAs a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.
\nKey responsibilities include:
\nYou will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
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\nYour responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.
\nYou will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.
\nThe impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.
\nTo succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.
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\nAs a Layout Design Senior Engineer, you will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.
\nKey Responsibilities:
\nImpact:
\nRequirements:
\nTeam:
\nYou will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world's most advanced chips and devices.
\nRewards and Benefits:
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\nYou are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.
\nYou will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.
\nYou will apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues. You will collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area.
\nYou will troubleshoot and debug layout challenges, continually improving methodologies and design outcomes. You will document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.
\nAccelerating the integration of advanced silicon IP into customer SoCs, ensuring robust and reliable IP performance through meticulous layout design and physical verification, driving innovation in memory interface IPs, and reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
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