We're seeking a Research Engineer, Machine Learning to join our Frontier AI team. As a key member of our team, you will distill and fine-tune transformer architectures for deployment on edge devices or compute-denied environments. You will propose and prototype LLM-based Agentic systems to solve real-world problems, leveraging the latest state-of-the-art techniques in the field. You will develop and maintain mission-relevant benchmarks and work cross-functionally with different business lines across Anduril to help discover and scope new research problems.
\nIn this role, you will have the opportunity to work on cutting-edge projects, collaborate with a talented team of engineers and researchers, and contribute to the development of impactful technologies. You will also have access to a comprehensive benefits package, including healthcare benefits, income protection, generous time off, and professional development opportunities.
\nThe ideal candidate will have a BS in Computer Science, Machine Learning, Electrical Engineering, or a related field, and 5+ years of experience developing and benchmarking ML algorithms. You will have strong Python skills with experience in ML frameworks such as PyTorch, and be eligible to obtain and maintain an active U.S. Secret security clearance.
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\nThe stack is modern: StarRocks as our primary analytical layer, Flink for processing, DBT for transformation, Airflow for orchestration and various tooling for surfacing insights.
\nYou'll be working on things that matter and are technically interesting:
\nDesign and build data pipelines for large volumes of payment data that are performant, reliable, and correct , not just fast.
\nOwn end-to-end data flows: from ingestion and transformation through to the outputs that Finance, Product, and clients depend on.
\nDrive data quality across your domain with tooling.
\nWork cross-functionally with Product, Finance and enable other Engineering teams via a 'consulting' style model.
\nContribute to how the team works , code review culture, CI/CD standards, ADRs, how we handle incidents , we're building these practices now and senior engineers shape them.
\nHelp onboard and level up engineers around you; there's real opportunity to make an impact here.
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\nAt Mistral AI, we believe in the power of AI to simplify tasks, save time, and enhance learning and creativity. Our technology is designed to integrate seamlessly into daily working life.
\nRole Summary
\nAs an early member of our Partner Team, you will work closely with our Partner and GTM teams to drive the adoption of our state-of-the-art enterprise AI platform and models.
\nResponsibilities
\nPre-Sale & Sales Activities:
\nProduct Implementation & Integration:
\nCustomer & Partner Success & Support:
\nAbout You
\nBenefits
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\nSan Francisco
\nEmployment Type
\nFull time
\nDepartment
\nScaling
\nCompensation
\nThe base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.
\nMore details about our benefits are available to candidates during the hiring process.
\nThis role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.
\nAbout the Team
\nOpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
\nAbout the Role
\nWe’re seeking a Research-Hardware Codesign Engineer to operate at the boundary between model research and silicon/system architecture. You’ll help shape the numerics, architecture, and technology bets of future OpenAI silicon in collaboration with both Research and Hardware.
\nYour work will include debugging gaps between rooflines and reality, writing quantization kernels, derisking numerics via model evals, quantifying system architecture tradeoffs, and implementing novel numeric RTL. This is a hands-on role for people who go looking for hard problems, get to ground truth, and drive it to production. Strong prioritization and clear, honest communication are essential.
\nLocation: San Francisco, CA (Hybrid: 3 days/week onsite)
\nRelocation assistance available.
\nIn this role you will:
\nYou Will Thrive in this Role if:
\n_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements.
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