{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/starrc"},"x-facet":{"type":"skill","slug":"starrc","display":"Starrc","count":5},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5be91f86-bf9"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</p>\n<p>You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</p>\n<p>You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.</p>\n<p>You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.</p>\n<p>You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.</p>\n<p>You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.</p>\n<p>You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.</p>\n<p>You will mentor junior engineers and contribute to team knowledge sharing initiatives.</p>\n<p><strong>Impact</strong></p>\n<p>You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.</p>\n<p>You will advance Synopsys&#39; leadership in IP implementation at cutting-edge technology nodes.</p>\n<p>You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.</p>\n<p>You will facilitate seamless cross-site collaboration, ensuring global project success.</p>\n<p>You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.</p>\n<p>You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electronics, Electrical Engineering, or related field.</p>\n<p>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</p>\n<p>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</p>\n<p>Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.</p>\n<p>Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.</p>\n<p>Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.</p>\n<p>Strong analytical and debugging skills for addressing complex design challenges.</p>\n<p><strong>Team</strong></p>\n<p>You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.</p>\n<p>The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.</p>\n<p>Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5be91f86-bf9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IP implementation","Timing closure","Clock tree synthesis","Skew balancing","Mixed-signal IP integration","Scripting languages (Tcl, Perl, Python)","Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:24.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IP implementation, Timing closure, Clock tree synthesis, Skew balancing, Mixed-signal IP integration, Scripting languages (Tcl, Perl, Python), Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a098910-ad1"},"title":"SRAM Design Engineer, Staff","description":"<p>You will be working as a SRAM Design Engineer, Staff at Synopsys. As a member of our team, you will be responsible for designing and verifying SRAM integrated circuits to ensure robustness and reliability. You will also develop SRAM compilers, including gds and netlist tiling for optimal performance and scalability. Additionally, you will characterize SRAM timing, power, and other critical metrics to meet customer and product requirements. Your work will involve executing compiler quality assurance processes to uphold industry-leading standards. You will also conduct SRAM bitcell analysis and formulate design criteria for advanced memory products. You will utilize EDA tools (XA, hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization. You will collaborate with cross-functional teams to address post-silicon debug and implement improvements. You will also explore and integrate SP/2P/ROM variety designs into SRAM IP solutions.</p>\n<p>Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.</p>\n<p>To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.</p>\n<p>You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a098910-ad1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/sram-design-engineer-staff/44408/91639673872","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SRAM circuit design","CMOS-based block level circuit design","SRAM architectures","SP/2P/ROM variety design","SRAM bitcell analysis","digital circuit design","VLSI process concepts","scripting languages","EDA tools"],"x-skills-preferred":["Python","Tcl/Tk","Perl","Unix shell","XA","hspice","Verilog","Starrc","EMIR"],"datePosted":"2026-03-09T11:06:12.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SRAM circuit design, CMOS-based block level circuit design, SRAM architectures, SP/2P/ROM variety design, SRAM bitcell analysis, digital circuit design, VLSI process concepts, scripting languages, EDA tools, Python, Tcl/Tk, Perl, Unix shell, XA, hspice, Verilog, Starrc, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_937c266a-1fb"},"title":"SRAM Design Engineer, Staff","description":"<p>You are a passionate and detail-oriented engineer eager to make an impact in the memory technology space. You thrive in collaborative environments and are driven by curiosity and a desire to push technological boundaries. Your background in Electrical or Electronic Engineering, complemented by a solid foundation in CMOS and digital circuit design, positions you perfectly to contribute to the world&#39;s largest SRAM circuit and compiler design team.</p>\n<p>You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.</li>\n<li>Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.</li>\n<li>Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.</li>\n<li>Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.</li>\n<li>Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.</li>\n<li>Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.</li>\n<li>Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.</li>\n<li>Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.</li>\n<li>Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.</li>\n<li>Enhance the efficiency and productivity of the design team through automation and process improvements.</li>\n<li>Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.</li>\n<li>Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Master’s degree in Electrical/Electronic Engineering or a related field.</li>\n<li>Strong understanding of CMOS-based block level circuit design and SRAM architectures.</li>\n<li>Solid grasp of digital circuit design and VLSI process concepts.</li>\n<li>Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.</li>\n<li>Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.</li>\n<li>Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.</li>\n<li>Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Innovative thinker with a strong desire to learn and explore new technologies.</li>\n<li>Detail-oriented and analytical, capable of tackling complex technical challenges.</li>\n<li>Collaborative team player who values diverse perspectives and open communication.</li>\n<li>Effective communicator able to present ideas clearly and work across global teams.</li>\n<li>Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.</li>\n<li>Proactive problem solver who takes ownership of projects and drives results.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_937c266a-1fb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/sram-design-engineer-staff/44408/91675562416","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS-based block level circuit design","SRAM architectures","digital circuit design","VLSI process concepts","scripting languages","EDA tools","SRAM circuit design","bitcell analysis","design criteria development"],"x-skills-preferred":["Python","Tcl/Tk","Perl","Unix shell","XA","Hspice","Verilog","Starrc","EMIR"],"datePosted":"2026-03-09T11:02:55.213Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS-based block level circuit design, SRAM architectures, digital circuit design, VLSI process concepts, scripting languages, EDA tools, SRAM circuit design, bitcell analysis, design criteria development, Python, Tcl/Tk, Perl, Unix shell, XA, Hspice, Verilog, Starrc, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c79f57de-0e6"},"title":"R&D Engineering-Sign Off, Principal Engineer","description":"<p>As a member of the IP Digital Design Methodology team, you will work with global teams to define best in class ASIC design standards and flows and assist IP development teams. You will be involved with next generation SerDes and Memory interface controllers, PHYs, and subsystems.</p>\n<p>You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.</p>\n<p>Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.</p>\n<p>You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO&#39;s.</p>\n<p>You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.</p>\n<p>You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.</p>\n<p>You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.</p>\n<p>You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.</p>\n<p>You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.</p>\n<p>You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.</p>\n<p>You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c79f57de-0e6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/r-and-d-engineering-sign-off-principal-engineer-15192/44408/91625669328","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$166000-$249000","x-skills-required":["ASIC Digital Signoff Engineer","EM and IR flows","High-speed digital IP cores and/or SOCs development","Static Timing Analysis (STA)","Power Analysis","EM/IR for advanced node designs","Synopsys tools","High-speed interface protocols"],"x-skills-preferred":["StarRC","ICV","HDMI","MIPI","PCIe","SATA","Ethernet","USB","DP","DDR"],"datePosted":"2026-03-09T11:02:21.865Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Digital Signoff Engineer, EM and IR flows, High-speed digital IP cores and/or SOCs development, Static Timing Analysis (STA), Power Analysis, EM/IR for advanced node designs, Synopsys tools, High-speed interface protocols, StarRC, ICV, HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, DDR","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":166000,"maxValue":249000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_97deabd5-0f0"},"title":"Senior Physical Design Engineer","description":"<p>You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.</p>\n<ul>\n<li>Demonstrating the unique advantages and capabilities of Synopsys&#39; industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<p>Bachelor&#39;s and/or Master&#39;s degree in Electrical Engineering or a related field.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_97deabd5-0f0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer-rtl-to-gds-fusion-compiler/44408/89670252864","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$157,000-$235,000","x-skills-required":["8-10 years of experience with the complete RTL-to-GDS physical design flow","Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus","In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies"],"x-skills-preferred":["Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.","Excellent communicator, able to clearly articulate technical concepts to diverse audiences."],"datePosted":"2025-12-22T11:58:13.476Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brackley"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"8-10 years of experience with the complete RTL-to-GDS physical design flow, Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus, In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies, Innovative, resourceful, and proactive in driving technical solutions and continuous improvement., Excellent communicator, able to clearly articulate technical concepts to diverse audiences.","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}}]}