Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nYou are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.
\nDesigning and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.
\nDeveloping cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.
\nApplying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.
\nCollaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.
\nConducting design reviews and offering constructive feedback to enhance quality and performance.
\nUtilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.
\nAccelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.
\nEnsuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.
\nEnhancing productivity and efficiency through workflow automation and quality assurance initiatives.
\nDriving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.
\nFostering collaboration across global teams, leading to improved methodologies and best practices.
\nMaintaining the highest standards of quality, compliance, and performance in every design delivered.
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\nAs a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.
\nKey responsibilities include:
\nYou will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
\nXML job scraping automation by YubHub
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