{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/sta-concepts"},"x-facet":{"type":"skill","slug":"sta-concepts","display":"Sta Concepts","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_eb9218fe-189"},"title":"Timing Analog Mixed Signal Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Develop accurate timing models for macros used in multi-die designs.</li>\n<li>Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.</li>\n<li>Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.</li>\n<li>Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.</li>\n<li>Perform STA (Static Timing Analysis) using industry-standard EDA tools.</li>\n<li>Support constraint development and validation for timing sign-off.</li>\n<li>Collaborate with design, verification, and physical implementation teams to resolve timing issues.</li>\n<li>Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA)</li>\n</ul>\n<p><strong>Authority:</strong></p>\n<ul>\n<li>Normally receives detailed instructions on all work.</li>\n<li>Follows standard practices and procedures in analyzing situations or data from which answers can be readily obtained.</li>\n<li>Applies company policies and procedures to resolve routine issues.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.</li>\n<li>1-2 year working experience in similar roles or fresh graduates</li>\n</ul>\n<p>(Fresh graduates are also welcomed and offered the on-the-job training to adapt the position&#39;s requirements.)</p>\n<ul>\n<li>Basic understanding of timing analysis, SPICE simulation, and STA concepts.</li>\n<li>Experience with scripting languages such as Python and TCL for automation and data processing.</li>\n<li>Familiarity with EDA tools for timing characterization and verification.</li>\n<li>Strong problem-solving abilities and keen attention to detail.</li>\n<li>Good verbal and written English communication skills.</li>\n<li>Highly responsible and self-motivated, with a strong sense of ownership over your work.</li>\n<li>Collaborative team player, open to feedback and eager to learn from others.</li>\n<li>Detail-oriented and methodical, always striving for accuracy and quality.</li>\n<li>Effective communicator, able to articulate technical concepts clearly.</li>\n<li>Adaptable and resilient in the face of new challenges or shifting priorities.</li>\n<li>Enthusiastic about contributing to a diverse, inclusive, and innovative workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join the Synopsys UCIe Design Team, a dynamic group of engineers specializing in advanced chiplet interconnect and analog mixed-signal technologies. This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.</p>\n<p>As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits:</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine around the office can be like</p>\n<p>\\ Explore Ho Chi Minh City</p>\n<p>View Map</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_eb9218fe-189","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/timing-analog-mixed-signal-design-engineer-hcmc/44408/92554331200","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["timing analysis","SPICE simulation","STA concepts","Python","TCL","EDA tools","timing characterization","verification"],"x-skills-preferred":["problem-solving","detail-oriented","effective communication","adaptability","resilience"],"datePosted":"2026-03-09T11:00:31.108Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"timing analysis, SPICE simulation, STA concepts, Python, TCL, EDA tools, timing characterization, verification, problem-solving, detail-oriented, effective communication, adaptability, resilience"}]}