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MHP values diversity and recognizes the importance of healthy, tight-knit communities and sustainable environmental changes.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8f33cca8-af4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"MHP","sameAs":"http://www.mhp.com/","logo":"https://logos.yubhub.co/mhp.com.png"},"x-apply-url":"https://jobs.porsche.com/index.php?ac=jobad&id=20432","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["digital product development","cloud- and web-based applications","agile software development lifecycles","ASPICE standards","V-Cycle development process","system engineering","architecture decision frameworks","modeling methods","foundational cloud architecture expertise","AWS","Azure"],"x-skills-preferred":["strong analytical and conceptual thinking skills","experience with architecture decision frameworks and modeling methods","ability to communicate effectively in written and spoken English"],"datePosted":"2026-04-22T17:33:42.310Z","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Consulting","skills":"digital product development, cloud- and web-based applications, agile software development lifecycles, ASPICE standards, V-Cycle development process, system engineering, architecture decision frameworks, modeling methods, foundational cloud architecture expertise, AWS, Azure, strong analytical and conceptual thinking skills, experience with architecture decision frameworks and modeling methods, ability to communicate effectively in written and spoken English"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bb1e67f5-f1d"},"title":"Senior Account Executive","description":"<p><strong>Role Description</strong></p>\n<p>As a Senior Account Executive on the Growth team, you will play a key role in helping Dropbox evolve how we go to market as we expand into newer products like Dash. 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We unify calling, messaging, meetings, and contact center on a single platform - powered by AI that understands every conversation in real time.</p>\n<p>More than 70,000 companies around the globe, including WeWork, Asana, NASDAQ, AAA Insurance, COMPASS Realty, Uber, Randstad, and Tractor Supply, rely on Dialpad to build stronger customer connections using real-time, AI-driven insights.</p>\n<p>We’re now leading the shift to Agentic AI: intelligent agents that don’t just analyse conversations but take action by automating workflows, resolving customer issues, and accelerating revenue in real time. Our DAART initiative (Dialpad Agentic AI in Real Time) is redefining what a communications platform can do.</p>\n<p>Visit dialpad.com to learn more.</p>\n<p>Being a Dialer</p>\n<p>At Dialpad, AI isn’t just a feature; it’s how our teams do their best work every day. We put powerful AI tools in every employee’s hands so they can move faster, think bigger, and achieve more.</p>\n<p>We believe every conversation matters. And we’ve built the platform that turns those conversations into insight and action, for our customers and ourselves.</p>\n<p>We look for people who are intensely curious and hold themselves to a high bar. Our ambition is significant, and achieving it requires a team that operates at the highest level.</p>\n<p>We seek individuals who embody our core traits: Scrappy, Curious, Optimistic, Persistent, and Empathetic.</p>\n<p>Your Role</p>\n<p>As a Client Account Executive for Mid-Market at Dialpad, you will be responsible for providing best-in-class strategic account management across a portfolio of existing Dialpad customers while growing year-over-year revenue.</p>\n<p>Serving as a consultant to the client, the CAE will demonstrate the value of what&#39;s possible through the implementation of additional Dialpad product suite offerings.</p>\n<p>The CAE will develop and execute a sales strategy for their book of business.</p>\n<p>They will be responsible for meeting or exceeding sales and revenue goals and objectives, managing overall customer relationships, and ensuring customer satisfaction.</p>\n<p>The CAE is ultimately responsible for ensuring our customers continually realise the value of their accounts, driving positive outcomes for both the customer and Dialpad.</p>\n<p>This position reports to our Sales Manager and has the opportunity to be based in our Denver Office.</p>\n<p>What you’ll do</p>\n<ul>\n<li>Focused on a portfolio of Mid-Market customers, the Mid-Market CAE will own the sales process from start to finish.</li>\n</ul>\n<p>You will work closely with Sales Managers, Sales Engineers, Customer Success, Professional Services, Marketing, and Dialpad Partners to grow our existing customer base.</p>\n<ul>\n<li>Create a territory account plan for how you will consistently achieve your quarterly goals and activity metrics.</li>\n</ul>\n<ul>\n<li>Cultivate relationships with our customers to gain insight into customer strategy and expansion plans,aligning our product suite with their goals.</li>\n</ul>\n<ul>\n<li>Generate a pipeline and drive an efficient sales process.</li>\n</ul>\n<ul>\n<li>Achieve or exceed quarterly revenue goals.</li>\n</ul>\n<ul>\n<li>Serve as a Dialpad expert, becoming a trusted advisor and resource for your customers.</li>\n</ul>\n<ul>\n<li>Identify customers who would be a good fit for the Customer Advisory Board and Executive Sponsor Program.</li>\n</ul>\n<p>Become an advocate for the customer to return to Dialpad.</p>\n<p>Skills you’ll bring</p>\n<ul>\n<li>3-5+ years of experience in a closing sales role.</li>\n</ul>\n<p>Previous Mid-Market experience preferred.</p>\n<ul>\n<li>Proven success in meeting and exceeding revenue targets with either a New Business or Account Management background.</li>\n</ul>\n<ul>\n<li>Ability to communicate, present, and influence key stakeholders and decision-makers.</li>\n</ul>\n<ul>\n<li>Experience with solution-selling techniques such as SPICED and/or MEDDICC.</li>\n</ul>\n<ul>\n<li>Experience providing timely and accurate forecasts to sales leadership.</li>\n</ul>\n<ul>\n<li>Excellent time management skills with the ability to track numerous details.</li>\n</ul>\n<ul>\n<li>Willingness to travel to customer locations or events as needed.</li>\n</ul>\n<ul>\n<li>SaaS sales background required, with bonus points for UCaaS/CCaaS.</li>\n</ul>\n<ul>\n<li>Experienced with CRM software (e.g., Salesforce) and GSuite tools (Google Sheets).</li>\n</ul>\n<p>Why Join Dialpad</p>\n<p>Work at the center of the AI transformation in business communications</p>\n<p>Build and ship agentic AI products that are redefining how companies operate</p>\n<p>Join a team where AI amplifies every employee’s impact</p>\n<p>Competitive salary, comprehensive benefits, and real opportunities for growth</p>\n<p>We believe in investing in our people. Dialpad offers competitive benefits and perks, cutting-edge AI tools, and a robust training program that help you reach your full potential.</p>\n<p>We have designed our offices to be inclusive, offering a vibrant environment to cultivate collaboration and connection.</p>\n<p>Our exceptional culture, repeatedly recognised as a Great Place to Work, ensures that every employee feels valued and empowered to contribute to our collective success.</p>\n<p>Don’t meet every single requirement? If you’re excited about this role and possess the fundamental traits, drive, and strong ambition we seek, but your experience doesn’t meet every qualification, we encourage you to apply.</p>\n<p>Dialpad is an equal-opportunity employer. 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We unify calling, messaging, meetings, and contact center on a single platform - powered by AI that understands every conversation in real time.</p>\n<p>Our Customers ------------ More than 70,000 companies around the globe, including WeWork, Asana, NASDAQ, AAA Insurance, COMPASS Realty, Uber, Randstad, and Tractor Supply, rely on Dialpad to build stronger customer connections using real-time, AI-driven insights.</p>\n<p>Your Role -------- As a Client Account Executive for Mid-Market at Dialpad, you will be responsible for providing best-in-class strategic account management across a portfolio of existing Dialpad customers while growing year-over-year revenue.</p>\n<p>Responsibilities ---------------</p>\n<ul>\n<li>Focused on a portfolio of Mid-Market customers, the Mid-Market CAE will own the sales process from start to finish.</li>\n<li>Create a territory account plan for how you will consistently achieve your quarterly goals and activity metrics.</li>\n<li>Cultivate relationships with our customers to gain insight into customer strategy and expansion plans,aligning our product suite with their goals.</li>\n<li>Generate pipeline and drive an efficient sales process.</li>\n<li>Achieve or exceed quarterly revenue goals.</li>\n<li>Serve as a Dialpad expert and become a trusted advisor and resource for your customers.</li>\n</ul>\n<p>Requirements -----------</p>\n<ul>\n<li>3-5+ years of experience in a closing sales role.</li>\n<li>Proven success in meeting and exceeding revenue targets with either a New Business or Account Management background.</li>\n<li>Ability to communicate, present, and influence key stakeholders and decision-makers.</li>\n<li>Experience with solution selling techniques such as SPICED and/or MEDDICC.</li>\n<li>Experience providing timely and accurate forecasts to sales leadership.</li>\n<li>Excellent time management skills with the ability to track numerous details.</li>\n<li>Willingness to travel to customer locations or events as needed.</li>\n<li>SaaS sales background required, with bonus points for UCaaS/CCaaS.</li>\n<li>Experienced with CRM software (e.g., Salesforce) and GSuite tools (Google Sheets).</li>\n</ul>\n<p>Why Join Dialpad -------------- We believe in investing in our people. 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modifications.</li>\n</ul>\n<ul>\n<li>Collaborate closely with engineering teams and stakeholders to integrate Business Manager capabilities into broader infrastructure and use cases across Reddit.</li>\n</ul>\n<p>Qualifications:</p>\n<ul>\n<li>7+ years software engineering experience building production services at scale.</li>\n</ul>\n<ul>\n<li>Ads domain experience.</li>\n</ul>\n<ul>\n<li>Excellent communication skills to collaborate with a service-oriented team and company.</li>\n</ul>\n<ul>\n<li>Experience coordinating large-scale, cross-functional efforts that span different teams, and driving alignment between diverse stakeholders.</li>\n</ul>\n<ul>\n<li>Experience in solving complex system scaling and latency performance problems.</li>\n</ul>\n<ul>\n<li>Strong proficiency in one or more: Go, Python; plus experience with service frameworks (gRPC/Thrift) and API design.</li>\n</ul>\n<ul>\n<li>Experience with distributed systems, data modeling, and event-driven architectures (e.g., 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You are adept at conflict resolution and possess strong customer-facing skills, making you an invaluable asset to any high-performing team.</p>\n<p>What You’ll Be Doing:</p>\n<p>Managing analog and mixed-signal IP projects from specifications to silicon.\nInteracting with customers to guide them and help adapt our solutions to their needs.\nHandling customer queries and debugging problems efficiently.\nAligning with and improving established design processes.\nInterfacing with internal and external stakeholders to ensure high engagement levels.\nCollaborating with a global team to co-develop Analog Full Custom IPs such as GPIOs, I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG, and more.</p>\n<p>The Impact You Will Have:</p>\n<p>Driving the integration of advanced capabilities into System on Chips (SoCs).\nEnabling customers to meet unique performance, power, and size requirements.\nAccelerating the time-to-market for differentiated products with reduced risk.\nEnhancing the design and development of high-performance silicon IP.\nImproving customer satisfaction through efficient problem-solving and support.\nContributing to the continuous innovation and technological advancements at Synopsys.</p>\n<p>What You’ll Need:</p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering or a related field from a reputed institution.\n12+ years of industry experience in analog and mixed-signal circuit design.\nProven experience in managing projects from specifications to silicon.\nStrong understanding of circuit design fundamentals, device physics, and technology effects.\nProficiency in spice simulations and various sub-micron design methodologies.</p>\n<p>Who You Are:</p>\n<p>A proactive team player with strong written and verbal communication skills.\nHigh energy individual with the ability to go the extra mile.\nCreative and flexible personality with excellent customer-facing skills.\nDemonstrates good analysis and problem-solving skills.\nAdept at conflict resolution and fostering collaboration among team members.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will be part of a strong development team specializing in GPIOs, Specialty IOs, and General Purpose Analog IPs. The team is distributed globally, bringing together experienced professionals from various sites. Together, you will co-develop high-performance analog full custom IPs and work on projects that push the boundaries of technology.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Develop and specify SERDES transceiver architectures and sub-blocks based on standards.</li>\n<li>Design, simulate, and verify high-speed analog circuits for optimal power and performance.</li>\n<li>Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.</li>\n<li>Present technical results internally and externally to customers and industry groups.</li>\n<li>Oversee physical layout to address parasitics and reliability concerns.</li>\n<li>Document features and test plans, and support post-silicon analysis and updates.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Advance industry-leading SERDES IP for next-generation SoCs.</li>\n<li>Enhance product differentiation and customer value.</li>\n<li>Streamline design processes for quality and time-to-market.</li>\n<li>Mentor junior team members and share best practices.</li>\n<li>Influence technical direction and innovation at Synopsys.</li>\n<li>Support customer success and product reliability.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.</li>\n<li>Expertise in transistor-level CMOS design and SERDES sub-circuits.</li>\n<li>Proficiency with schematic, layout, and verification tools; SPICE simulators.</li>\n<li>Experience with scripting languages (Verilog-A, TCL, Python, etc.).</li>\n<li>Strong communication and documentation skills.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Technical leader and mentor</li>\n<li>Collaborative and proactive</li>\n<li>Analytical and detail-oriented</li>\n<li>Adaptable and innovative</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4815342e-ce8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/kanata/analog-design-engineer/44408/93286401584","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["High-speed SERDES IP","Transistor-level CMOS design","SERDES sub-circuits","Schematic, layout, and verification tools","SPICE simulators","Scripting languages (Verilog-A, TCL, Python, etc.)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:26.629Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Kanata"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"High-speed SERDES IP, Transistor-level CMOS design, SERDES sub-circuits, Schematic, layout, and verification tools, SPICE simulators, Scripting languages (Verilog-A, TCL, Python, etc.)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2ce8fb82-628"},"title":"R&D Engineering, Sr Staff Engineer- 16038","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. 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Collaborating with cross-functional teams to align project deliverables with business objectives. Contributing to the technical direction and problem-solving efforts within the engineering group. Sharing knowledge and supporting the professional growth of team members through technical mentorship.</p>\n<p><strong>Impact:</strong></p>\n<p>Advance our product portfolio with innovative solutions addressing market demands. Improve the efficiency and effectiveness of engineering development workflows. Solve complex engineering challenges, contributing to successful project outcomes. Support the growth and technical development of colleagues through guidance and collaboration. Contribute to Synopsys&#39; success by delivering high-quality products on schedule. Help foster a culture of innovation and continuous improvement within the engineering team.</p>\n<p><strong>Requirements:</strong></p>\n<p>Bachelor&#39;s or master&#39;s degree in Electrical Engineering, Computer Science, or a related field. Significant experience in analog design and memory compiler flow. Proficiency in Python and Hspice. Strong problem-solving and technical skills. Ability to work collaboratively and communicate effectively within and across teams.</p>\n<p><strong>Team:</strong></p>\n<p>You will be part of a dynamic and innovative engineering team at the forefront of high-performance silicon chip and software development. Our team relentlessly pushes technology boundaries, delivering solutions that drive the Era of Pervasive Intelligence. We collaborate closely to ensure our products meet the highest standards of quality and performance.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2ce8fb82-628","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-sr-staff-engineer-16038/44408/93015824912","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$165000-$248000","x-skills-required":["analog design","memory compiler flow","Circuit design","Memory architecture","Python","Hspice"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:07.406Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog design, memory compiler flow, Circuit design, Memory architecture, Python, Hspice","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":165000,"maxValue":248000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e14d730c-676"},"title":"Analog Design, Staff Engineer - SERDES","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p><em>big_They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</em></p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Staff Engineer in our Analog Design team, you will be responsible for designing and developing full custom analog circuit macros for high-speed SERDES PHY IP.</p>\n<p>Your responsibilities will include designing and developing full custom analog circuit macros for high-speed SERDES PHY IP, including transceivers, voltage/current-mode drivers, PLLs, DLLs, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, and clock data recovery circuits.</p>\n<p>You will also collaborate with cross-functional teams locally and globally to refine circuit implementations and achieve optimal power, area, and performance targets.</p>\n<p>In addition, you will ensure analog sub-block performance adheres to SerDes standards and architecture specification documents.</p>\n<p>You will lead verification strategies using advanced simulator features to guarantee the highest quality design outcomes.</p>\n<p>You will oversee physical layout processes to minimize parasitic effects, device stress, and process variations.</p>\n<p>You will present simulation data for peer and customer reviews, and document design features and test plans.</p>\n<p>You will consult on electrical characterization and support the integration of your circuit within the SerDes IP product.</p>\n<p>You will handcraft high-performance clock and data paths using digital/CMOS logic cells and verify timing margins with SPICE and STA tools.</p>\n<p>You will address ESD and latch-up design verification, crosstalk coupling impacts, and ensure robust mixed-signal analog design.</p>\n<p>The impact you will have includes accelerating development of high-performance silicon chips critical to emerging technologies like AI, IoT, and 5G.</p>\n<p>You will optimize chip designs for power, cost, and performance, helping customers reduce project schedules by months.</p>\n<p>You will advance Synopsys&#39; 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a UCIe Analog Design Senior Engineer at Synopsys, you will design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...</p>\n<p>You will analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.</p>\n<p>You will work closely with layout engineers to make sure layout quality. Perform post layout verifications.</p>\n<p>You will perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.</p>\n<p>You will design analysis  and solve problems of noise, margin, signal integrity, power integrity.</p>\n<p>You will complete all design quality checks and data quality checks</p>\n<p>You will do design reviews across global team</p>\n<p>You will work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.</p>\n<p>You will train for fresh engineers and interns</p>\n<p>The ideal candidate will have a BS/MS in Electronics Engineering, Electromechanics, Telecommunications.</p>\n<p>They should have 0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.</p>\n<p>They should have solid knowledge of CMOS Analog design knowledge and techniques</p>\n<p>They should have solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso</p>\n<p>They should have solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim...</p>\n<p>They should have good understanding of layout effects on circuit performance.</p>\n<p>They should have experienced with writing design review presentations and circuit verification reports</p>\n<p>They should have good English communication both verbally and in writing</p>\n<p>They should be a great team player, willing to support others.</p>\n<p>They should be highly responsible, result oriented.</p>\n<p>They should be self-motivated and highly enthusiasm in technology and solving problems</p>\n<p>Leadership skill and experience is a plus</p>\n<p>Familiar with high speed analog designs, IO designs, PLL/DLL is a plus</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cf9481bc-553","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/ucie-analog-design-senoir-engineer/44408/92607813456","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["BS/MS in Electronics Engineering, Electromechanics, Telecommunications","0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design","Solid knowledge of CMOS Analog design knowledge and techniques","Solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso","Solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim..."],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:42.161Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"BS/MS in Electronics Engineering, Electromechanics, Telecommunications, 0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design, Solid knowledge of CMOS Analog design knowledge and techniques, Solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso, Solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim..."},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b215ccd0-321"},"title":"ASIC Digital Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>This role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.</p>\n<p>Key responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.</p>\n<p>The ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.</p>\n<p>As a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.</p>\n<p>In this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.</p>\n<p>Synopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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shell"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_84adbba8-30e"},"title":"SerDes Analog Behavioral Modeling & Validation Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced SerDes Analog Behavioral Modeling &amp; Validation Engineer to join our team.</p>\n<p>As a key member of our engineering team, you will be responsible for developing and refining behavioral models for high-speed SerDes blocks, collaborating with analog teams for SPICE-vs-model correlation and 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You have a strong technical background and excellent problem-solving skills. Your ability to communicate effectively and work well with diverse teams makes you an asset to any project. You are dedicated to continuous learning and development, and your passion for technology drives you to stay ahead of industry trends. You are adaptable, detail-oriented, and committed to delivering high-quality results.</p>\n<p><strong>Team</strong></p>\n<p>You will be working with a group of highly-skilled, supportive, and globally spread-out teams. Our team is dedicated to driving innovation and excellence in SIPI analysis of high speed interface IP&#39;s. We value collaboration, continuous learning, and a can-do attitude. Together, we strive to develop the most advanced technologies and deliver exceptional results for our clients.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6bd5b497-557","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/signal-and-power-integrity-staff-engineer/44408/92599737632","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["Transmission line theory","Time/frequency-domain analysis","SPICE","3D field solvers","DDR","HBM","UCIE","PCIe/Ethernet interfaces","Python","TCL","Windows","Linux"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:20:46.261Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Transmission line theory, Time/frequency-domain analysis, SPICE, 3D field solvers, DDR, HBM, UCIE, PCIe/Ethernet interfaces, Python, TCL, Windows, Linux"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a098910-ad1"},"title":"SRAM Design Engineer, Staff","description":"<p>You will be working as a SRAM Design Engineer, Staff at Synopsys. As a member of our team, you will be responsible for designing and verifying SRAM integrated circuits to ensure robustness and reliability. You will also develop SRAM compilers, including gds and netlist tiling for optimal performance and scalability. Additionally, you will characterize SRAM timing, power, and other critical metrics to meet customer and product requirements. Your work will involve executing compiler quality assurance processes to uphold industry-leading standards. You will also conduct SRAM bitcell analysis and formulate design criteria for advanced memory products. You will utilize EDA tools (XA, hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization. You will collaborate with cross-functional teams to address post-silicon debug and implement improvements. You will also explore and integrate SP/2P/ROM variety designs into SRAM IP solutions.</p>\n<p>Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.</p>\n<p>To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.</p>\n<p>You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a098910-ad1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/sram-design-engineer-staff/44408/91639673872","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SRAM circuit design","CMOS-based block level circuit design","SRAM architectures","SP/2P/ROM variety design","SRAM bitcell analysis","digital circuit design","VLSI process concepts","scripting languages","EDA tools"],"x-skills-preferred":["Python","Tcl/Tk","Perl","Unix shell","XA","hspice","Verilog","Starrc","EMIR"],"datePosted":"2026-03-09T11:06:12.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SRAM circuit design, CMOS-based block level circuit design, SRAM architectures, SP/2P/ROM variety design, SRAM bitcell analysis, digital circuit design, VLSI process concepts, scripting languages, EDA tools, Python, Tcl/Tk, Perl, Unix shell, XA, hspice, Verilog, Starrc, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5f4e85a9-296"},"title":"Staff Analog Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15391</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.</p>\n<p>You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.</p>\n<p>Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</li>\n</ul>\n<ul>\n<li>Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</li>\n</ul>\n<ul>\n<li>Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</li>\n</ul>\n<ul>\n<li>Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</li>\n</ul>\n<ul>\n<li>Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.</li>\n</ul>\n<ul>\n<li>Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.</li>\n</ul>\n<ul>\n<li>Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.</li>\n</ul>\n<ul>\n<li>Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.</li>\n</ul>\n<ul>\n<li>Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.</li>\n</ul>\n<ul>\n<li>Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</li>\n</ul>\n<ul>\n<li>Proven expertise with FinFET technologies and CMOS tape-outs.</li>\n</ul>\n<ul>\n<li>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</li>\n</ul>\n<ul>\n<li>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</li>\n</ul>\n<ul>\n<li>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</li>\n</ul>\n<ul>\n<li>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</li>\n</ul>\n<ul>\n<li>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</li>\n</ul>\n<ul>\n<li>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</li>\n</ul>\n<ul>\n<li>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</li>\n</ul>\n<ul>\n<li>Excellent communication and documentation skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and open-minded, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Detail-oriented and thorough, with a commitment to delivering high-quality results.</li>\n</ul>\n<ul>\n<li>Analytical thinker with strong problem-solving abilities and a proactive approach.</li>\n</ul>\n<ul>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in fast-paced, dynamic environments.</li>\n</ul>\n<ul>\n<li>Committed to fostering an inclusive, innovative, and supportive workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a world-class analog and mixed-signal R&amp;D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and patern</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5f4e85a9-296","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/staff-analog-design-engineer/44408/92076328848","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability","schematic entry","physical layout","design verification tools","SPICE simulators","scripting languages","system-level budgeting","signal integrity"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:05:32.632Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, schematic entry, physical layout, design verification tools, SPICE simulators, scripting languages, system-level budgeting, signal integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_937c266a-1fb"},"title":"SRAM Design Engineer, Staff","description":"<p>You are a passionate and detail-oriented engineer eager to make an impact in the memory technology space. You thrive in collaborative environments and are driven by curiosity and a desire to push technological boundaries. Your background in Electrical or Electronic Engineering, complemented by a solid foundation in CMOS and digital circuit design, positions you perfectly to contribute to the world&#39;s largest SRAM circuit and compiler design team.</p>\n<p>You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.</li>\n<li>Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.</li>\n<li>Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.</li>\n<li>Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.</li>\n<li>Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.</li>\n<li>Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.</li>\n<li>Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.</li>\n<li>Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.</li>\n<li>Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.</li>\n<li>Enhance the efficiency and productivity of the design team through automation and process improvements.</li>\n<li>Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.</li>\n<li>Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Master’s degree in Electrical/Electronic Engineering or a related field.</li>\n<li>Strong understanding of CMOS-based block level circuit design and SRAM architectures.</li>\n<li>Solid grasp of digital circuit design and VLSI process concepts.</li>\n<li>Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.</li>\n<li>Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.</li>\n<li>Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.</li>\n<li>Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Innovative thinker with a strong desire to learn and explore new technologies.</li>\n<li>Detail-oriented and analytical, capable of tackling complex technical challenges.</li>\n<li>Collaborative team player who values diverse perspectives and open communication.</li>\n<li>Effective communicator able to present ideas clearly and work across global teams.</li>\n<li>Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.</li>\n<li>Proactive problem solver who takes ownership of projects and drives results.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_937c266a-1fb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/sram-design-engineer-staff/44408/91675562416","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS-based block level circuit design","SRAM architectures","digital circuit design","VLSI process concepts","scripting languages","EDA tools","SRAM circuit design","bitcell analysis","design criteria development"],"x-skills-preferred":["Python","Tcl/Tk","Perl","Unix shell","XA","Hspice","Verilog","Starrc","EMIR"],"datePosted":"2026-03-09T11:02:55.213Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS-based block level circuit design, SRAM architectures, digital circuit design, VLSI process concepts, scripting languages, EDA tools, SRAM circuit design, bitcell analysis, design criteria development, Python, Tcl/Tk, Perl, Unix shell, XA, Hspice, Verilog, Starrc, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_eb9218fe-189"},"title":"Timing Analog Mixed Signal Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Develop accurate timing models for macros used in multi-die designs.</li>\n<li>Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.</li>\n<li>Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.</li>\n<li>Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.</li>\n<li>Perform STA (Static Timing Analysis) using industry-standard EDA tools.</li>\n<li>Support constraint development and validation for timing sign-off.</li>\n<li>Collaborate with design, verification, and physical implementation teams to resolve timing issues.</li>\n<li>Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA)</li>\n</ul>\n<p><strong>Authority:</strong></p>\n<ul>\n<li>Normally receives detailed instructions on all work.</li>\n<li>Follows standard practices and procedures in analyzing situations or data from which answers can be readily obtained.</li>\n<li>Applies company policies and procedures to resolve routine issues.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.</li>\n<li>1-2 year working experience in similar roles or fresh graduates</li>\n</ul>\n<p>(Fresh graduates are also welcomed and offered the on-the-job training to adapt the position&#39;s requirements.)</p>\n<ul>\n<li>Basic understanding of timing analysis, SPICE simulation, and STA concepts.</li>\n<li>Experience with scripting languages such as Python and TCL for automation and data processing.</li>\n<li>Familiarity with EDA tools for timing characterization and verification.</li>\n<li>Strong problem-solving abilities and keen attention to detail.</li>\n<li>Good verbal and written English communication skills.</li>\n<li>Highly responsible and self-motivated, with a strong sense of ownership over your work.</li>\n<li>Collaborative team player, open to feedback and eager to learn from others.</li>\n<li>Detail-oriented and methodical, always striving for accuracy and quality.</li>\n<li>Effective communicator, able to articulate technical concepts clearly.</li>\n<li>Adaptable and resilient in the face of new challenges or shifting priorities.</li>\n<li>Enthusiastic about contributing to a diverse, inclusive, and innovative workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join the Synopsys UCIe Design Team, a dynamic group of engineers specializing in advanced chiplet interconnect and analog mixed-signal technologies. This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.</p>\n<p>As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits:</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine around the office can be like</p>\n<p>\\ Explore Ho Chi Minh City</p>\n<p>View Map</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_eb9218fe-189","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/timing-analog-mixed-signal-design-engineer-hcmc/44408/92554331200","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["timing analysis","SPICE simulation","STA concepts","Python","TCL","EDA tools","timing characterization","verification"],"x-skills-preferred":["problem-solving","detail-oriented","effective communication","adaptability","resilience"],"datePosted":"2026-03-09T11:00:31.108Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"timing analysis, SPICE simulation, STA concepts, Python, TCL, EDA tools, timing characterization, verification, problem-solving, detail-oriented, effective communication, adaptability, resilience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e173e34d-507"},"title":"Electronic Hardware Design Engineer","description":"<p>Your job is to design next-generation automotive ECUs, inverters, and BMS. You will work with analog and digital hardware design, using LTspice or similar SPICE software for circuit simulation and analysis. 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simulation data to peers and customers, and documenting design features and test plans.</p>\n<p><strong>What you need</strong></p>\n<ul>\n<li>MSc with 5+ years in analog IC design</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bd560ba5-e45","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/markham/staff-analog-design-engineer-dte-13613/44408/89385354672","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"contract","x-salary-range":null,"x-skills-required":["analog IC design","SerDes sub-circuits","schematic","layout","verification tools","SPICE simulation","scripting","communication","documentation"],"x-skills-preferred":["transistor-level CMOS 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As a Staff Analog and Mixed Signal IC Designer, you will be responsible for designing and developing high-speed analog and mixed-signal ICs. You will work closely with our cross-functional teams to develop and implement new design methodologies and tools.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Design and develop high-speed analog and mixed-signal ICs</li>\n<li>Collaborate with cross-functional teams to develop and implement new design methodologies and tools</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or related field</li>\n<li>3+ years of experience in analog and mixed-signal IC design</li>\n<li>Strong understanding of analog and mixed-signal circuit design and analysis</li>\n<li>Experience with SPICE simulators and EDA tools</li>\n<li>Strong communication and teamwork skills</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e344db05-e19","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/markham/staff-analog-and-mixed-signal-ic-designer-15315/44408/92214309312","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog and mixed-signal IC design","SPICE simulators","EDA tools"],"x-skills-preferred":["circuit design and analysis","communication and teamwork skills"],"datePosted":"2026-03-06T07:26:51.053Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Markham"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog and mixed-signal IC design, SPICE simulators, EDA tools, circuit design and analysis, communication and teamwork skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b536cc5b-c88"},"title":"Analog IC Design Engineer","description":"<p>We are seeking an experienced Analog IC Design Engineer to join our team. As an Analog IC Design Engineer, you will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Develop and specify SERDES transceiver architectures and sub-blocks based on standards.</li>\n<li>Design, simulate, and verify high-speed analog circuits for optimal power and performance.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b536cc5b-c88","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ottawa/analog-ic-design-engineer-14913/44408/91106519536","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","SERDES transceiver architectures","high-speed analog circuits"],"x-skills-preferred":["transistor-level CMOS design","SPICE simulators","scripting languages"],"datePosted":"2026-03-06T07:26:19.092Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ottawa"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, SERDES transceiver architectures, high-speed analog circuits, transistor-level CMOS design, SPICE simulators, scripting languages"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e4d218e4-3b5"},"title":"Power Integrity Staff Engineer","description":"<p>We are looking for a Power Integrity Staff Engineer to join our team. As a Power Integrity Staff Engineer, you will be responsible for modeling, simulating, analyzing signal and power integrity, troubleshooting, and reviewing interfaces interconnect. This encompasses all aspects of physical include interconnect and power network delivery in a system context, including silicon, package, pcb, connectors and components on multi-signal transmission line interfaces.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Responsible for modeling(IBIS, AMI,CMM, CPM, CTM), simulating, analyzing signal and power integrity (SIPI), troubleshooting, and reviewing interfaces interconnect.</li>\n<li>Performs, verifies, and documents interface SIPI analysis outcome as part of global chip design team.</li>\n<li>Carry out experiments to validate modeling and methodologies.</li>\n<li>Develop and document signal and power integrity requirements and flows for internal and external customer use.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Possesses excellent communication skills, both verbal and written.</li>\n<li>Familiarity with both Windows and Linux operating system is required.</li>\n<li>An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.</li>\n<li>Knowledge on interface such as UCIE is a plus, though DDR, HBM, PCIe (e.g. gen 6/5), Ethernet, SATA, for example, can be leveraged.</li>\n<li>Some experience in programming languages such as Python, TCL and Matlab is desired.</li>\n<li>A working knowledge of circuit simulation tools such as Synopsys HSPICE is required. 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Our team works closely with R&amp;D, product management, and global customers to deliver technical excellence, foster innovation, and drive the adoption of industry-leading library characterization solutions.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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