Tony's Chocolonely is committed to ending exploitation in cocoa. We are an impact company that makes chocolate, not a chocolate company that makes impact. With incredibly tasty chocolate, we lead by example, demonstrating that ethical practices and success can go hand in hand.

What you will do

As our Global Category Buyer, you'll own our global packaging categories, securing supply, supporting supplier partnerships, and driving both innovation and efficiency. This role mixes daily operational hustle with long-term category strategy, giving you huge influence on product quality, sustainability, and cost control. You'll bring structure where needed and move forward improvements in how we work. And above all, you'll help ensure our iconic packaging continues to tell our story - loudly, clearly, and responsibly.

All wrapped up -

• Develop and execute 3-year sourcing strategies for all key packaging categories, aligned with Tony’s sustainability commitments and commercial goals.
• Build, manage and develop a reliable global supplier base, fostering long-term partnerships, monitoring performance, and encouraging continuous improvement.
• Guide negotiations and secure rolling contracts with price discussions balancing cost, quality, and ethical standards.
• Run day-to-day operations while simultaneously progressing major improvement projects: dual supply, legal compliance updates, assortment suitability.
• Work collaboratively with Product, QA, Operations, Finance and Project Management to deliver NPD, manage risks, and keep big initiatives moving.
• Explore spend data, benchmark the market, and build savings pipelines that support both category strategy and yearly budget targets.
• Act as the internal go-to for all packaging-related topics - bringing visibility, clarity and a strong point of view to the table.
• Drive supply continuity and risk mitigation through BCP planning, dual sourcing and supplier diversification.

Requirements

Our new flavor:

• You bring relevant procurement experience in food or beverage industry – you understand materials, markets, and how FMCG speed feels.
• A proactive problem-solver who loves building structures.
• Strong in budgeting, cost reflection, PPV management and able to translate strategy into practical actions and timelines.
• Detail-oriented, thoughtful, and comfortable juggling tight deadlines.
• A self-assured, articulate negotiator - expressive when needed, and ready to make Tony’s more visible with suppliers and internally.
• Thrives in cross-functional environments and communicates well with stakeholders at all seniority levels.
• Hands-on, unafraid of ambiguity, and energized by a fast-paced environment where improvements never stop.
• Skilled in Excel, PowerPoint and basic project management tools.
• You raise the bar: challenge yourself and team Tony’s to increase our ambition and to accomplish our mission. Making mistakes along the way and learning from them.
• We are all about being more in person than apart; this means we offer flexibility but see each other in the office on average 3 days a week. More is fine too!
• Believe wholeheartedly in Tony’s purpose. You live our core values: outspoken, willful, entrepreneurial and makes you smile.

Our benefits (the icing on the cake)

At Tony's you will get the opportunity to be part of something extraordinary; first and foremost, by making real impact in the world but also enjoying the nice benefits we provide as you help us succeed. We’re dedicated to enabling all Tonys to grow and develop their careers and therefore we offer training programs, regular feedback cycles, coaching and a generous L&D budget. We also offer a wide range of additional benefits, including a luxurious vegetarian lunch, company bonus, minimum of 28 holidays, inspirational team updates, unforgettable events and unlimited chocolate. But we also know chocolate won’t cover the bills, so we’ve made sure your salary is just as rewarding, for this role that means a salary between EUR 56k-70k on a yearly basis, including holiday pay.

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You will lead the content and social strategy for Scale Labs' dedicated online presence, taking a research-native approach that earns attention and credibility from the AI community. You will build and maintain competitive intelligence and a sharp point of view on the data market, arming the team with differentiated positioning as the market evolves.

You will partner with Scale Labs researchers to amplify published work - leaderboards, benchmarks, and research papers - and translate it into pipeline and demand generation for the GenAI business. You will develop go-to-market strategies for new data offerings and modalities, working closely with product and sales to drive awareness and build market momentum.

You will collaborate cross-functionally with sales, engineering, and research to ensure consistent, compelling messaging across every customer touchpoint.

Ideally, you'd have 5+ years of experience in product marketing, with a track record of marketing technical products to developer or research audiences. You should have strong technical fluency and passion for AI, with the ability to hold a credible conversation about AI/ML fundamentals, training, and the role of data quality in model performance.

You should also have experience building social-native content and community strategies on platforms like X, with an instinct for what resonates with technical practitioners. You should have excellent written communication and storytelling skills, with the ability to make complex technical concepts compelling without oversimplifying them.

Nice to haves include familiarity with the AI training data market, or adjacent data and infrastructure spaces, as well as an existing network or relationships within the AI research community.

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Key responsibilities include:

• Working with a cross-functional team to design market-leading hardware products.
• Full cycle PCB design, including collecting requirements, schematic design, component selection, supervision or completion of layout, bring-up, test, debug, and integration with the system.
• Driving product maturity through rapid prototyping, design verification, and qualification activities.
• Applying modern design standards and guidelines to create high-reliability, highly manufacturable assemblies.
• Implementing combinations of high-speed digital, precision analog, RF, and high-power designs.
• Leading the team in establishing internal guidelines for design for manufacturing (DFM) and quality fabrication and assembly outputs.
• Conducting peer-level and cross-discipline design reviews.
• Low-level firmware development for bring-up and test.
• Root cause analysis in support of production operations.

Requirements include:

• 4+ years of professional experience in hardware product development.
• Full understanding of PCB Layout techniques to meet mechanical, electrical, and manufacturing requirements.
• Ability to read and interpret schematics and apply best practices appropriate for each design.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Knowledge of modern analog and digital electronics and electronic circuits.
• Ability to determine work priorities based on broad direction from management.
• Experience using Altium Designer or equivalent E-CAD tools.
• Excellent communication skills and ability to work effectively with others.
• Ability to work within our company and team culture.
• Must have an active U.S. Secret security clearance.

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At Cloudflare, we are on a mission to help build a better Internet. As a Customer Solutions Engineer (CSE), you will be the trusted technical advisor throughout a customer's lifecycle. You are a product expert and will leverage your knowledge to ensure our Enterprise customers understand and utilize the Cloudflare platform to its fullest extent.

Responsibilities:

As a critical member of the Account Team, you will serve as a trusted technical advisor, help expand existing business, and ensure the success of our customers. You will be part of a regional team and will work closely with Customer Success Managers (CSMs) working with the regional customers of Cloudflare.

From a technical perspective, as part of the account team, your primary responsibilities will be to deliver a timely and organized onboarding for customers, ensure customers see the full value in Cloudflare's products, and advise on technical best practices.

Ensure customer retention and expansion through relationship building and participation in periodic account reviews to contribute your expertise on technical topics.

Provide customers with clear proactive technical guidance and expertise across all our products.

Collaborate with Customer Support, Engineering, and other teams to assist with technical escalations.

Proactively identify opportunities for expansion for existing customers.

Promote retention by capturing and communicating gaps in product or features.

Contribute towards the success of the CSE role through knowledge-sharing activities such as contributing to internal and external documentation, answering technical Q&A, and helping iterate on best practices.

The role requires 15-30% travel to attend meetings with customers, attend conferences, and other industry events, and to collaborate with your Cloudflare teammates.

Experiences might include a combination of the skills below:

Deep understanding of how the internet works and the desire to expand that knowledge.

Layers and protocols of the OSI model, such as TCP/IP, TLS, DNS, HTTP.

Reverse and forward proxies and the applications of both.

Security aspects of an internet property, such as Firewalls, WAFs, Bot Management, Rate Limiting, (M)TLS, Zero Trust.

Performance aspects of an internet property, such as Speed, Latency, Caching, HTTP/2, TLSv1.3.

Enjoying the adventure of troubleshooting and solving technical problems.

Understanding why Cloudflare plays an increasingly important role on today's internet.

Demonstrated experience with a coding language (e.g. JavaScript, Python, etc) and a desire to expand those skills.

Technical curiosity and passion: Cloudflare is at the cutting edge of internet technology, and our CSEs are viewed as subject-matter experts.

It's incumbent on us to stay up to date not only with Cloudflare's specific products, but with industry trends.

Ability to proactively identify and solve problems then build sustainable solutions to prevent recurrence.

Ability to manage a project, work to deadlines, and prioritize between competing demands.

Great communication skills & stakeholder management skills.

Ability to read and write in an additional APAC language.

What Makes Cloudflare Special?

We're not just a highly ambitious, large-scale technology company. We're a highly ambitious, large-scale technology company with a soul.

Fundamental to our mission to help build a better Internet is protecting the free and open Internet.

Project Galileo: Since 2014, we've equipped more than 2,400 journalism and civil society organizations in 111 countries with powerful tools to defend themselves against attacks that would otherwise censor their work, technology already used by Cloudflare's enterprise customers--at no cost.

Athenian Project: In 2017, we created the Athenian Project to ensure that state and local governments have the highest level of protection and reliability for free, so that their constituents have access to election information and voter registration.

Since the project, we've provided services to more than 425 local government election websites in 33 states.

1.1.1.1: We released 1.1.1.1 to help fix the foundation of the Internet by building a faster, more secure and privacy-centric public DNS resolver.

This is available publicly for everyone to use - it is the first consumer-focused service Cloudflare has ever released.

Here's the deal - we don't store client IP addresses never, ever.

We will continue to abide by our privacy commitment and ensure that no user data is sold to advertisers or used to target consumers.

Sound like something you'd like to be a part of? We'd love to hear from you!

This position may require access to information protected under U.S. export control laws, including the U.S. Export Administration Regulations.

Please note that any offer of employment may be conditioned on your authorization to receive software or technology controlled under these U.S. export laws without sponsorship for an export license.

Cloudflare is proud to be an equal opportunity employer.

We are committed to providing equal employment opportunity for all people and place great value in both diversity and inclusiveness.

All qualified applicants will be considered for employment without regard to their, or any other person's, perceived or actual race, color, religion, sex, gender, gender identity, gender expression, sexual orientation, national origin, ancestry, citizenship, age, physical or mental disability, medical condition, family care status, or any other basis protected by law.

We are an AA/Veterans/Disabled Employer.

Cloudflare provides reasonable accommodations to qualified individuals with disabilities and encourages applicants with disabilities to apply.

If you need assistance or an accommodation due to a disability, please let us know.

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This role is ideal for someone who thrives at the intersection of research and systems engineering: a builder who understands both the math of optimization and the realities of distributed compute.

Responsibilities:

• Design and optimize distributed training infrastructure for large-scale LLMs, focusing on performance, stability, and reproducibility across multi-GPU and multi-node setups.
• Implement and evaluate low-precision numerics (for example, BF16, MXFP8, NVFP4) to improve efficiency without sacrificing model quality.
• Develop kernels and communication primitives that use hardware-level support for mixed and low-precision arithmetic.
• Collaborate with research teams to co-design model architectures and training recipes that align with emerging numeric formats and stability constraints.
• Prototype and benchmark scaling strategies such as data, tensor, and pipeline parallelism that integrate precision-adaptive computation and quantized communication.
• Contribute to the design of our internal orchestration and monitoring systems to ensure that thousands of distributed experiments can run efficiently and reproducibly.
• Publish and share learnings through internal documentation, open-source libraries, or technical reports that advance the field of scalable AI infrastructure.

Skills and Qualifications:

Minimum qualifications:

• Bachelor’s degree or equivalent experience in computer science, electrical engineering, statistics, machine learning, physics, robotics, or similar.
• Understanding of deep learning frameworks (e.g., PyTorch, JAX) and their underlying system architectures.
• Thrive in a highly collaborative environment involving many, different cross-functional partners and subject matter experts.
• A bias for action with a mindset to take initiative to work across different stacks and different teams where you spot the opportunity to make sure something ships.
• Strong engineering skills, ability to contribute performant, maintainable code and debug in complex codebases in areas such as floating-point numerics, low-precision arithmetic, and distributed systems.

Preferred qualifications , we encourage you to apply if you meet some but not all of these:

• Familiarity with distributed frameworks such as PyTorch/XLA, DeepSpeed, Megatron-LM.
• Experience implementing FP8, INT8, or block-floating point (MX) formats and understanding their numerical trade-offs.
• Prior contributions to open-source deep learning infrastructure such as PyTorch, DeepSpeed, or XLA.
• Publications, patents, or projects related to numerical optimization, communication-efficient training, or systems for large models.
• Experience training and supporting large-scale AI models.
• Track record of improving research productivity through infrastructure design or process improvements.

Logistics:

• Location: This role is based in San Francisco, California.
• Compensation: Depending on background, skills and experience, the expected annual salary range for this position is $350,000 - $475,000 USD.
• Visa sponsorship: We sponsor visas. While we can't guarantee success for every candidate or role, if you're the right fit, we're committed to working through the visa process together.
• Benefits: Thinking Machines offers generous health, dental, and vision benefits, unlimited PTO, paid parental leave, and relocation support as needed.

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At Cloudflare, we are on a mission to help build a better Internet. Today the company runs one of the world’s largest networks that powers millions of websites and other Internet properties for customers ranging from individual bloggers to SMBs to Fortune 500 companies.

As a Cloud Engineer for Developer Platform, you are an individual contributor working in the post-sales landscape, responsible for the technical execution of solutions and guidance to our customers, following a consultative approach, to get the most value possible from their Cloudflare investment.

Key Responsibilities:

• Plan and deliver timely and organized services for customers, ensure customers see the full value in Cloudflare’s products and advice on product best practices.

• Gather business and technical requirements, use cases and any other information required to build, migrate and deliver a solution on behalf of the customer and transition the Cloudflare working environment to the customer.

• Produce a Solution Design, HLD, LLD, databuilds, procedures, scripts, test plans, drawings, deployment plan, migration plan, as-builts, and any other artifacts necessary to deliver the solution and transition smoothly into the customer’s technical teams.

• Implement changes on behalf of the customer in the Cloudflare environment following the customer’s change management process.

• Troubleshoot implementation issues and collaborate with Customer Support, Engineering and other teams to assist technical escalations.

• Contribute towards the success of the organization through knowledge sharing activities such as contributing to internal and external documentation, answering technical Q&A, and helping to iterate on best practices.

Support building operational assets like templates, automation scripts, procedures, workflows, etc.

Requirements:

• 3+ years of experience in a customer facing position as a Consultant delivering services.

• Demonstrated experience with:

• Developing serverless code in a CI/CD pipeline using an Agile methodology.

• Layers and protocols of the OSI model, such as TCP/IP, TLS, DNS, HTTP.

• Scripting languages.

• A scripting language (e.g. Python, JavaScript, Bash) and a desire to expand those skills.

• Infrastructure as code tools like Terraform.

• Strong experience with APIs.

• CI/CD pipelines using Azure DevOps or Git.

• Implementation and troubleshooting experience, knowledge of tools to troubleshoot, observability, logs, etc.

• Good understanding and knowledge of:

• Internet and Security technologies such as DDoS, Web Application Firewall, Certificates, DNS, CDN, Analytics and Logs.

• Security aspects of an internet property, such as DNS, WAFs, Bot Management, Rate Limiting, (M)TLS, certificates, OWASP.

• Performance aspects of an internet property, such as Speed, Latency, Caching, HTTP/3, TLSv1.3.

Preferred Qualifications:

• You have worked with a Cybersecurity company or products and have performed migrations using migration tools.

• You have developed application security and performance capabilities.

• Ability to manage a project, work to deadlines, prioritize between competing demands and manage uncertainty.

• The work will be performed in English. Fluency in a second regional European language is a strong advantage.

What Makes Cloudflare Special?

We’re not just a highly ambitious, large-scale technology company. We’re a highly ambitious, large-scale technology company with a soul. Fundamental to our mission to help build a better Internet is protecting the free and open Internet.

Project Galileo: Since 2014, we've equipped more than 2,400 journalism and civil society organizations in 111 countries with powerful tools to defend themselves against attacks that would otherwise censor their work, technology already used by Cloudflare’s enterprise customers--at no cost.

Athenian Project: In 2017, we created the Athenian Project to ensure that state and local governments have the highest level of protection and reliability for free, so that their constituents have access to election information and voter registration. Since the project, we've provided services to more than 425 local government election websites in 33 states.

1.1.1.1: We released 1.1.1.1 to help fix the foundation of the Internet by building a faster, more secure and privacy-centric public DNS resolver. This is available publicly for everyone to use - it is the first consumer-focused service Cloudflare has ever released.

Here’s the deal - we don’t store client IP addresses never, ever. We will continue to abide by our privacy commitment and ensure that no user data is sold to advertisers or used to target consumers.

Sound like something you’d like to be a part of? We’d love to hear from you!

This position may require access to information protected under U.S. export control laws, including the U.S. Export Administration Regulations. Please note that any offer of employment may be conditioned on your authorization to receive software or technology controlled under these U.S. export laws without sponsorship for an export license.

Cloudflare is proud to be an equal opportunity employer. We are committed to providing equal employment opportunity for all people and place great value in both diversity and inclusiveness. All qualified applicants will be considered for employment without regard to their, or any other person's, perceived or actual race, color, religion, sex, gender, gender identity, gender expression, sexual orientation, national origin, ancestry, citizenship, age, physical or mental disability, medical condition, family care status, or any other basis protected by law. We are an AA/Veterans/Disabled Employer. Cloudflare provides reasonable accommodations to qualified individuals

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You are an expert in Developer Platform products or equivalent and will focus on building and deploying serverless applications with scale, performance, security and reliability leveraging: Workers, Workers KV, Workers AI, D1, R2, Images, and many other products.

This position has working hours Monday to Friday 09:00 a.m. to 06:00 p.m. Occasionally, we support our customers during the weekends for specific changes that need to be done outside of their business hours. Travel is expected to be around 40%.

Experience might include a combination of the skills below:

• Plan and deliver timely and organized services for customers, ensure customers see the full value in Cloudflare’s products and advice on product best practices.
• Gather business and technical requirements, use cases and any other information required to build, migrate and deliver a solution on behalf of the customer and transition the Cloudflare working environment to the customer.
• Produce a Solution Design, HLD, LLD, databuilds, procedures, scripts, test plans, drawings, deployment plan, migration plan, as-builts, and any other artifacts necessary to deliver the solution and transition smoothly into the customer’s technical teams.
• Implement changes on behalf of the customer in the Cloudflare environment following the customer’s change management process.
• Proven experience with Cloudflare or similar with Workers, Javascript/Typescript and Workers APIs.
• Troubleshoot implementation issues and collaborate with Customer Support, Engineering and other teams to assist technical escalations.
• Contribute towards the success of the organization through knowledge sharing activities such as contributing to internal and external documentation, answering technical Q&A, and helping to iterate on best practices.

Support building operational assets like templates, automation scripts, procedures, workflows, etc.

Experience might include a combination of the skills below:

• 3+ years of experience in a customer facing position as a Consultant delivering services.
• Demonstrated experience with:

Developing serverless code in a CI/CD pipeline using an Agile methodology. Layers and protocols of the OSI model, such as TCP/IP, TLS, DNS, HTTP Scripting languages A scripting language (e.g. Python, JavaScript, Bash) and a desire to expand those skills. Infrastructure as code tools like Terraform. Strong experience with APIs. CI/CD pipelines using Azure DevOps or Git. Implementation and troubleshooting experience, knowledge of tools to troubleshoot, observability, logs, etc. Good understanding and knowledge of:

Internet and Security technologies such as DDoS, Web Application Firewall, Certificates, DNS, CDN, Analytics and Logs. Security aspects of an internet property, such as DNS, WAFs, Bot Management, Rate Limiting, (M)TLS, certificates, OWASP. Performance aspects of an internet property, such as Speed, Latency, Caching, HTTP/3, TLSv1.3.

Strong advantage if:

You have worked with a Cybersecurity company or products and have performed migrations using migration tools. You have developed application security and performance capabilities. Ability to manage a project, work to deadlines, prioritize between competing demands and manage uncertainty.

The work will be performed in English. Fluency in a second regional European language is a strong advantage.

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At Cloudflare, we are on a mission to help build a better Internet. Today the company runs one of the world’s largest networks that powers millions of websites and other Internet properties for customers ranging from individual bloggers to SMBs to Fortune 500 companies.

We are looking for an Application Security and Performance Consultant to join our Professional Services team. As a Consultant, you will be responsible for the technical execution of solutions and guidance to our customers to get the most value possible from their Cloudflare investment.

Responsibilities

• Plan and deliver timely and organized services for customers, ensure customers see the full value in Cloudflare’s products and advice on product best practices
• Gather business and technical requirements, use cases and any other information required to build, migrate and deliver a solution on behalf of the customer and transition the Cloudflare working environment to the customer
• Produce a Solution Design, HLD, LLD, databuilds, procedures, scripts, test plans, drawings, deployment plan, migration plan, as-builts, and any other artifacts necessary to deliver the solution and transition smoothly into the customer’s technical teams
• Implement changes on behalf of the customer in the Cloudflare environment following the customer’s change management process
• Provide guidance to the customer to configure their CPEs and integration points
• Troubleshoot implementation issues and collaborate with Customer Support, Engineering and other teams to assist technical escalations

Requirements

• 5+ years of experience in a customer facing position as a Customer Engineer, Security Engineer, Implementation Engineer, Onboarding Engineer, Consultant, Technical Support Engineer, Solutions Architect, and/or Systems Engineer
• Layers and protocols of the OSI model, such as TCP/IP, TLS, DNS, HTTP
• Understanding of Internet and Security technologies such as DDoS, Web Application Firewall, Certificates, DNS, CDN, Analytics and Logs
• Demonstrated experience with a scripting language (e.g. Python, JavaScript, Bash) and a desire to expand those skills
• Demonstrated experience with security aspects of an internet property, such as DNS, WAFs, Bot Management, Rate Limiting, (M)TLS and certificates
• Performance aspects of an internet property, such as Speed, Latency, Caching, HTTP/3, TLSv1.3
• Working experience with infrastructure as code tools like Terraform
• Strong experience with APIs
• Ability to manage a project, work to deadlines, prioritize between competing demands and manage uncertainty

What Makes Cloudflare Special?

We are not just a highly ambitious, large-scale technology company. We are a highly ambitious, large-scale technology company with a soul. Fundamental to our mission to help build a better Internet is protecting the free and open Internet.

Project Galileo: Since 2014, we've equipped more than 2,400 journalism and civil society organizations in 111 countries with powerful tools to defend themselves against attacks that would otherwise censor their work, technology already used by Cloudflare’s enterprise customers--at no cost.

Athenian Project: In 2017, we created the Athenian Project to ensure that state and local governments have the highest level of protection and reliability for free, so that their constituents have access to election information and voter registration. Since the project, we've provided services to more than 425 local government election websites in 33 states.

1.1.1.1: We released 1.1.1.1 to help fix the foundation of the Internet by building a faster, more secure and privacy-centric public DNS resolver. This is available publicly for everyone to use - it is the first consumer-focused service Cloudflare has ever released.

Sound like something you’d like to be a part of? We’d love to hear from you!

This position may require access to information protected under U.S. export control laws, including the U.S. Export Administration Regulations. Please note that any offer of employment may be conditioned on your authorization to receive software or technology controlled under these U.S. export laws without sponsorship for an export license.

Cloudflare is proud to be an equal opportunity employer. We are committed to providing equal employment opportunity for all people and place great value in both diversity and inclusiveness. All qualified applicants will be considered for employment without regard to their, or any other person's, perceived or actual race, color, religion, sex, gender, gender identity, gender expression, sexual orientation, national origin, ancestry, citizenship, age, physical or mental disability, medical condition, family care status, or any other basis protected by law.

GetType

experienceLevel: senior employmentType: full-time workplaceType: hybrid category: Engineering industry: Technology salaryRange: requiredSkills: [TCP/IP, TLS, DNS, HTTP, DDoS, Web Application Firewall, Certificates, DNS, CDN, Analytics and Logs, Python, JavaScript, Bash, DNS, WAFs, Bot Management, Rate Limiting, (M)TLS and certificates, Speed, Latency, Caching, HTTP/3, TLSv1.3, Terraform, APIs] preferredSkills: []

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At Cloudflare, we are on a mission to help build a better Internet. Today the company runs one of the world’s largest networks that powers millions of websites and other Internet properties for customers ranging from individual bloggers to SMBs to Fortune 500 companies.

Cloudflare protects and accelerates any Internet application online without adding hardware, installing software, or changing a line of code. Internet properties powered by Cloudflare all have web traffic routed through its intelligent global network, which gets smarter with every request. As a result, they see significant improvement in performance and a decrease in spam and other attacks.

As a Customer Solutions Engineer (CSE), you will be the trusted technical advisor throughout a customer’s lifecycle. You are a product expert and will leverage your knowledge to ensure our Enterprise customers understand and utilize the Cloudflare platform to its fullest extent.

Responsibilities

As a critical member of the Account Team you will serve as a trusted technical advisor, help expand existing business, and ensure the success of our customers:

• You will be part of a regional team and will work closely with CSMs supporting the regional book of business

• From a technical perspective, as part of the account team, your primary responsibilities will be to deliver a timely and organized onboarding for customers, ensure customers see the full value in Cloudflare's products, and advise on technical best practices

• Ensure customer retention and expansion through relationship building and participation in periodic account reviews to contribute your expertise on technical topics

• Provide customers with clear proactive technical guidance and expertise across all our products

• Collaborate with Customer Support, Engineering, and other teams to assist with technical escalations

• Proactively identify opportunities for expansion for existing customers

• Promote retention by capturing and communicating gaps in product or features

• Contribute towards the success of the CSE organization through knowledge-sharing activities such as contributing to internal and external documentation, answering technical Q&A, and helping iterate on best practices

Experiences might include a combination of the skills below:

• 10 years of prior post-sales customer relationship management

• Deep understanding of how the internet works and the desire to expand that knowledge

• Layers and protocols of the OSI model, such as TCP/IP, TLS, DNS, HTTP

• Reverse and forward proxies and the applications of both

• Security aspects of an internet property, such as Firewalls, WAFs, Bot Management, Rate Limiting, (M)TLS, Zero Trust

• Performance aspects of an internet property, such as Speed, Latency, Caching, Video Streaming, HTTP/2, TLSv1.3

• Enjoying the adventure of troubleshooting and solving technical problems

• Understanding why Cloudflare plays an increasingly important role on today’s internet

• Ability to proactively identify and solve problems then build sustainable solutions to prevent recurrence

• Demonstrated experience with a scripting language (e.g. Python, JavaScript, Bash) and a desire to expand those skills

• Technical curiosity and passion: Cloudflare is at the cutting edge of internet technology, and our CSEs are viewed as subject-matter experts. It’s incumbent on us to stay up to date not only with Cloudflare’s specific products, but with industry trends.

• Ability to manage a project, work to deadlines, and prioritize between competing demands

• Fluent in English and Russian, Ukrainian, or Hebrew is a must.

What Makes Cloudflare Special?

We’re not just a highly ambitious, large-scale technology company. We’re a highly ambitious, large-scale technology company with a soul. Fundamental to our mission to help build a better Internet is protecting the free and open Internet.

Project Galileo: Since 2014, we've equipped more than 2,400 journalism and civil society organizations in 111 countries with powerful tools to defend themselves against attacks that would otherwise censor their work, technology already used by Cloudflare’s enterprise customers--at no cost.

Athenian Project: In 2017, we created the Athenian Project to ensure that state and local governments have the highest level of protection and reliability for free, so that their constituents have access to election information and voter registration. Since the project, we've provided services to more than 425 local government election websites in 33 states.

1.1.1.1: We released 1.1.1.1 to help fix the foundation of the Internet by building a faster, more secure and privacy-centric public DNS resolver. This is available publicly for everyone to use - it is the first consumer-focused service Cloudflare has ever released.

Here’s the deal - we don’t store client IP addresses never, ever. We will continue to abide by our privacy commitment and ensure that no user data is sold to advertisers or used to target consumers.

Sound like something you’d like to be a part of? We’d love to hear from you!

This position may require access to information protected under U.S. export control laws, including the U.S. Export Administration Regulations. Please note that any offer of employment may be conditioned on your authorization to receive software or technology controlled under these U.S. export laws without sponsorship for an export license.

Cloudflare is proud to be an equal opportunity employer. We are committed to providing equal employment opportunity for all people and place great value on diversity and inclusion.

XML job scraping automation by YubHub

Key responsibilities include:

• Supporting new products transitioning to and currently in production, ensuring smooth production onboarding or sustainment.
• Working with System Architect to map Vehicle level requirements to subsystem or component level.
• Procuring, building, testing and analysing new or sustaining hardware against requirements.
• Maintaining Design Verification and Validation plans.
• Working with the manufacturing and R&D engineering teams to implement incremental product improvements to increase reliability, performance and manufacturability.
• Creating and maintaining BOMs, Parts, Assemblies, drawings and technical procedures for existing engine configurations under development or sustaining status.
• Leading investigations into field failures or manufacturing/design issues and presenting proposed changes.
• Working with responsible engineers to propose permanent corrective actions.
• Working with responsible engineers to issue formal Change Requests, track and monitor them for timely implementation.
• Representing the design team in Change Control Board or Change Review Board.
• Being responsible for Value Engineering activities; collaborating with Supply Base and Responsible Engineers to implement cost reduction or supplier resiliency initiatives.
• Acting as a single point of contact for providing daily engineering support to engine production operations to resolve production obstacles.
• Facilitating supplier liaison on technical specifications and quality improvements.

The ideal candidate will have:

• 3+ years experience in Design Engineering, Sustaining or hands-on R&D role.
• BS or higher degree in Mechanical or Aerospace Engineering.
• Experience designing mechanical parts (CAD) in NX or Solidworks.
• Understanding of manufacturing methods (Castings, Machining, sheet metal, composites, 3D printing, injection moulding etc.).
• Proficient in mechanical drawings, ASME Y14.5 GD&T.
• Experience with release management in Teamcenter or equivalent PLM systems.
• Experience procuring parts and working in a machine shop.
• Working knowledge of machine safety and shop safety protocols.
• Excellent attention to detail, ability to manage product complexity and associated requirements.
• Excellent written and verbal communication skills.
• Demonstrated ability to work within a fast-paced and dynamic environment.
• Organised and detail-oriented.

Preferred qualifications include experience developing high-speed machines for aerospace or automotive applications, experience launching products in high-volume production, and proven track record of working in multidisciplinary teams.

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Key responsibilities include:

• Developing high-performance, high-efficiency, and highly robust avionics solutions for air vehicle platforms
• Developing reliable on-board communication systems to exchange high-bandwidth data across various air and ground assets
• Architecting, designing, and building high-speed digital PCBAs (schematic capture, simulation, board layout)
• Helping decide what to do in-house and what to outsource, communicating design requirements with external vendors and helping drive the progress
• Developing relationships with external vendors and communicating design requirements to external vendors and suppliers
• Working cross-functionally between software, firmware, and hardware teams
• Developing hardware validation test plans for sub-system and full system products

Requirements include:

• Bachelor's degree in Electrical Engineering, or a closely related field
• 8+ years relevant experience in electrical hardware design
• Experience designing high-density PCB layouts with an understanding of cutting-edge PCB manufacturing technology
• Deep understanding of thermal, mechanical, power, and performance tradeoffs
• Experience with creating test plans, benchmarking, and performing validation tests to determine performance of complex hardware systems
• Understanding of high-speed interfaces (PCIe, DDR, USB, MIPI, etc.), power integrity, and signal integrity
• Knowledgeable of EMI/EMC susceptibility and emissions along with mitigation experience
• Eligible to obtain and maintain an active U.S. Secret security clearance

Preferred qualifications include:

• Experience with high-performance SOMs (System On a Module)
• Experience in developing FPGA and ASIC architectures
• Experience with rapid, hands-on prototyping
• Skilled at soldering and reworking microelectronic components
• Knowledgeable in RF investigation and analysis with the use of specialized equipment (Spectrum analyzer, Network Analyzer, etc.) and RF simulation tool suites
• Knowledge of state-of-the-art hardware systems, software tools, and algorithms for interfaces required for sensors, actuators, firmware development, and inter-communication bus protocols (CAN-FD, Ethernet, SFP, 1553, etc.)
• Experience using Linux command line interface (CLI)

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Your goal is to help customers be successful and derive the most value possible from their Cloudflare investment. As a CSE, you strive to understand customer requirements and issues at the molecular level. No matter your background, you have natural curiosity and desire to identify root causes of unique problems and find the most elegant and efficient solutions.

Fundamentally, you are enamored with how the internet works. You will work closely with the Customer Success Manager (CSM) as well as every other team at Cloudflare, from Sales and Product to Engineering and Customer Support.

Responsibilities:

• Serve as a trusted technical advisor, help expand existing business, and ensure the success of our customers

• Be part of a regional team and work closely with CSMs supporting the regional book of business

• From a technical perspective, as part of the account team and your primary responsibilities, deliver a timely and organized onboarding for customers, ensure customers see the full value in Cloudflare's products, and advise on technical best practices

• Ensure customer retention and expansion through relationship building and participation in periodic account reviews to contribute your expertise on technical topics

• Provide customers with clear proactive technical guidance and expertise across all our products

• Collaborate with Customer Support, Engineering, and other teams to assist with technical escalations

• Proactively identify opportunities for expansion for existing customers

• Promote retention by capturing and communicating gaps in product or features

• Contribute towards the success of the CSE organization through knowledge-sharing activities such as contributing to internal and external documentation, answering technical Q&A, and helping iterate on best practices

• The role requires 20-50% travel to attend meetings with customers, attend conferences, and other industry events, and to collaborate with your Cloudflare teammates

Experiences might include a combination of the skills below:

• 5+ years of prior post-sales customer relationship management

• Deep understanding of how the internet works and the desire to expand that knowledge. For example:

• Layers and protocols of the OSI model, such as TCP/IP, TLS, DNS, HTTP

• Reverse and forward proxies and the applications of both

• Security aspects of an internet property, such as Firewalls, WAFs, Bot Management, Rate Limiting, (M)TLS, Zero Trust

• Performance aspects of an internet property, such as Speed, Latency, Caching, Video Streaming, HTTP/2, TLSv1.3

• Enjoying the adventure of troubleshooting and solving technical problems

• Understanding why Cloudflare plays an increasingly important role on today’s internet

• Ability to proactively identify and solve problems, then build sustainable solutions to prevent recurrence

• Demonstrated experience with a scripting language (e.g. Python, JavaScript, Bash) and a desire to expand those skills

• Technical curiosity and passion: Cloudflare is at the cutting edge of internet technology, and our CSEs are viewed as subject-matter experts. It’s incumbent on us to stay up to date not only with Cloudflare’s specific products, but with industry trends.

• Ability to manage a project, work to deadlines, and prioritize between competing demands

Bonus!

• Understanding of, or experience with, regulatory requirements such a PCI DSS, HIPAA, and SOC-2

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In addition to a competitive salary, we offer a variety of benefits to support your needs, including medical, dental, and vision insurance, company-paid life insurance, voluntary supplemental life insurance, short and long-term disability insurance, flexible spending account, health savings account, tuition reimbursement, ability to participate in employee stock purchase program (ESPP), mental wellness benefits through Spring Health, family-forming support provided by Carrot, paid parental leave, flexible, full-service childcare support with Kinside, 401(k) with a generous employer match, flexible PTO, catered lunch each day in our office and data center locations, and a casual work environment.

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This position requires a blend of systems engineering expertise, hands-on technical proficiency, and a deep understanding of complex test environments. You will be responsible for defining the architectural roadmap, integrating cutting-edge sensors, data acquisition systems, and telemetry solutions, and ensuring the robust operation of our mission-critical test assets.

Responsibilities

• Architectural Design & Development:
• Lead the architectural design, development, and evolution of comprehensive instrumentation systems and associated range infrastructure for complex test and evaluation systems.
• Define system requirements, specifications, and interface control documents (ICDs) for new and upgraded range capabilities.
• Develop long-term architectural roadmaps, technology insertion plans, and strategic upgrades to maintain state-of-the-art range capabilities.
• Instrumentation Systems Engineering:
• Select, integrate, and validate various instrumentation technologies including, but not limited to: telemetry (RF/Optical), radar, optics (high-speed cameras, IR, EO), GPS/PNT, environmental sensors, and acoustic arrays.
• Design and implement robust data acquisition (DAQ), processing, storage, and analysis pipelines to support real-time and post-test data needs.
• Develop and manage calibration procedures and ensure accuracy and traceability of all instrumentation.
• Range Infrastructure Development:
• Design and oversee the implementation of critical range infrastructure components, such as fiber optic networks, RF distribution systems, power distribution, communication systems, timing and synchronization, and environmental controls for instrumentation shelters.
• Perform RF Survey analysis to ensure noise floor is within desired tolerance ranges for various test sites and environments.
• Ensure network connectivity, cybersecurity, and data security for all instrumentation systems across the range.
• Coordinate with facility engineers and construction teams for physical infrastructure modifications and deployments.
• Test & Operations Support:
• Collaborate closely with test directors, mission planners, range operators, and data analysts to understand requirements and provide technical solutions.
• Provide expert support during testing, anomaly resolution, and post-test data analysis.
• Ensure compliance with all relevant range safety, security, environmental, and regulatory requirements.
• Technical Leadership & Mentorship:
• Provide technical leadership, guidance, and mentorship to junior engineers and cross-functional teams.
• Conduct trade studies, feasibility analyses, and risk assessments for proposed architectural changes and technology investments.
• Prepare detailed technical reports, presentations, and documentation for internal stakeholders and external customers.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Aerospace Engineering, Systems Engineering, Computer Science, or a related technical field.
• 15+ years of progressive experience in instrumentation systems architecture, leadership, or complex range infrastructure development, preferably within the defence or aerospace industry.
• Demonstrated experience in systems architecture development for complex real-time systems.
• Strong understanding of data acquisition (DAQ) principles, telemetry systems (e.g., IRIG 106), RF systems, and various sensor technologies.
• Proficiency with system modeling tools (e.g., SysML, MATLAB/Simulink), CAD software, and/or programming languages (e.g., Python, C++).
• Extensive experience in the design, development, integration, operation, and maintenance of test range infrastructure and instrumentation supporting high-speed weapons systems and Unmanned Aerial Vehicles (UAVs)/drones.
• Experience with network design, distributed systems, and real-time data processing.
• Excellent written and verbal communication skills, with the ability to articulate complex technical concepts to diverse audiences.
• Ability to work independently, manage multiple priorities, and lead technical efforts within a team environment.
• Ability to travel as required to multiple test locations CONUS and OCONUS.
• Must be able to obtain and maintain a U.S. Security Clearance (Secret or Top Secret preferred).

Preferred Qualifications

• Master's or Ph.D. in a relevant engineering discipline.
• Experience with specific missile test range instrumentation, such as high-speed video systems, precision timing systems, advanced radar tracking, or target scoring systems.
• Knowledge of cybersecurity best practices and implementation for critical infrastructure and classified systems.
• Familiarity with industry standards (e.g., IRIG, MIL-STD-1553, ARINC 429).
• Project management experience (PMP certification a plus).
• Hands-on experience with hardware design, prototyping, and testing.

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Our mission is to bring web3 to a billion people by providing builders with the tools they need to build exceptional onchain products.

About the Role

We’re seeking a Head of Go-To-Market to build and scale Alchemy’s global revenue engine. This role sits at the intersection of product, growth, and revenue, and will own how Alchemy brings products to market across developers, startups, enterprises, and emerging ecosystems.

Responsibilities

• Define and lead Alchemy’s global go-to-market strategy, determining how our platform reaches developers, startups, enterprises, and new onchain ecosystems worldwide.

• Build and scale a high-performing GTM organization across sales, marketing, partnerships, and revenue operations to drive durable, predictable growth.

• Turn product innovation into market adoption, partnering closely with Product and Engineering to launch category-defining infrastructure and developer tools.

• Create the operating system for revenue at Alchemy, establishing the frameworks for forecasting, pipeline generation, pricing, and performance management.

• Scale both developer-led growth and enterprise expansion, building repeatable motions that convert product usage into long-term revenue.

• Develop and lead exceptional GTM leaders, fostering a culture of ownership, speed, and deep customer understanding across the organization.

What We’re Looking For

• 10+ years experience leading go-to-market or revenue organizations at high-growth technology companies

• Proven experience scaling GTM functions from early stage to growth stage

• Experience leading multi-functional teams (sales, marketing, partnerships, revops)

• Strong experience selling or scaling technical products (developer platforms, infrastructure, or SaaS)

• Demonstrated success launching new products and building repeatable growth motions

• Strong analytical and operational mindset

• Ability to partner closely with product and engineering teams

• Comfort operating in fast-moving, ambiguous environments

Benefits and Perks

• Medical, Dental, & Vision

• Gym Reimbursement

• Home Office Build-out Budget

• In-Office Group Meals

• Commuter Benefits

• Flexible Time Off

• Wellbeing & Mental Health Perks

• Learning & Development Stipend

• Company Sponsored Conferences & Events

• HSA and FSA Plans

• Fertility Benefits

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Key responsibilities include:

• Aerodynamics design of unmanned air vehicles/missiles at conceptual, preliminary, and detailed design maturities
• Aerodynamics analysis of unmanned air vehicles, using both low and high order methods, including analysis tool development and improvement as needed
• Stability and control analysis
• Trajectory optimization for performance analysis, vehicle conceptual trades, and sensitivities
• Aerothermodynamic analysis of flight vehicles in high-speed environments
• Aircraft performance modeling and simulation
• Aerodynamic loads generation
• Wind tunnel test planning, execution, and analysis
• Flight test planning, execution, and analysis

Required qualifications include:

• BS or higher degree in Aerospace Engineering
• Experience with a variety of aerodynamic analysis techniques including hand calculations, lower-order codes, and computational fluid dynamics (CFD)
• Strong programming skills in higher-level languages (e.g., MATLAB, Python) for internal tool development in a version-controlled environment
• Experience preparing formal documentation (i.e., specifications, test procedures, technical reports, etc.)
• Passion for defending the United States and her allies
• Ability to obtain and hold a U.S. Top Secret security clearance

Preferred qualifications include:

• StarCCM+ experience
• Experience evaluating external aerodynamics characteristics of a vehicle in the supersonic or hypersonic flow regime
• Experience with aerothermal analysis
• Experience leveraging trajectory optimization software for performance analysis, vehicle conceptual trades, and/or sensitivities
• Knowledge of high-speed aerodynamic laminar, transitional, and turbulent simulation techniques
• Experience with chemical kinetics modeling and simulation
• Experience with combustion computational fluid dynamics and a foundational understanding of compressible flow
• Active U.S. Secret security clearance

US Salary Range: $146,000-$194,000 USD

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In this role, you will work closely with an interdisciplinary technical team to route high-speed mixed-signal designs, interact with fabricators and assemblers, and manage signal integrity in complex PCBs.

Key responsibilities include:

• Working directly with engineers to produce printed circuit board designs supporting Anduril's products.
• Applying modern design standards and guidelines to create high-reliability, highly manufacturable assemblies.
• Implementing combinations of high-speed digital, precision analog, RF, and high-power designs.
• Leading the team in establishing internal guidelines for design for manufacturing (DFM), design for assembly (DFA), and overall quality fabrication and assembly outputs.
• Developing and refining team processes for PCB design, part creation, and library/database standards.
• Coordinating external PCB design resources during design surges.

Required qualifications include:

• A bachelor's degree in electrical engineering or similar and 5+ years of professional experience in PCB design OR 10+ years of professional experience in PCB design.
• Ability to read and interpret schematics and apply best practices appropriate for each design.
• Expertise in applying relevant IPC standards, CID, CID+ certification.
• Expertise in PCB fabrication processes, limitations, design rules, and best practice.
• Experience using Altium Designer CAD tools (Allegro is a plus).
• Experience with developing component libraries and library management.
• Excellent communication skills with multiple fab houses (ensuring boards are built to print).
• Excellent communication skills with multiple assembly houses (ensuring boards are built to BOM).
• Experience with a variety of board types, including high density and high layer count (greater than 16) digital designs, power electronics, flex circuits, and RF circuits.
• Experience with HDI (high density interconnect) and thicker boards (greater than 1.6mm).
• Experience with high speed digital interfaces and controlled impedance routing requirements like USB, PCIe, Ethernet, SERDES, and DDR memory.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred qualifications include:

• Familiarity with RF board design.
• Experience with high-pin count packages (FPGA fanout).
• Familiarity with basic signal and power integrity rules (how they affect layout).

US Salary Range $111,000-$147,000 USD

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We are seeking exceptional GNC Engineers to shape the next generation of advanced tactical missile systems, strategic weapons, and hypersonic strike and defense systems. As a key contributor, you will develop, test, and integrate cutting-edge GNC architectures for subsonic, supersonic, and hypersonic autonomous systems, driving innovation in mission-critical capabilities.

Responsibilities:

• Develop, implement, and test algorithms for guidance, navigation, and control systems in line with project requirements.
• Design, implement, and assess the GNC architectures considering all elements, including sensors, actuators, and algorithms.
• Participate in all phases of system development, from concept to design, prototyping, testing, and operation.
• Collaborate closely with a multidisciplinary team including systems engineers, flight software engineers, and test engineers to ensure system-wide integration and performance.
• Contribute to design reviews, safety assessments, and system documentation.
• Use simulation and analysis tools to verify GNC models and system performance under different operating conditions.
• Provide system engineering expertise in the development of GNC systems, ensuring a cohesive and efficient approach to the design and implementation process.
• Troubleshoot and resolve issues related to GNC systems during design, testing, and operational phases.
• Keep updated with the latest technologies and trends in GNC engineering and system architecture design.

Required Qualifications:

• BS in Robotics, Computer Science, Electrical, Mechanical, Mechatronics, Aerospace Engineering or related field with focus on dynamics and control
• A strong theoretical knowledge of flight mechanics, classical and modern control theory, estimation, and filtering techniques.
• Experience with developing GNC solutions for flight systems
• Proficiency with GNC simulation tools like MATLAB, Simulink and related toolboxes
• Familiarization with 6-DOF simulations
• Must be eligible to obtain and maintain a U.S. Top Secret clearance

Preferred Qualifications:

• A MS or Ph.D. in Aerospace Engineering, Mechanical Engineering, Electrical Engineering, or a related field is a plus
• Strong understanding of flight mechanics and related physics.
• Practical experience developing GNC designs for high speed flight systems and re-entry vehicles.
• Practical experience with Explicit Model Following, Dynamic Inversion, and Adaptive Control techniques.
• Extensive experience in GNC system and architecture development and testing, preferably in the aerospace industry.
• Experience generating C or C++ code from Simulink models.
• Experience writing code in C/C++
• Strong analytical, problem-solving, and decision-making skills.
• Excellent verbal and written communication skills.
• Ability to work independently and in a team-oriented, collaborative environment.
• Familiarity with agile and Lean product development methodologies such as Scrum.
• Experience using Jira, Git, GitHub, or GitLab
• Understanding of and compliance with industry, safety, and quality standards appropriate for the application
• Passion for defending the United States and its allies
• Current Active U.S. Top Secret clearance preferred

Salary Range:

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package.

Benefits:

Anduril offers top-tier benefits for full-time employees, including:

• Healthcare Benefits - US Roles: Comprehensive medical, dental, and vision plans at little to no cost to you.
• UK & AUS Roles: We cover full cost of medical insurance premiums for you and your dependents.
• IE Roles: We offer an annual contribution toward your private health insurance for you and your dependents.
• Income Protection: Anduril covers life and disability insurance for all employees.
• Generous time off: Highly competitive PTO plans with a holiday hiatus in December.
• Caregiver & Wellness Leave is available to care for family members, bond with a new baby, or address your own medical needs.
• Family Planning & Parenting Support: Coverage for fertility treatments (e.g., IVF, preservation), adoption, and gestational carriers, along with resources to support you and your partner from planning to parenting.
• Mental Health Resources: Access free mental health resources 24/7, including therapy and life coaching.
• Additional work-life services, such as legal and financial support, are also available.
• Professional Development: Annual reimbursement for professional development.
• Commuter Benefits: Company-funded commuter benefits based on your region.
• Relocation Assistance: Available depending on role eligibility.
• Retirement Savings Plan - US Roles: Traditional 401(k), Roth, and after-tax (mega backdoor Roth) options.
• UK & IE Roles: Pension plan with employer match.
• AUS Roles: Superannuation plan.

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This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms. You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centres, including our primary front and backend networks that train Grok and that customers use for inference.

Responsibilities:

• Design, validate, and productise high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).
• Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterisation.
• Investigate the opportunity for LPO and LRO in our network.
• Evaluate early co-packaged and near-packaged engines for switches and GPUs.
• Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.
• Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.
• Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.
• Perform system-level simulation of end-to-end fabric performance.
• Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
• Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.

Basic Qualifications:

• At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacentre environment.
• Master's or PhD degree in Electrical Engineering, Photonics or Physics.
• Deep knowledge of PAM4 SerDes performance, equalisation, jitter, crosstalk.
• Solid operational understanding of FEC, Retimers, TIAs and Drivers.
• Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.
• Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterisation.
• Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.
• Knowledge of SiPh design process, yield improvement and reliability testing.
• Familiarity with CPO technologies and challenges/risk areas.
• Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.
• Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.

Compensation and Benefits:

$180,000 - $440,000 USD

Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.

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Your responsibilities will include shaping hardware product roadmaps and leading capture campaigns to secure contracts and deliver capability. This role requires a deep understanding of undersea commercial operations, undersea kill chains, and the challenges of subsea operations. You must have a proven track record in influencing product roadmaps and collaborating with multiple program offices, services, and international partners to deliver capabilities.

Key Responsibilities:

• Generate and capture business opportunities
• Grow existing business
• Communicate our value to clients
• Inform product development

Required Qualifications:

• Proven development and growth leader with prior experience in commercial or DoD Capture and Sales
• Demonstrated knowledge in defense acquisitions, with a history of zero-to-one defense program growth a plus
• Experience in the technical, programmatic, and operational challenges of developing and deploying underwater vehicles, torpedoes, and high-speed systems
• Demonstrated high-energy, high-ownership leader who will drive performance and exhibit strong management skills with a high level of emotional intelligence
• Excellent writing, communication skills with experience briefing senior executives and customers
• Demonstrated knowledge of relevant DoD / IC / Commercial programs, platforms, and payloads, to include enabling technologies, systems integration, and software development

Preferred Qualifications:

• Expertise in Undersea Warfare, Distributed Maritime Operations, or complex engineering systems
• Experience with government business development, government contract structures, and government proposal processes
• Prior military or contracting experience, or experience in DoD or Government
• Ability to travel 20-50%, including International
• Masters or PhD in electrical engineering, physics, or computer science
• Eligible to obtain and maintain an active U.S. Top Secret security clearance

US Salary Range: $166,000-$220,000 USD

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About the Job: The Maritime Division builds integrated autonomous maritime systems, including surface and undersea vehicles, subsea sensing, and kinetic payloads, all powered by our Lattice platform. We are seeking an Associate Director, Business Development, Copperhead, to join our rapidly growing Business Development team in Washington, DC.

Responsibilities:

• Generate and capture business opportunities. The BD team is ultimately responsible for growing revenue. You will support the growth team in identifying, pursuing, and shaping future opportunities for our Undersea Reconnaissance and Strike portfolio.
• Grow existing business. You will partner with adjacent business lines and product engineers to identify opportunities for business growth with current clients.
• Communicate our value to clients. BD team members represent Anduril to a broad audience: clients, partners, competitors, and the interested public.
• Inform product development. You will be a liaison between a current or prospective client and the engineering organization, and as such must be able to translate their problem set into an actionable internal plan and product roadmap.

Requirements:

• The ideal candidate will be a proven development and growth leader with prior experience in commercial or DoD Capture and Sales, demonstrating a track record of building, executing, and winning business capture strategies, particularly with an emphasis on the US Navy as a customer.
• Demonstrated knowledge in defense acquisitions, with a history of zero-to-one defense program growth a plus.
• Experience in the technical, programmatic, and operational challenges of developing and deploying underwater vehicles, torpedoes and high speed systems.
• Demonstrated high-energy, high-ownership leader who will drive performance and exhibit strong management skills with a high level of emotional intelligence.
• Excellent writing, communication skills with experience briefing senior executives and customers.
• Demonstrated knowledge of relevant DoD / IC / Commercial programs, platforms and payloads, to include enabling technologies, systems integration and software development.

Preferred Qualifications:

• Expertise in Undersea Warfare, Distributed Maritime Operations or complex engineering systems.
• Experience with government business development, government contract structures, and government proposal processes.
• Prior military or contracting experience, or experience in DoD or Government.
• Ability to travel 20-50%, including International.
• Masters or PhD in electrical engineering, physics or computer science.
• Eligible to obtain and maintain an active U.S. Top Secret security clearance.

Salary: $166,000-$220,000 USD

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Our team looks for engineers that value first principles engineering and extreme ownership.

Responsibilities:

• Own a design that directly impacts the X-BAT system and major flight test milestones. A senior engineer is assigned as a direct mentor to provide technical review and professional feedback.
• Full lifecycle ownership: concept, design, verification, integration, flight test, and manufacturing
• Design efforts include:
• Circuit design for our embedded system. You will design with analog, digital, power conversion, high-speed, FPGA, MCU, EMI/EMC, etc.
• System integration and verification
• Environmental test, qualification, and automation
• Debug, root cause, and drive resolution
• Systems must be designed for high-reliability, radiation, aggressive temperature changes, and high-magnitude vibration

Qualifications:

• Have a degree in Electrical Engineering or equivalent
• Strong technical fundamentals
• Have been part of an engineering team/club
• Experience with electrical design software, Altium, KiCAD, etc.

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Your responsibilities will include:

• Designing circuitry for our embedded system, incorporating analog, digital, power conversion, high-speed, FPGA, MCU, EMI/EMC, and other components
• System integration and verification
• Environmental testing, qualification, and automation
• Debugging, root cause analysis, and driving resolution

You will be expected to design systems for high-reliability, radiation resistance, aggressive temperature changes, and high-magnitude vibration.

As a member of our team, you will receive direct mentorship and technical review from Senior Electrical Engineers, and have the opportunity to contribute to the development of our X-BAT system.

We are looking for engineers who value first principles engineering and extreme ownership, and are eager to take on new challenges and learn from experienced professionals.

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You will collaborate cross-functionally with other electrical, firmware/software, mechanical, and manufacturing/quality teams to design, validate, and deliver robust electronic solutions.

Key Responsibilities:

• Primarily digital and power-based designs, but analog design is a possibility.
• Own the entire PCB design lifecycle, including requirements, major component selection, block diagrams, schematic, circuit analysis, placement, routing, DFA/DFM review, prototype testing, and documentation.
• Create and maintain BOMs, design files, netlists, and manufacturing documentation.
• Work closely with mechanical engineers to integrate PCBs into enclosures and assemblies.
• Lead or support prototype bring-up, debugging, and testing with support from the firmware/software teams (Capability to write firmware/software for bring-up is a plus).
• Perform signal integrity, power budgeting, and thermal analysis as needed.
• Review and optimize designs for EMC/EMI compliance and environmental robustness.
• Interface with fabrication and assembly vendors, addressing build issues and driving quality improvements.
• Participate and cross-collaborate in design reviews and peer reviews to ensure high standards.
• Contribute to and improve engineering processes, libraries, and design guidelines.
• Support ITAR/export compliance and follow relevant standards such as MIL-STD’s, IPC-610/6012, etc.

Required Qualifications:

• Bachelor’s degree in Electrical Engineering or related field.
• 3+ years of professional experience in PCB schematic and layout design.
• Proficiency with Altium Designer (or other equivalent EDA tools).
• Experience with multi-layer board design and high-speed or mixed-signal circuitry.
• Strong understanding of electronic components, circuit theory, and board-level design principles.
• Ability to interpret datasheets, standards, and mechanical constraints.
• Proven experience with design for manufacturing (DFM) and design for test (DFT).

Preferred Qualifications:

• Experience in defense, aerospace, or other safety/mission-critical industries.
• Familiarity with ruggedized systems, high-temperature settings, water-intrusion protection, and other environmental requirements.
• Knowledge of MIL-STD, IPC standards, or similar frameworks.
• Experience with SPICE simulations, Signal Integrity Analysis, or reliability engineering.
• Ability to work with firmware, FPGA, or embedded teams.
• Active or previous security clearance (or ability to obtain one).
• Ownership mentality and attention to detail.
• Ability to work both independently and in multidisciplinary teams.
• Strong organizational and time management skills.
• Comfortable working in a fast-paced, product-focused environment.

Benefits:

• Medical Insurance: Comprehensive health insurance plans covering a range of services
• Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care
• Saronic pays 100% of the premium for employees and 80% for dependents
• Time Off: Generous PTO and Holidays
• Parental Leave: Paid maternity and paternity leave to support new parents
• Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses
• Retirement Plan: 401(k) plan
• Stock Options: Equity options to give employees a stake in the company’s success
• Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage
• Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

Physical Demands:

• Prolonged periods of sitting at a desk and working on a computer.
• Occasional standing and walking within the office.
• Manual dexterity to operate a computer keyboard, mouse, and other office equipment.
• Visual acuity to read screens, documents, and reports.
• Occasional reaching, bending, or stooping to access file drawers, cabinets, or office supplies.
• Lifting and carrying items up to 20 pounds occasionally (e.g., office supplies, packages).

Additional Information:

This role requires access to export-controlled information or items that require “U.S. Person” status. As defined by U.S. law, individuals who are any one of the following are considered to be a “U.S. Person”: (1) U.S. citizens, (2) legal permanent residents (a.k.a. green card holders), and (3) certain protected classes of asylees and refugees, as defined in 8 U.S.C. 1324b(a)(3).

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Responsibilities: Conduct one or more of the following tasks with a high level of proficiency: Hull form development and optimization. Resistance, power and speed predictions. Functional design and general arrangement development. Stability analysis and loading manuals (IMO and USCG requirements). Hydrodynamic analysis (hydrodynamic properties, seakeeping, motions and accelerations). Propulsion and powerplant (conventional and non-conventional). Ship systems design (specifications, arrangement, P&ID’s). Global ship structural design (hull girder strength and global loads, fatigue and service life assessment). Local ship structural design (cargo holds, hatch covers, top-side structures, general outfitting). Prepare regulatory submissions according to USA-flag and international maritime regulations (USCG, IMO conventions, ABS, LR, DNV…etc.). Collaborate with other engineers to support CAD modeling, weight management, and the integration of autonomous navigation and control systems into vessel designs. Participate in design reviews and brainstorming sessions for new and existing vessel concepts. Support documentation, technical writing, and preparation of reports for internal use and client presentations. Research and stay updated on new developments in naval architecture, autonomous technology, and commercial shipping trends and innovation.

Qualifications: Must be a “U.S. Person”: U.S. citizens, legal permanent residents, and certain protected classes of asylees and refugees, as defined in 8 U.S.C. 1324b(a)(3). Bachelor’s degree or higher in Naval Architecture, Marine Engineering, Ocean Engineering, or a related field. Ability to work at speed and support quick turnaround trade studies, highly attentive to schedule-driven design freezes. Clear communicator with both engineering and non-engineering stakeholders. Strong fundamentals in core naval architecture principles and proficiency with industry-standard tools, including one or more of the following: Hull form and hydrostatics (e.g., Rhino3D, Orca3D) Hydrodynamics and seakeeping (e.g., Proteus DS / ShipMo3D, StarCCM+, Simerics) Stability and load case analysis tools (e.g. GHS) Structural analysis FEA and FEM interfaces (e.g. FEMAP) Systems and structures drawing tools (e.g. AutoCAD, Siemens NX) Working knowledge with energy efficiency measures (EEDI/EEXI, CII, hull optimization, hybrid power, alternative fuels, wind-assist) Senior Naval Architect: 5+ years of experience. Staff Naval Architect: 15+ years of experience.

Benefits: Medical Insurance: Comprehensive health insurance plans covering a range of services Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care Saronic pays 100% of the premium for employees and 80% for dependents Time Off: Generous PTO and Holidays Parental Leave: Paid maternity and paternity leave to support new parents Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses Retirement Plan: 401(k) plan Stock Options: Equity options to give employees a stake in the company’s success Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

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In this role, you will define FPGA architectures, implement high-performance digital logic, and collaborate closely with hardware, firmware, and quantum engineering teams to build scalable, low-latency control systems.

Key responsibilities include: Developing and improving a custom microprocessor responsible for waveform generation and critical logic to operate a quantum computer Working closely with hardware, firmware, and software teams to define architecture, data flow, and interfaces Implementing, simulating, and verifying designs including DSP pipelines, control logic, and high-speed I/O Optimizing designs for latency, resource utilization, and robustness in production environments Developing and maintaining testbenches, verification flows, and CI Supporting bring-up, lab validation, and debugging in collaboration with Quantum Engineering on actual quantum computers Contributing to the long-term roadmap for the architecture of Rigetti’s control systems.

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You'll work hands-on across compute, storage, interconnect and cooling to keep one of France's largest GPU/CPU clusters healthy and scalable.

Location: Bruyères-le-Châtel , on-site, field role (multi-site mobility: Paris area and nearby)

Reporting line: Hardware Ops

Impact:

• Compute is a key lever for Mistral's success and our largest spend item.

• Direct impact on scale: you'll restore service on complex incidents and raise the bar on reliability as we grow.

• Enable breakthrough AI: your work unlocks science & engineering teams to deliver state-of-the-art AI.

What you will do:

• Lead complex interventions: plan and execute vendor-level or multi-node operations (e.g., full rack work, intricate recabling, post-restart diagnosis), own risk assessment/rollback, and coordinate with vendors (RMA/escalations).

• Advanced diagnostics: correlate symptoms across compute, storage, interconnect, cooling; read system indicators (LED/POST/beep), BMC/IPMI consoles, and logs to identify root causes.

• Guide and uplift L1s: coach on safe practices (ESD/LOTO), first-line triage, rack craftsmanship, documentation quality; pair on tricky procedures.

• Process & automation: improve SOPs/checklists; propose/build small automation (Python/Bash) for photo/serial capture, inventory sync, dashboards/alerts; shorten MTTR.

• Safety & compliance: enforce lockout/tagout, ESD, PPE; ensure audit-ready tickets, evidence and change traces.

• Parts & logistics (advanced): plan spares strategy, track failure trends, and drive proactive vendor actions.

About you:

• 5+ years in data center/server hardware or L2/L3 hardware support, with proven complex hands-on work in production (HPC/AI/Cloud at scale).

• End-to-end hardware expertise: comfortable across CPU/memory/PCIe cards (incl. accelerators), NICs, PSUs, drives, network, power and cooling (including DLC); strong judgment on when/how to escalate.

• Diagnostics depth: confident in analyzing BMC/IPMI logs, linux software logs and crashes simple CLI checks; methodical root cause analysis.

• Safety & discipline: impeccable ESD/LOTO/PPE habits; zero rough handling; clean, labeled, auditable work.

• Communication & mentoring: crisp status/handovers; able to coach L1s during live operations.

Provide technical documentations to L1s or other team

Mobility: willing to travel between sites (Paris area or nearby regions, occasionally in Europe or US))

Nice to have:

• Vendor tools (iDRAC/iLO/IPMI), RAID/storage basics (NVMe/SAS/SATA), high-speed interconnect (Ethernet/InfiniBand).

• Coding/automation (Python/Bash) for small ops tools and reporting.

• Experience with ticketing (Jira/ServiceNow), inventory/RMA flows, vendor coordination.

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We are seeking a Research Engineer to join our Machine Learning team. As a Research Engineer, you will work on building and optimizing large-scale learning systems that power our open-weight models.

Responsibilities

• Accelerate researchers by taking on the heavy parts of large-scale ML pipelines and building robust tools.
• Interface cutting-edge research with production: integrate checkpoints, streamline evaluation, and expose APIs.
• Conduct experiments on the latest deep-learning techniques.
• Design, implement and benchmark ML algorithms; write clear, efficient code in Python.
• Deliver prototypes that become production-grade components for Le Chat and our enterprise API.

Requirements

• Master's or PhD in Computer Science (or equivalent proven track record).
• 4 + years working on large-scale ML codebases.
• Hands-on with PyTorch, JAX or TensorFlow; comfortable with distributed training (DeepSpeed / FSDP / SLURM / K8s).
• Experience in deep learning, NLP or LLMs; bonus for CUDA or data-pipeline chops.
• Strong software-design instincts: testing, code review, CI/CD.
• Self-starter, low-ego, collaborative.

Benefits

• Competitive cash salary and equity.
• Food: Daily lunch vouchers.
• Sport: Monthly contribution to a Gympass subscription.
• Transportation: Monthly contribution to a mobility pass.
• Health: Full health insurance for you and your family.
• Parental: Generous parental leave policy.

Note: Benefits may vary depending on location.

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The MLS team at Freenome develops DL models using massive-scale genomic data that presents significant challenges for current training paradigms. The Senior Machine Learning Research Engineer will primarily be responsible for developing and deploying the infrastructure needed to support development of such DL models: enabling distributed DL pipelines, optimising hardware utilisation for efficient training, and performing model optimisations.

As part of an interdisciplinary R&D team, they will work in close collaboration with machine learning scientists, computational biologists and software engineers to accelerate the development of state-of-the-art ML/AI models and help Freenome achieve its mission.

Key responsibilities include:

• Implementing and refining DL pipelines on distributed computing platforms to enhance the speed and efficiency of DL operations, including model training, data handling, model management, and inference.
• Collaborating closely with ML scientists and software engineers to understand current challenges and requirements and ensure that the DL model development pipelines created are perfectly aligned with scientific goals and operational needs.
• Continuously monitoring, evaluating, and optimising DL model training pipelines for performance and scalability.
• Staying up to date with the latest advancements in AI, ML, and related technologies, and quickly learning and adapting new tools and frameworks, if necessary.
• Developing and maintaining robust and reproducible DL pipelines that guarantee that DL pipelines can be reliably executed, maintaining consistency and accuracy of results.
• Driving performance improvements across our stack through profiling, optimisation, and benchmarking. Implementing efficient caching solutions and debugging distributed systems to accelerate both training and evaluation pipelines.
• Acting as a bridge facilitating communication between the engineering and scientific teams, documenting and sharing best practices to foster a culture of learning and continuous improvement.

Must-haves include:

• MS or equivalent experience in a relevant, quantitative field such as Computer Science, Statistics, Mathematics, Software Engineering, with an emphasis on AI/ML theory and/or practical development.
• 5+ years of post-MS industry experience working on developing AI/ML software engineering pipelines.
• Proficiency in a general-purpose programming language: Python (preferred), Java, Julia, C, C++, etc.
• Strong knowledge of ML and DL fundamentals and hands-on experience with machine learning frameworks such as PyTorch, TensorFlow, Jax or Scikit-learn.
• In-depth knowledge of scalable and distributed computing platforms that support complex model training (such as Ray or DeepSpeed) and their integration with ML developer tools like TensorBoard, Wandb, or MLflow.
• Experience with cloud platforms (e.g., AWS, Google Cloud, Azure) and how to deploy and manage AI/ML models and pipelines in a cloud environment.
• Understanding of containerisation technologies (e.g., Docker) and computing resource orchestration tools (e.g., Kubernetes) for deploying scalable ML/AI solutions.
• Proven track record of developing and optimising workflows for training DL models, large language models (LLMs), or similar for problems with high data complexity and volume.
• Experience managing large datasets, including data storage (such as HDFS or Parquet on S3), retrieval, and efficient data processing techniques (via libraries and executors such as PyArrow and Spark).
• Proficiency in version control systems (e.g., Git) and continuous integration/continuous deployment (CI/CD) practices to maintain code quality and automate development workflows.
• Expertise in building and launching large-scale ML frameworks in a scientific environment that supports the needs of a research team.
• Excellent ability to work effectively with cross-functional teams and communicate across disciplines.

Nice-to-haves include:

• Experience working with large-scale genomics or biological datasets.
• Experience managing multimodal datasets, such as combinations of sequence, text, image, and other data.
• Experience GPU/Accelerator programming and kernel development (such as CUDA, Triton or XLA).
• Experience with infrastructure-as-code and configuration management.
• Experience cultivating MLOps and ML infrastructure best practices, especially around reliability, provisioning and monitoring.
• Strong track record of contributions to relevant DL projects, e.g. on github.

The US target range of our base salary for new hires is $161,925 - $227,325. You will also be eligible to receive equity, cash bonuses, and a full range of medical, financial, and other benefits depending on the position offered.

Freenome is proud to be an equal-opportunity employer, and we value diversity. Freenome does not discriminate on the basis of race, colour, religion, marital status, age, national origin, ancestry, physical or mental disability, medical condition, pregnancy, genetic information, gender, sexual orientation, gender identity or expression, veteran status, or any other status protected under federal, state, or local law.

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Key responsibilities include:

• Developing core software features that make up Eve's product
• Driving product direction by collaborating with the team to understand user needs, define new features, and decide on implementation strategies
• Full-stack development, owning and scaling the user-facing experience of Eve products
• AI integration, designing and building AI-native solutions that power and streamline every aspect of law firm operations
• Rapid deployment, embracing a fast shipping cadence and continuously iterating based on user feedback

You will work closely with our customers to solve their problems, innovate, and iterate.

To be successful in this role, you should have a proven track record of building incredible products, be comfortable working across the entire stack, and have experience or strong interest in building with AI.

In addition to a competitive salary and equity, we offer a range of benefits, including a 401(k) program with employer matching, health, dental, vision, and life insurance, short-term and long-term disability, commuter benefits, an autonomous work environment, office setup reimbursement, flexible time off, and quarterly team gatherings.

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Key Responsibilities

• Design, develop, and optimize FPGA-based digital systems for real-time defense applications
• Implement RTL designs (VHDL, Verilog, SystemVerilog) for high-speed data processing
• Perform simulation, synthesis, timing analysis, and timing closure
• Develop and integrate DSP algorithms in hardware (e.g., FFTs, filters, modulation)
• Interface with high-speed ADCs/DACs, RF front ends, and embedded processors
• Support hardware bring-up, debugging, and validation in lab environments
• Collaborate with RF, systems, and software engineers to ensure system performance
• Document designs, requirements, and verification results

Required Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (or related field)
• Minimum of 2 years' professional experience within the aerospace & defense industry
• Minimum 2 years' experience using FPGA toolchains (Xilinx Vivado, Intel Quartus)
• Proficiency in HDLs (VHDL, Verilog, or SystemVerilog)
• Strong understanding of digital design fundamentals (timing, clock domains, pipelining)
• Experience with simulation/verification tools (ModelSim, Questa, etc.)
• Ability to obtain and maintain a U.S. security clearance

ITAR Regulations

• To conform to U.S. Government technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicant must be a US Citizen, Green Card holder, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

Bonus Points

• Experience with defense systems (radar, EW, communications)
• Knowledge of digital signal processing (DSP) implementation and fixed-point math
• Proficient in scripting languages (Tcl, bash, Python)
• Familiarity with embedded software integration on SoCs
• Experience with high-speed interfaces (JESD204, PCIe, Ethernet, DDR)
• Familiarity with SoC platforms (e.g., Xilinx Zynq, RFSoC)
• Understanding of RF signal chains and systems

Additional Information

CX2 is a next-generation defense technology company securing spectrum dominance for the United States and its allies. We build AI-enabled hardware and software platforms to detect, disrupt, and defend the electromagnetic spectrum across land, air, sea, and space. Our systems are deployed in the most contested operational environments in the world. We’re backed by leading venture investors in the defense ecosystem and led by founders with track records at Meta, SpaceX, Epirus, and the U.S. Department of Defense.

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We are seeking an accomplished architect with expertise in high-speed analog and mixed-signal IC design. You will thrive on solving complex challenges and leading teams to deliver innovative transceiver solutions for silicon photonics.

Key responsibilities include:

Architecting 224G & 448G analog transceiver solutions for silicon photonics. Collaborating across engineering teams to drive integration and innovation. Mentoring engineers and supporting technical growth. Representing Synopsys in industry forums. Shaping technical roadmaps for emerging markets. Ensuring designs meet stringent performance and reliability standards.

As an Analog Design Architect, you will advance Synopsys' leadership in silicon photonics and high-speed analog design. You will enable next-generation data center and cloud connectivity, drive technical excellence and innovation, promote collaboration and knowledge sharing, influence industry standards, and open new business opportunities.

Requirements include:

Deep experience in high-speed analog/mixed-signal IC and transceiver design. Expertise in 224G & 448G architectures and silicon photonics integration. Proficiency with EDA tools and IC layout. Strong grasp of signal integrity and power management. Ability to translate technical needs into scalable solutions.

Ideal candidates are innovative and collaborative leaders with a clear communication style, detail-oriented and adaptable, and passionate about advancing technology.

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This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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Job Description

As an experienced Analog Layout Senior Engineer, you will work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield. You will build and enhance layout flow for faster, higher quality design processes.

Responsibilities

• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.
• Floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
• Apply Analog Layout techniques to ensure design meets performance with minimum area and good yield.
• Build and enhance layout flow for faster, higher quality design processes.
• Perform layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
• Conduct PERC verification for ESD/LUP checks.
• Complete all design quality checks and data quality checks.
• Collaborate with Place and Route engineers to integrate analog layouts into the top level.
• Work with the Package team to ensure the integration of top die and package.
• Participate in design reviews across the global team.
• Engage in package design, including interposer and RDL design.
• Collaborate closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.
• Join research programs to implement new ideas for future products and flows.
• Lead a layout team to complete a full design block.
• Mentor junior layout engineers or interns.

Impact

• Drive the development of high-performance Analog IPs that power cutting-edge technologies.
• Enhance the layout design process for improved efficiency and quality.
• Ensure the robustness and reliability of our designs through meticulous verification processes.
• Contribute to the integration of complex layouts into top-level designs.
• Foster collaboration and knowledge sharing across global teams.
• Mentor and develop the next generation of layout engineers.

Requirements

• BS in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in custom layout.
• Proficiency with layout entry tools: Cadence, Synopsys.
• Experience with layout verification tools: Mentor Calibre, Synopsys ICV.
• Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.
• Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.
• Experience mentoring/leading junior layout engineers.
• Ability to write layout review presentations and layout verification reports.
• Good English communication skills.

Team

You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Designing, developing, and maintaining Speed Adapter solutions for advanced protocols, including PCIe and CXL. Implementing protocol functionality on FPGA-based platforms to bridge real-world I/O with DUTs running at reduced speeds on emulation and prototyping systems. Collaborating with IP, emulation, and prototyping teams to deliver comprehensive, end-to-end system-level validation solutions. Developing and debugging RTL, firmware, and system-level components for Speed Adapter products. Supporting seamless integration with ZeBu and HAPS platforms, including creating example designs and reference flows. Participating in customer escalations, conducting root-cause analysis, and delivering solutions for complex system-level issues. Contributing to roadmap planning, feature definition, and technical differentiation versus competitive solutions.

Enable customers to connect pre-silicon designs to real devices, testers, and hosts with unmatched fidelity and performance. Advance industry-leading system-level validation technology for top semiconductor and hyperscale customers. Shape the adoption and implementation of next-generation protocols such as PCIe Gen6/Gen7 and CXL3.x/4.0. Drive innovation in hardware-assisted verification, influencing patent-pending technologies that differentiate Synopsys solutions. Enhance integration across IP, emulation, prototyping, and real-world connectivity to deliver robust validation platforms. Support global teams and customers, fostering technical excellence and collaborative problem-solving.

12 years+ relevant experience Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. Strong hands-on experience with PCIe and/or CXL protocols, including implementation and debugging. Solid understanding of digital design, RTL development, and FPGA-based systems. Experience with system-level validation, emulation, or prototyping environments. Familiarity with high-speed serial interfaces and real-world I/O connectivity. Strong debugging skills across RTL, firmware, and hardware/software boundaries. Ability to work effectively in a cross-geography, cross-functional team.

Innovative thinker with a strategic mindset. Collaborative team player who values diverse perspectives. Excellent communicator and technical mentor. Resilient problem-solver, able to navigate ambiguity and complexity. Customer-focused, with a commitment to delivering high-impact solutions. Adaptable and proactive, eager to stay ahead in a fast-evolving technology landscape.

You'll join the Speed Adapter engineering team within Synopsys' HW-Assisted Verification (HAV) organization. This talented group is dedicated to developing and deploying industry-leading Speed Adapter solutions that bridge advanced protocols and real-world interfaces with ZeBu emulation and HAPS prototyping platforms. The team collaborates globally across IP, emulation, and prototyping domains to deliver robust, high-performance system validation solutions, directly impacting the success of top semiconductor and hyperscale customers.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You will be a part of a fast-growing analog and mixed-signal R&D team, dedicated to developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You'll interact with a global, dynamic, multi-cultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

As a Staff Engineer, you will be responsible for:

Developing and/or validating analog circuits considering electrical specifications and reliability constraints. Documenting simulation results and analyzing performance. Evaluating the impact of parasitic effects related to layout implementations and working with the layout team to minimize such effects, improving performance, power, and area. Defining and planning analog design activities for high-speed SerDes products. Collaborating with a global team of engineers to integrate and verify design solutions. Continuously learning and applying the latest advancements in FinFET/GAA process nodes to enhance design efficiency.

You will contribute to the development of high-speed SerDes products that enable high-performance chip-to-chip communications. You will enhance the performance, power efficiency, and reliability of analog integrated circuits in advanced CMOS technologies. You will support the integration of more capabilities into System-on-Chip (SoC) designs, accelerating time-to-market for innovative products.

You will be a part of a dynamic, multicultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

The ideal candidate will have a good understanding of CMOS technologies and analog circuit design principles. They will have strong analysis, problem-solving, and organizational skills. They will have experience in analog and mixed-signal block design, with a focus on high-speed SERDES. They will be proficient in documenting and analyzing simulation results. They will be familiar with IC design packages and UNIX operating systems.

You will be a collaborative team player who thrives in a global, multicultural environment. You will be an effective communicator with strong written and verbal skills in English. You will be a proactive and self-motivated individual with a passion for innovation and continuous learning. You will be an analytical thinker with the ability to tackle complex design challenges and find creative solutions. You will be a detail-oriented engineer who values precision and accuracy in their work.

You will be rewarded with a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide,and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Internship Experience:

• Plan and execute system-level testing for PCIe6 and PCIe7 protocols, focusing on reproducing and debugging customer issues with SNPS PHY.
• Develop and maintain Python-based test scripts to automate validation processes.
• Utilize lab instrumentation to conduct hands-on experiments and gather critical data.
• Collaborate with engineering teams to report findings, discuss next steps, and contribute to solutions that directly impact customer satisfaction.
• Engage in creative problem-solving, proactively seeking new approaches to resolve complex technical challenges.

What You'll Need:

• Currently pursuing a master’s degree in Electronic Engineering, Computer Science, or a related field.
• Strong programming skills in Python,ability to develop and troubleshoot test automation scripts is essential.
• Previous experience with lab instrumentation and hands-on testing environments, is a plus.
• Familiarity with high-speed SerDes protocols such as PCIe.
• Proactive and persistent approach to problem-solving, with a curious mindset and eagerness to learn.
• Effective communication skills to clearly report findings and collaborate within a team.

Key Program Facts:

• Program Length: 6 months
• Location: Lagoas Park, Oeiras (Lisbon)
• Working Model: In-office
• Full-Time preferred
• Expected start Date: May timeframe preferred

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As a High-Speed Interface Digital Design Manager, you will be responsible for managing and mentoring engineers, fostering a culture of innovation, ownership, and continuous improvement. You will drive architecture specification, digital design, and verification activities for current and next-generation products, engaging with customers to manage escalations, facilitate pre- and post-sales discussions, and ensure their requirements are met.

Key responsibilities include:

• Leading a high-performing digital and verification engineering team focused on the design and delivery of advanced SerDes IP
• Managing and mentoring engineers, fostering a culture of innovation, ownership, and continuous improvement
• Driving architecture specification, digital design, and verification activities for current and next-generation products
• Engaging with customers to manage escalations, facilitate pre- and post-sales discussions, and ensure their requirements are met

Requirements include:

• Bachelor's or Master's degree in Electrical Engineering or related field
• 10+ years of hands-on digital design and verification experience in the semiconductor industry
• 5+ years of proven leadership and people management experience, preferably in ASIC or IP development environments
• Deep knowledge of the ASIC development flow, including architecture specification, digital design, and verification methodologies
• Experience with high-speed interface protocols (e.g., PCIe, Ethernet, USB) and digital signal processing techniques
• Expertise in managing customer escalations and facilitating technical discussions during pre- and post-sales phases
• Proficiency with industry-standard EDA tools, scripting, and project management platforms

Benefits include:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

If you are a strong leader with excellent team-building and mentoring skills, a customer-focused and results-oriented individual with sound decision-making abilities, a collaborative communicator able to build strong cross-functional alliances, organized, detail-oriented, and adept at managing multiple priorities efficiently, adaptable, proactive, and committed to continuous improvement, we encourage you to apply.

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As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.

Responsibilities:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

Requirements:

• Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.

Who You Are:

• Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.
• Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
• Collaborative team player who builds productive relationships and networks effectively.
• Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.
• Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.
• Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:

You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.

What You’ll Be Doing:

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.
• Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.
• Present technical results internally and externally to customers and industry groups.
• Oversee physical layout to address parasitics and reliability concerns.
• Document features and test plans, and support post-silicon analysis and updates.

The Impact You Will Have:

• Advance industry-leading SERDES IP for next-generation SoCs.
• Enhance product differentiation and customer value.
• Streamline design processes for quality and time-to-market.
• Mentor junior team members and share best practices.
• Influence technical direction and innovation at Synopsys.
• Support customer success and product reliability.

What You’ll Need:

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.
• Expertise in transistor-level CMOS design and SERDES sub-circuits.
• Proficiency with schematic, layout, and verification tools; SPICE simulators.
• Experience with scripting languages (Verilog-A, TCL, Python, etc.).
• Strong communication and documentation skills.

Who You Are:

• Technical leader and mentor
• Collaborative and proactive
• Analytical and detail-oriented
• Adaptable and innovative

The Team You’ll Be A Part Of:

A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.

What You’ll Be Doing:

• Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.

• Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.

• Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.

• Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.

• Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.

• Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.

The Impact You Will Have:

• Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.

• Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.

• Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.

• Drive advancements in deep submicron CMOS technology adoption and integration.

• Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.

• Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.

What You’ll Need:

• MSc in Electrical/Computer Engineering (or equivalent).

• Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.

• Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).

• Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.

• Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.

• Strong skills in UNIX environments, including shell scripting and command-line operations.

• Familiarity with scripting languages such as TCL and Python.

Who You Are:

• Excellent problem-solving, organizational, and communication skills.

• Self-motivated and proactive, with the ability to work independently and as part of a team.

• Effective collaborator who values diverse perspectives and fosters inclusive teamwork.

• Adaptable and open to new challenges, with a commitment to continuous improvement.

• Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.

The Team You’ll Be A Part Of:

You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are an expert in high-speed analog design, with hands-on experience in wireline or optical SerDes above 200GBaud. You excel with PLLs, ILOs, DLLs, and phase mixers, as well as transmitters, serializers, optical drivers, receiver analog front ends, TIAs, and data converters.

Designing advanced SerDes and clocking circuits for ultra-high-speed data. Developing transmitters, serializers, and optical drivers. Creating receiver analog front ends and TIAs. Optimizing signal integrity and power usage. Collaborating across global teams. Mentoring junior engineers.

Enable next-gen connectivity solutions. Strengthen Synopsys' technology leadership. Accelerate product innovation and time-to-market. Improve reliability and performance of industry-leading chips. Foster technical growth across teams. Influence industry standards.

Our ideal candidate has a BSEE with at least 8+ years of direct industry experience. They must have extensive analog/SerDes IC design experience above 200GBaud, expertise with PLLs, DLLs, ILOs, phase mixers, and related circuits, proficiency in EDA tools and advanced process technologies, strong signal integrity and layout skills, and lab validation and debugging experience.

Collaborative and proactive leader. Detail-oriented problem solver. Effective technical communicator. Innovative and curious. Supportive mentor.

Join an elite analog design team focused on high-speed connectivity and SerDes IP, collaborating globally to deliver breakthrough solutions.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are an experienced Analog Design Manager with a passion for high-speed SerDes technology. You have a proven track record in leading teams to develop cutting-edge analog integrated circuits. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP, combined with your strong leadership skills, enables you to guide a team through complex design challenges. You thrive in a collaborative environment, working alongside analog and digital designers from diverse backgrounds. Your technical proficiency is complemented by your ability to develop schedules and action plans that ensure project success. With excellent communication and documentation skills, you effectively present design activities and solutions to critical issues. You are committed to fostering an environment of continuous improvement and operational excellence.

What You’ll Be Doing:

Directing and guiding the activities of a team of analog designers developing high-speed SERDES IP. Conducting design reviews and evaluating the final results of simulation and electrical characterization reports. Presenting the results of design activities, technology assessments, or critical issue investigations and making recommendations for actions necessary to achieve desired results. Selecting, developing, and evaluating personnel to ensure the efficient operation of the team. Developing schedules and action plans to meet overall project timelines. Reviewing documented design features and test plans. Ensuring that the team follows processes and operational policies for maximum design quality. Consulting on the electrical characterization of the SerDes IP product and proposing solutions for post-silicon design updates.

What You’ll Need:

B.Tech/BE/M.Tech/MS in Electronics Engineering. 8+ years of experience in Analog Design for High-Speed SerDes applications. 3-5 years of experience in a management or supervisory role. In-depth familiarity with transistor level circuit design and sound CMOS design fundamentals. Detailed design experience with SerDes sub-circuits such as receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers,voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, and DAC, DSP, Signal Integrity Familiarity with both analog and digital circuits and issues related to interfacing and timing between them. Aware of ESD issues (i.e. circuit techniques, layout). Familiarity with custom digital design (i.e. highspeed logic paths). Knowledge of design for reliability (i.e. EM, IR, aging, etc.). Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.). Good communication and documentation skills.

The Impact You Will Have:

Driving the development of high-speed SerDes IP that meets industry standards and customer requirements. Fostering innovation and excellence within the analog design team. Ensuring the delivery of high-quality, reliable analog integrated circuits. Contributing to the advancement of Synopsys' technology portfolio in the analog and mixed-signal domains. Enhancing the performance and efficiency of our high-speed communication products. Supporting the growth and development of team members through effective leadership and mentorship.

Who You Are:

You are a proactive leader with a strong technical background in analog design. You possess excellent problem-solving skills and the ability to make sound decisions under pressure. Your collaborative nature allows you to work effectively with cross-functional teams. You are detail-oriented and have a keen eye for quality. Your passion for continuous learning and improvement drives you to stay updated with the latest industry trends and technologies. You are committed to fostering a positive and inclusive team culture, encouraging innovation and excellence.

The Team You’ll Be A Part Of:

You will be part of a fast-growing analog and mixed-signal R&D team developing high-speed analog integrated circuits in the latest FinFET process nodes. The team is composed of talented analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking a Senior High-Speed IO Architect to join our team. As a Senior High-Speed IO Architect, you will be responsible for driving integration and delivery of high-speed I/O designs from concept to production.

Responsibilities

• Drive integration and delivery of high-speed I/O designs from concept to production.
• Collaborate with architecture and design teams for optimal circuit performance.
• Lead cross-functional teams, aligning IP and SoC design groups.
• Recruit, train, and mentor engineering talent.
• Ensure designs meet performance, power, area, and reliability goals.
• Manage post-silicon verification and advanced interface development.

The Impact You Will Have

• Drive innovation in high-speed I/O solutions.
• Elevate Synopsys' leadership in silicon IP.
• Build and sustain a world-class engineering team.
• Ensure product quality and customer satisfaction.
• Enable seamless integration of advanced interfaces.
• Deliver scalable solutions for industry leaders.

What You’ll Need

• 15+ years engineering experience in high-speed mixed-signal IC design.
• Expertise across full product lifecycle.
• Leadership in managing engineering teams.
• Strong understanding of advanced technology nodes.
• Experience recruiting and mentoring staff.
• Excellent communication and project management skills.
• UCIe Die-to-Die PHY experience required.

Who You Are

• Strategic thinker and collaborative leader.
• Clear communicator and mentor.
• Adaptable, detail-oriented, and quality-driven.

The Team You’ll Be A Part Of

Join a world-class engineering team pioneering high-speed I/O and interface technologies, committed to innovation, collaboration, and technical excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are an accomplished engineering leader with more than a decade of hands-on experience in SoC verification, emulation, and system-level validation. You thrive at the intersection of advanced hardware-assisted verification (HAV) and simulation acceleration (SimXL), bringing a deep understanding of complex SoC architectures, memory subsystems, and high-speed interconnects.

Architecting and leading Hardware-Assisted Verification and Simulation Acceleration solutions for large-scale SoCs and multi-die systems.

Driving end-to-end SimXL deployments, including use-case definition, performance optimization, and methodology standardization.

Defining and owning system-level verification and acceleration strategies spanning simulation, emulation, and prototyping.

Bridging gaps between RTL simulation, emulation, and software bring-up to enable early and scalable system validation.

Leading complex customer engagements involving HAV platforms, simulation acceleration, and hybrid verification flows.

Translating customer verification challenges into scalable, reusable solution architectures and acting as a technical authority in escalations.

Driving innovation in HAV and SimXL methodologies, including automation, reuse, and productivity frameworks leveraging AI/GenAI-assisted approaches.

Collaborating with R&D, Product Management, and Applications teams to influence product roadmaps and feature requirements.

Accelerate customer verification cycles, enabling earlier software and system bring-up for complex SoC designs.

Define and scale best-in-class HAV and SimXL solutions across strategic accounts, enhancing customer outcomes.

Drive measurable improvements in performance, capacity, and debug productivity for verification workflows.

Shape the future of AI-assisted verification and solution deployment within Synopsys and across the industry.

Act as a key technical leader in advancing the organization’s verification acceleration strategy.

Mentor and empower senior engineers, fostering a culture of innovation and technical excellence.

Influence product direction and solution roadmaps through deep technical insights and customer engagement.

10+ years of experience in SoC verification, emulation, or system-level validation.

Deep hands-on expertise in Hardware-Assisted Verification, simulation acceleration, and hybrid verification flows.

Strong experience with emulation platforms and accelerated simulation environments.

Solid understanding of SoC architectures, interconnects, memory subsystems, and software bring-up challenges.

Proven ability to design and deploy scalable verification solutions for complex designs.

Experience with system-level testbenches, transactors, and acceleration frameworks.

Exposure to GenAI or AI-assisted techniques applied to verification, debug, or solution automation.

Background in high-speed interfaces, memory subsystems, or multi-die architectures.

Track record of creating reusable assets, methodologies, or automation frameworks.

Experience influencing product direction or defining solution roadmaps.

Innovative thinker with a passion for driving technological advancement and automation.

Collaborative leader who mentors and inspires teams across geographies.

Strong communicator adept at translating complex technical concepts for diverse audiences.

Customer-focused problem solver with a commitment to delivering impactful solutions.

Adaptable and resilient in fast-paced, matrixed environments.

Detail-oriented, analytical, and proactive in identifying and addressing challenges.

You will join a dynamic, cross-functional team dedicated to advancing verification acceleration solutions for Synopsys’ strategic customers. The team comprises experts in HAV, simulation acceleration, R&D, product management, and applications engineering, all working collaboratively to define and deploy innovative methodologies.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a seasoned analog architect with deep expertise in high-speed interface design. You enjoy leading technical coordination, collaborating with diverse teams, and driving innovation. Your communication skills and mentoring abilities help foster a positive, inclusive engineering environment. You’re ready to make an impact on our advanced 224G and future 448G products.

Responsibilities: Coordinating engineering efforts for 224G and 448G analog products Architecting high-speed SerDes solutions Collaborating with cross-functional teams Mentoring junior engineers Defining design standards and methodologies Managing project timelines and resources Interfacing with customers and key external partners on SerDes technical topics

The Impact You Will Have: Enable launch of industry-leading analog products Drive technical excellence and innovation Mentor and develop engineering talent Set new benchmarks power, latency, area, and performance Shape Synopsys’ future in high-speed connectivity Accelerate adoption of advanced SerDes IP

What You’ll Need: Experience in high-speed analog IC design (224G/448G) Strong technical coordination skills Proficiency with EDA tools Solid understanding of circuit architecture and signal integrity Knowledge of semiconductor manufacturing processes

Who You Are: Innovative and collaborative leader Excellent communicator Detail-oriented and quality-focused Adaptable and eager to learn

The Team You’ll Be A Part Of: Join a multidisciplinary engineering team dedicated to developing high-speed analog IP for next-generation silicon platforms.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details during the hiring process.

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Your expertise in high-speed, high-density board design enables you to tackle complex challenges, from 200G signaling to intricate HDI stack-ups. You are passionate about optimizing performance and reliability, and you possess a deep understanding of the full hardware development cycle—from schematic entry to final deliverables.

You are proficient with industry-standard EDA tools and comfortable managing libraries and constraints, ensuring accuracy and efficiency throughout the design process. Your strong communication skills enable you to share ideas, learn from others, and drive progress within a diverse team.

Design and optimize PCB layouts for cutting-edge HAPS hardware platforms, focusing on high-speed and high-density applications.

Collaborate with global teams to perform placement of small and large PCBAs, ensuring efficient use of space and signal integrity.

Execute complex routing tasks across multi-layer boards (from 8–16 layers up to 50+ layers), including blind and buried vias.

Work closely with colleagues on stack-up design and collaboration, contributing to robust and reliable board architectures.

Generate and manage PCB deliverables, including manufacturing files, BOMs, and assembly documentation.

Conduct DFx (Design for Excellence) checks, ensuring manufacturability, reliability, and compliance with industry standards.

Maintain and update EDA libraries, supporting rapid development and accurate component integration.

Participate in schematic entry, constraint management, and overall hardware design workflow.

Enable Synopsys to deliver industry-leading FPGA-based prototyping systems for semiconductor innovation.

Enhance product reliability and performance through meticulous PCB design and layout optimization.

Accelerate development cycles by collaborating across time zones and ensuring seamless deliverables.

Support high-speed signaling and connectivity, powering next-generation AI, automotive, and IoT solutions.

Drive improvements in manufacturability and quality, reducing costs and increasing customer satisfaction.

Contribute to the global success of HAPS hardware platforms, making a tangible difference in the tech industry.

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Key Responsibilities:

• Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.
• Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.
• Define, develop, and execute functional verification plans and test strategies.
• Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.
• Generate VCD files and perform power analysis/reporting using PrimeTime PX.

Requirements:

• Minimum of 2 years of experience in ASIC RTL design flow.
• Proficiency in RTL and GLS verification, with strong debugging capabilities.
• Excellent teamwork and communication skills, with professional proficiency in English.
• Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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Your work will involve hands-on troubleshooting and repair of compute, storage, interconnect and cooling systems to keep our large GPU/CPU cluster healthy and scalable. You will also be responsible for leading complex interventions, advanced diagnostics, guiding and uplifting L1s, process and automation, safety and compliance, and parts and logistics.

To be successful in this role, you will need 5+ years of experience in data center/server hardware or L2/L3 hardware support, with proven complex hands-on work in production (HPC/AI/Cloud at scale). You should have end-to-end hardware expertise, including comfort with CPU/memory/PCIe cards, NICs, PSUs, drives, network, power and cooling. You should also be confident in analyzing BMC/IPMI logs, linux software logs and crashes simple CLI checks, and have methodical root cause analysis skills.

The ideal candidate will be willing to travel between sites (Paris area or nearby regions, occasionally in Europe or US) and have a strong understanding of safety and discipline, including impeccable ESD/LOTO/PPE habits, zero rough handling, and clean, labeled, auditable work.

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Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.

As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.
• You will be responsible for micro-architecture using sophisticated verification methodologies.
• As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

Requirements:

• Bachelors or Master’s Degree (or equivalent experience)
• 3+ years of relevant verification experience
• Experience in architecting test bench environments for unit level verification
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Prior Design or Verification experience of Coherent high-speed interconnects
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful
• Strong background developing TB's from scratch using SV and UVM methodology is desired
• C++ programming language experience, scripting ability and an expertise in System Verilog
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong debugging and analytical skills
• Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

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What you'll be doing:

• Lead the design, automation, and validation of System Level Tests (SLT) for HVM (High Volume Manufacturing) for complex, high power, high speed SOCs.
• Develop and integrate test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals.
• Partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.
• Drive custom SLT development to optimize system performance, power efficiency, and test coverage.
• Oversee handler selection, enablement, and hardware integration – including PCB design, socket selection, and temperature control systems.
• Improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes.
• Collaborate closely with OSATs on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.
• Support silicon qualification and reliability testing (HTOL, Burn in) at the system level.

What we need to see:

• MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience).
• 12+ years of experience in Systems level test, systems validation, and/or bench testing.
• Experience in new silicon bring up at the system level.
• Experience in driving SLT testing and deployment for HVM.
• Experience with testing and characterization of high power SOCs and High Speed I/Os.
• Knowledge of network topology and experience in network connectivity.
• Proficient in C#, C/C++, PERL, Python, .NET framework.
• Experience in Security provisioning and knowledge of fuse programming implementation.

Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

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Responsibilities:

• Silicon and board bring up, validation, and debug from prototype to production.
• Responsible for the GPU and SoC system qualification including feature checks, system stress at PVT conditions, testing of large number of systems and debug of issues affecting any unit of the chip or software.
• Debug complex ASIC and board issues related to logic design, signal integrity and power delivery in a high energy work environment, with a team that is the best in the business!
• Understand architecture of next generation chips, develop test plans, scripts and implement.
• Understand various HW features related to power, performance and safety.
• Drive the debug of Silicon, Board or Software issues involving many multi-functional teams.
• Develop new methodologies to improve the silicon validation process and take it to the next level!

Requirements:

• BTech/BE or MTech/ME degree in Electronics with 4+ years of work experience.
• Good knowledge in board and system design considerations, experience in silicon design/bring up.
• Hardware design experience related to high-speed subsystem design, High-speed IO protocols, and on-chip interconnect would be much appreciated.
• An understanding of PC architecture and various commonly used buses.
• Familiarity with scripting languages like perl and/or python.
• Very good problem solving and debugging skills.
• Strong data analysis and logical reasoning skills.
• Must be a standout colleague and ready to work with global teams from diverse cultural backgrounds.

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Your primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.

In addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.

You will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.

Finally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.

To be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.

Additionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.

If you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!

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We are seeking an Expert ECE - COSMOS project F/M/X to join our team at Eurostar. As an Expert ECE, you will be responsible for providing functional expertise on reference data and maintenance regimes for our continental fleet. You will also be responsible for following and piloting evolutions related to engineering data, including structures, maintenance regimes, updates, and consistency of reference data.

Responsibilities

• Provide functional expertise on reference data and maintenance regimes for the continental fleet (PBA/PBKA and, if applicable, the future Celestia fleet).
• Follow and pilot evolutions related to engineering data: structures, maintenance regimes, updates, and consistency of reference data.
• Act as a reference person within the Rolling Stock department for the target tools of the COSMOS project for creating and updating reference data.
• Develop new processes and procedures applicable during the different Go-Live phases of the project and contribute to updating the associated reference frameworks.
• Organize, facilitate, and follow up on workgroups with internal and external stakeholders to define new practices, inform teams, and facilitate their adoption.
• Be the point of contact for SNCF Engineering for all performances carried out in the context of the COSMOS project for Eurostar, and coordinate internal and external resources according to the project plan.
• Ensure expertise on maintenance reference data for the continental fleet in the new COSMOS tools: registration of trains, management of compositions, definition, and management of maintenance regimes.
• Define and make available performance indicators for your domain in the decision-making support system to be developed by Eurostar.
• Design and deliver training for users of the new tools, including creating training materials and supporting documentation.
• Provide on-site support during tests, Go-Live moments, and operational migration phases of data.
• Follow up and document all actions in project management tools to inform stakeholders of the project's progress.

Requirements

• You hold a degree in engineering or equivalent higher education.
• You have 10 years of experience in the field of railway engineering and maintenance.
• You have proven experience with high-speed trains, preferably TGV or equivalent.
• You have experience in project management.
• You master engineering reference data (structures, maintenance regimes, reference frameworks).
• You are familiar with IT tools and CMMS/GMAO systems.
• You have strong skills in facilitating workshops, making syntheses, and structuring action plans.
• You master French and English perfectly, both spoken and written.

Salary

The salary for this position is not specified.

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You'll work with our product owners to define features and requirements, produce system-level designs including selection of key technologies and components, then go on to design the schematics and PCBs.

You'll be responsible for planning your work and delivering against production schedules - this means strong analytical and estimation skills, and the ability to communicate effectively with technical and non-technical peers.

You'll spend a lot of your time designing and debugging hardware, so systematic measurement, analysis and fault-finding skills are essential.

Signal integrity, EMC and analogue debugging experience are also highly desirable.

You'll contribute to our roadmaps, helping determine what products we deliver and how we deliver them - this means seeing the big-picture and understanding our products, market and customers.

You'll be working with a team of experienced engineers who are on hand to support you in a friendly, social and inclusive environment where our shared passion for music and music tech is front and centre.

About you:

You bring energy, technical acumen, and a proven track record.

You've been responsible for delivering successful products to market in music tech, consumer electronics or a similar industry.

You're a proactive and pragmatic problem solver, able to find creative solutions to problems that others didn't see coming.

You're decisive, you back yourself, and you're able to bring others along with you.

You build strong working relationships with your peers; you support and mentor others and know when to seek support yourself.

You think strategically and can work across multiple projects while still diving down into detail.

Most importantly of all, you love what you do - designing and shipping products that help millions of people make music.

Required skills and experience – you should apply for this role if you have:

• A degree or HND in Electronics Engineering (or related subject).

• Taken ownership of commercial designs throughout the full development process and delivered them successfully.

• Experience of designing hardware that balances quality, cost and time to market.

• The ability to plan and deliver to deadlines, learning and applying new skills quickly.

Technical knowledge we're looking for:

• Analogue electronics for audio applications (low-noise design, signal processing).

• High speed digital interfaces (e.g. SDRAM, I2S, USB, RGMII).

• Linear and switching power supply design, PMICs, USB PD.

• Embedded systems.

Further desirable experience:

• Design of products for high-volume mass production.

• Design and debug for EMCD and RED approvals.

• An active interest in making music and music technology.

• Working with ODM/JDM/CDS models.

• Altium Designer (schematic and PCB layout)

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.

Technical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.

You bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You’ll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Fostering technical excellence and knowledge sharing across the organization.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Directly impact customer success by providing guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You’ll Need:

• 8+ years of experience in Firmware, ASIC design, verification, system validation, and technical roles.
• Be results driven
• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
• In-depth knowledge of system-level validation for high-speed interface PHY
• Proven track record of working cross-functionally and driving issues to closure
• Knowledge of mixed-signal design
• Experience in working in cross-functional collaborations
• Be an excellent communicator and a beacon for change

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

XML job scraping automation by YubHub

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15391

Remote Eligible

No

Date Posted

02/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.

You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.

Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.

What You’ll Be Doing:

• Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

• Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

• Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

• Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

• Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

• Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.

• Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.

The Impact You Will Have:

• Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.

• Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.

• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.

• Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.

• Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.

• Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.

What You’ll Need:

• MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

• Proven expertise with FinFET technologies and CMOS tape-outs.

• Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

• Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

• Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

• Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

• Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

• Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

• Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

• Excellent communication and documentation skills.

Who You Are:

• Collaborative and open-minded, eager to share knowledge and learn from others.

• Detail-oriented and thorough, with a commitment to delivering high-quality results.

• Analytical thinker with strong problem-solving abilities and a proactive approach.

• Excellent communicator, able to convey complex technical concepts clearly.

• Adaptable and resilient in fast-paced, dynamic environments.

• Committed to fostering an inclusive, innovative, and supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and patern

XML job scraping automation by YubHub

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk.

You Are:

You are a talented Firmware Development Engineer with a passion for embedded systems and software innovation. You thrive in environments where high-speed and precision matter, bringing a strong programming background and an aptitude for developing reliable, scalable firmware solutions. Your expertise in C programming and familiarity with scripting languages such as Perl, TCL, or Python make you a versatile contributor. You are experienced in developing firmware for complex embedded systems and high-speed interfaces, and you take pride in rigorous problem-solving and debugging. You enjoy collaborating with hardware engineers to ensure seamless integration between firmware and hardware, and you are skilled at navigating verification and emulation environments to enhance product quality. Your attention to detail and commitment to delivering robust, high-quality firmware are matched by your ability to adapt to new challenges in a fast-moving industry. You value diversity and inclusion, and you are comfortable working in a dynamic, multicultural team. Whether you are mentoring junior engineers, spearheading integration efforts, or contributing to pre-silicon environments, you consistently demonstrate initiative, innovation, and a collaborative spirit. If you are excited to power the Era of Smart Everything and help shape tomorrow’s breakthroughs, you’ll find your place at Synopsys.

What You’ll Be Doing:

• Designing and implementing firmware for high-speed PHY IPs using C programming.
• Developing and maintaining software development environments and tools to streamline workflows.
• Collaborating with hardware engineers to ensure firmware compatibility and optimized integration with hardware designs.
• Conducting rigorous unit testing and debugging to ensure high-quality firmware performance
• Utilizing verification and emulation environments to enhance the integration process and support pre-silicon development.
• Documenting design processes, maintaining code quality, and ensuring compliance with industry standards.
• Staying current with emerging technologies in embedded systems and high-speed interfaces.

The Impact You Will Have:

• Accelerating the integration of advanced capabilities into SoCs through robust firmware development.
• Enhancing product reliability, performance, and time-to-market for customers in diverse industries.
• Supporting the development of differentiated products that power innovations like AI, 5G, IoT, and self-driving cars.
• Reducing risk and optimizing project outcomes by leveraging your expertise in embedded systems and high-speed interfaces.
• Driving cross-functional collaboration between software and hardware teams to deliver seamless solutions.
• Contributing to Synopsys’ leadership in silicon IP and embedded technology by delivering high-quality, scalable firmware.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Strong programming skills in C and familiarity with software development methodologies.
• Experience with scripting languages such as Perl, TCL, or Python.
• Proven experience in firmware development for complex embedded systems or high-speed interfaces.
• Excellent problem-solving and debugging skills, especially in unit testing and integration scenarios.
• Knowledge of high-speed interface protocols such as DDR, LPDDR (preferred).
• Experience with pre-silicon environments, including verification or emulation (preferred).

Who You Are:

• Analytical, detail-oriented, and committed to delivering high-quality results.
• Collaborative and effective communicator, able to work across diverse teams and disciplines.
• Adaptable and eager to learn new technologies and methodologies.
• Proactive, with a passion for innovation and continuous improvement.
• Inclusive and respectful, supporting a diverse and multicultural work environment.

The Team You’ll Be A Part Of:

You will join a vibrant Silicon IP engineering team dedicated to developing and integrating advanced firmware for high-speed interfaces. The team consists of experts in embedded systems, software, and hardware design, working together to solve complex challenges and deliver industry-leading solutions. Collaboration, innovation, and a commitment to excellence define the team’s culture as they support customers in bringing differentiated products to market quickly and efficiently.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

XML job scraping automation by YubHub

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted 02/24/2026

Category EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.

What You’ll Be Doing:

• Developing robust functional verification environments (test benches) for high-speed PHY IPs.
• Creating comprehensive test plans and detailed test cases to ensure thorough coverage.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Executing simulations, generating both random and focused stimuli, and performing coverage analysis to validate design functionality.
• Building architectural and micro-architectural understanding of complex digital design blocks under verification.
• Collaborating with cross-functional engineering teams to resolve issues and optimize verification strategies.
• Contributing to process improvements and sharing best practices within the team.

The Impact You Will Have:

• Accelerate the integration of advanced capabilities into SoCs, enabling customers to meet performance, power, and size requirements.
• Ensure the delivery of differentiated, high-quality silicon IP products with reduced risk and faster time-to-market.
• Drive innovation in verification methodologies that support the development of next-generation technologies, including AI, cloud, 5G, and IoT.
• Enhance the reliability and functionality of high-speed digital interfaces, powering smart devices across industries.
• Support Synopsys’ leadership in chip design and software security by maintaining rigorous verification standards.
• Contribute to a culture of inclusion and excellence, mentoring junior engineers and promoting diversity within the team.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Solid background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Experience with industry-standard development and verification tools and methodologies.
• Excellent diagnostic and problem-solving skills for identifying and resolving verification issues.
• Preferred: Experience with formal verification, System Verilog Assertions, and code/functional coverage implementation and analysis.
• Preferred: Familiarity with scripting languages such as Perl, TCL, and Shell scripting.
• Preferred: Knowledge of high-speed interface protocols such as DDR and LPDDR.

Who You Are:

• Detail-oriented and analytical thinker with a proactive approach to problem-solving.
• Effective communicator who thrives in collaborative and diverse team environments.
• Adaptable and eager to learn new technologies and methodologies.
• Resourceful and resilient in overcoming technical challenges.
• Committed to fostering inclusion, respect, and continuous improvement within the workplace.

The Team You’ll Be A Part Of:

You will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.

You Are:

You are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.

What You’ll Be Doing:

• Developing functional verification environments (test benches) for complex digital design blocks.
• Creating comprehensive test plans and test cases to ensure thorough coverage and robust design validation.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Performing simulations, generating random and focused stimulus, and conducting coverage analysis to verify functionality.
• Building architecture and micro-architecture knowledge of digital blocks under test to drive effective verification strategies.
• Collaborating with cross-functional teams to share insights and resolve issues throughout the pre-silicon verification process.
• Utilizing industry-standard verification tools and methodologies to enhance efficiency and quality.

The Impact You Will Have:

• Ensuring the reliability and performance of high-speed PHY IPs through rigorous pre-silicon functional verification.
• Accelerating product time-to-market by identifying and resolving design issues early in the development cycle.
• Reducing risk for customers by delivering thoroughly verified and differentiated silicon IP solutions.
• Supporting the development of next-generation products that power innovations in AI, 5G, IoT, and more.
• Contributing technical expertise to the team, fostering a culture of continuous improvement and learning.
• Promoting collaboration and knowledge sharing across engineering teams to achieve collective goals.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Excellent diagnostic and problem-solving skills for debugging and optimizing verification flows.
• Experience with industry-standard development and verification tools and methodologies.
• Familiarity with scripting languages such as Perl, TCL, and Shell scripting (preferred).
• Experience with formal verification, System Verilog Assertions, and code/functional coverage analysis (preferred).
• Knowledge of high-speed interface protocols such as DDR and LPDDR (preferred).

Who You Are:

• Analytical thinker with a strong eagerness to learn and grow.
• Dynamic personality, energizing and motivating team members.
• Strong communicator, able to collaborate effectively in diverse environments.
• Self-motivated leader, capable of driving verification activities independently and as part of a team.
• Detail-oriented, ensuring thorough validation and quality in all deliverables.

The Team You’ll Be A Part Of:

You will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.

A technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.

You bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You'll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Mentoring and coaching engineering teams, fostering technical excellence and knowledge sharing across the organization.
• Collaborating with cross-functional groups and customers to resolve challenges, ensure quality design, and meet aggressive project milestones.
• Driving continuous improvement in functional and performance testing on hardware and test-chips, and leading architectural refinements based on analysis.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Driving cross-team synergy, technical mentorship, and a culture of continuous learning and inclusivity.
• Directly impact customer success by providing expert guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You'll Need:

• 15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.

• Be results driven

• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.

• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.

• In-depth knowledge of system-level validation for high-speed interface PHY

• Proven track record of working cross-functionally and driving issues to closure

• Knowledge of mixed-signal design

• Experience in working in cross-functional collaborations

• Be an excellent communicator and a beacon for change

• Excellent debugging, analytical, and problem-solving skills

• Working knowledge of scripting in languages such as Python and/or Perl

• Good understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon

• Good interpersonal skills, ability & desire to work as a standout colleague

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

#LI-DP1

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness
• Time Away
• Family Support
• ESPP
• Retirement Plans
• Compensation

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You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.

You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.

You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.

You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.

You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Responsibilities:

• Oversee day-to-day AP operations within the Shared Services Centre
• Ensure timely and accurate processing of invoices, payments, vendor reconciliations, and compliance with internal controls
• Manage a team of AP analysts
• Drive process improvements
• Maintain service level agreements (SLAs)
• Support stakeholders across business units and regions

Requirements:

• 4-6+ years of experience in Accounts Payable, preferably in an SSC environment
• Solid understanding of accounting principles, tax rules, and internal controls
• Hungarian and English language knowledge
• SAP S4/Hana knowledge
• Strong communication and stakeholder-management abilities
• Ability to resolve complex issues independently
• High accuracy, speed, and decision-making abilities in a high-volume environment

We offer:

• Group accident insurance
• Private medical insurance
• Free fruits
• Flexible working time
• Home office possibility (60%)
• International projects
• Business trips
• Travel reimbursement
• Relaxation and fitness room
• Cafe and restaurant in the office building

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About the Team

We build foundational AI infrastructure that enables large-scale training and inference across diverse workloads and rapidly evolving hardware generations. Our work directly shapes how AI systems are designed, deployed, and scaled today and into the future. Engineers on this team operate with end-to-end ownership, deep technical rigor, and a strong bias toward real-world impact.

Microsoft Superintelligence Team

Microsoft Superintelligence team’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

This role is part of Microsoft AI’s Superintelligence Team. The MAIST is a startup-like team inside Microsoft AI, created to push the boundaries of AI toward Humanist Superintelligence—ultra-capable systems that remain controllable, safety-aligned, and anchored to human values. Our mission is to create AI that amplifies human potential while ensuring humanity remains firmly in control. We aim to deliver breakthroughs that benefit society—advancing science, education, and global well-being. We’re also fortunate to partner with incredible product teams giving our models the chance to reach billions of users and create immense positive impact. If you’re a brilliant, highly-ambitious and low ego individual, you’ll fit right in—come and join us as we work on our next generation of models!

Responsibilities

Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks. Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements. Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems. Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps. Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations. Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs. Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams. Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

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We pursue this mission through deep hardware–software co-design, combining rigorous systems thinking with hands-on engineering. The team invests heavily in understanding real production workloads large-scale training, inference, and emerging multimodal models and translating those insights into concrete improvements across the stack: from kernels, runtimes, and distributed systems, all the way down to silicon-level trade-offs and datacenter-scale architectures.

This role sits at the boundary between exploration and production. You will work closely with internal infrastructure, hardware, compiler, and product teams, as well as external partners across the hardware and systems ecosystem. Our operating model emphasizes rapid ideation and prototyping, followed by disciplined execution to drive high-leverage ideas into production systems that operate at massive scale.

In addition to delivering real-world impact on large-scale AI platforms, the team actively contributes to the broader research and engineering community. Our work aligns closely with leading communities in ML systems, distributed systems, computer architecture, and high-performance computing, and we regularly publish, prototype, and open-source impactful technologies where appropriate.

Microsoft Superintelligence Team Microsoft Superintelligence team’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

This role is part of Microsoft AI’s Superintelligence Team. The MAIST is a startup-like team inside Microsoft AI, created to push the boundaries of AI toward Humanist Superintelligence—ultra-capable systems that remain controllable, safety-aligned, and anchored to human values. Our mission is to create AI that amplifies human potential while ensuring humanity remains firmly in control. We aim to deliver breakthroughs that benefit society—advancing science, education, and global well-being. We’re also fortunate to partner with incredible product teams giving our models the chance to reach billions of users and create immense positive impact.

Responsibilities Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks.

Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements.

Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems.

Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps.

Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations.

Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs.

Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams.

Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

Qualifications Bachelor’s Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Additional or Preferred Qualifications Master’s Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR Bachelor’s Degree in Computer Science or related technical field AND 12+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Strong background in one or more of the following areas: AI accelerator or GPU architectures Distributed systems and large-scale AI training/inference High-performance computing (HPC) and collective communications ML systems, runtimes, or compilers Performance modeling, benchmarking, and systems analysis Hardware–software co-design for AI workloads Proficiency in systems-level programming (e.g., C/C++, CUDA, Python) and performance-critical software development.

Proven ability to work across organizational boundaries and influence technical decisions involving multiple stakeholders. Experience designing or operating large-scale AI clusters for training or inference. Deep familiarity with LLMs, multimodal models, or recommendation systems, and their systems-level implications. Experience with accelerator interconnects and communication stacks (e.g., NCCL, MPI, RDMA, high-speed Ethernet or InfiniBand). Background in performance modeling and capacity planning for future hardware generations. Prior experience contributing to or leading hardware roadmaps, silicon bring-up, or platform architecture reviews. Publications, patents, or open-source contributions in systems, architecture, or ML systems are a plus.

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About the Team:

OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

Role Overview

We are seeking an experienced engineer to lead the development of advanced packaging technologies that enable next-generation, high-performance compute systems. This role sits at the intersection of chip architecture, package integration, and manufacturing scale-up, driving breakthroughs in performance, power, thermal, and reliability. The ideal candidate brings deep expertise in 2.5D and 3.5D large-reticle integration and Co-Packaged Optics (CPO) packaging, with a proven ability to translate advanced concepts into qualified, high-volume production solutions.

In this role you will:

• Architect, develop, and prototype advanced packaging solutions (2.5D/3D integration, large-format interposers/bridges, high-density substrates, advanced assembly flows), and drive end-to-end qualification for high-volume production.

• Develop packaging concepts and requirements to support CPO packaging, including optical/electrical co-integration considerations, thermal/mechanical constraints, and high-volume manufacturability.

• Lead large-reticle and multi-die integration strategies, including mechanical/thermal co-design, warpage control, and yield/reliability risk mitigation across package scale-up.

• Identify and solve fundamental technical challenges in package architecture, integration, and manufacturability for high-performance compute chips.

• Collaborate closely with cross-functional teams (silicon architecture, SI/PI, thermal, mechanical, system, test, and manufacturing) to align package development with product requirements and program milestones.

• Drive vendor engagement and technical alignment with external partners (foundry/OSAT/material/tool vendors), including technology selection, DOE planning, and qualification readiness.

You might thrive in this role if you have:

• Large-reticle / large-body-size integration, including interposer/bridge-based architectures, package-scale mechanical/thermal risk management, and manufacturability at scale.

• Hands-on experience with CPO packaging, including package-level optical integration constraints and cross-domain trade-offs (electrical/optical/thermal/mechanical).

• Proven track record developing and productizing large-format, high-power, high-speed advanced packaging technologies for high-performance compute products.

• In-depth expertise across advanced packaging techniques and platforms used in the semiconductor industry (2.5D, 3D stacking, interposers/bridges, high-density substrates, advanced materials and assembly).

• Strong understanding of chip–package co-design: how chip architecture, I/O, power delivery, and floorplan decisions interact with packaging architecture and constraints.

Preferred Qualifications

• Solid understanding of thermal and mechanical interactions in large-format packages (warpage, stress, lid/heat-spreader/cold-plate interfaces, material interactions).

• Working knowledge of reliability requirements and qualification methodologies for advanced packages (JEDEC/industry practices, failure analysis, DOE-driven learning cycles).

• Familiarity with system-level considerations and chip architecture fundamentals (I/O topology, HBM/advanced memory integration, SI/PI constraints, module-to-system integration).

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Product Designer, Business Products

Location

San Francisco

Employment Type

Full time

Location Type

On-site

Department

Product Design

Compensation

• $207K – $245K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the team

OpenAI’s mission is to ensure that general-purpose artificial intelligence benefits all of humanity. The ChatGPT team works across research, engineering, product, and design to bring OpenAI’s technology to the world. We serve a diverse audience of users who are already using ChatGPT daily in their lives and work.

We seek to learn from deployment and distribute the benefits of AI, while ensuring that this powerful tool is used responsibly and safely. Safety is more important to us than unfettered growth.

Design plays a critical role here. To succeed in our mission, it’s crucial that we make our technology intuitive and accessible. We’re hiring a product designer to create products that are easy to use, beautiful, and push the boundaries of what’s possible. As an early team member, you’ll have a huge part in shaping our product direction and design culture.

About the role

We're hiring product designers to join the Business Products team at OpenAI. Our team is growing rapidly as we build foundational tools and experiences for developers, startups, enterprise customers, and net-new B2B solutions. We're looking for versatile designers who thrive in complexity, care deeply about craft, and are excited to help shape the future of AI-powered platforms.

We have a variety of roles open across areas like developer tools, enterprise solutions, public sector initiatives, and 0-1 product incubations. Designers on these teams have a strong generalist skillset but also depth in technical experience, product thinking, systems, and a bias toward high-quality, usable interfaces.

What you’ll do:

• Partner with product, engineering, research, and go-to-market teams to define and build new tools and experiences from the ground up.

• Design thoughtful, scalable solutions for complex systems, especially in B2B or developer-facing domains.

• Create clear artifacts that guide decision-making and execution.

• Navigate ambiguity and help define the problem space before jumping into solutions.

• Contribute to a high-functioning, collaborative design culture that values speed and craftsmanship.

Who you are:

• You’ve designed and shipped complex, high-impact products, ideally in the B2B or developer tools space.

• You’re comfortable designing for ambiguity, and can lead design efforts from early discovery through implementation.

• You can zoom out to systems thinking and strategy, then zoom in to pixel-level details and user flows.

• You communicate clearly and proactively—both in visual design and written/spoken formats.

• You’re collaborative, curious, and energized by fast-paced, mission-driven work.

Why you’ll love this role:

• Opportunity to design at the cutting edge of AI technology, shaping how businesses integrate and benefit from AI tools.

• Influence the product direction of ChatGPT for Work as we build experiences tailored to enterprise environments.

• Join a collaborative, mission-driven team passionate about creating impactful products.

Preferred qualifications:

• 4+ years of experience designing digital products; open to more senior designers depending on role.

• Background in b2b software, developer platforms, or technical tools is a strong plus.

• Experience working with cross-functional teams in highly technical domains.

• Familiarity with Figma and modern design systems.

• Based in (or willing to relocate to) San Francisco or New York.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve this, we must be committed to transparency, accountability, and collaboration.

XML job scraping automation by YubHub

Location

Remote - US; San Francisco; Seattle

Employment Type

Full time

Location Type

Remote

Department

People

Compensation

• Remote$136K – $240K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team At OpenAI, we are dedicated to building safe artificial general intelligence (AGI) to benefit all of humanity. Our mission attracts the world’s top talent in science, engineering, and business to address one of the most ambitious challenges of our time.

This role sits within the Recruiting team and partners directly with OpenAI’s B2B Applications organization—the group responsible for building and scaling the products that bring OpenAI’s research to businesses, enterprises, and governments around the world. The Recruiting team plays a critical role in enabling this work by hiring exceptional talent who can operate in highly technical, fast-moving, and evolving product environments.

About the Role As a Technical Sourcer, you will be responsible for identifying and engaging top-tier engineering talent to support OpenAI’s B2B Applications teams. These teams build and operate the OpenAI API and Enterprise products that power AI-driven solutions for millions of developers and organizations globally.

You will partner closely with recruiters, hiring managers, and technical leaders across B2B Applications to build pipelines for highly specialized engineering roles, including product engineering, backend systems, and platform-adjacent teams. This role requires comfort sourcing in complex technical domains, navigating evolving product priorities, and operating with speed and rigor as the business scales.

In this role, you will:

• Lead sourcing strategies for engineering roles supporting B2B and enterprise-facing products.

• Build and maintain strong pipelines of passive candidates through proactive outreach, research, and networking.

• Partner closely with recruiters and hiring managers to understand role requirements, team needs, and shifting priorities.

• Leverage advanced sourcing tools and techniques to identify high-impact talent in competitive markets.

• Maintain accurate candidate data and sourcing metrics to inform strategy and execution.

You’ll thrive in this role if you:

• Have 6+ years of experience sourcing engineers, especially across product engineering, backend systems, or platform-adjacent roles.

• Have sourced engineers for B2B, enterprise, developer, or API-driven products.

• Can quickly understand complex technical requirements and translate them into effective sourcing strategies and outreach.

• Build strong partnerships with recruiters, hiring managers, and technical leaders in fast-moving environments.

• Can manage multiple searches simultaneously while maintaining a high quality bar

Adapt quickly as product priorities, org structures, and hiring needs evolve.

About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

XML job scraping automation by YubHub

Trust & Safety Operations Analyst

Location

San Francisco

Employment Type

Full time

Department

Compensation

• $189K – $280K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

At OpenAI, our Trust, Safety & Risk Operations teams safeguard our products, users, and the company from abuse, fraud, scams, regulatory non-compliance, and other emerging risks. We operate at the intersection of operations, compliance, user trust, and safety working closely with Legal, Policy, Engineering, Product, Go-To-Market, and external partners to ensure our platforms are safe, compliant, and trusted by a diverse, global user base.

We support users across ChatGPT, our API, enterprise offerings, and developer tools handling sensitive inbound cases, building detection and enforcement systems, and scaling operational processes to meet the demands of a fast-moving, high-stakes environment.

About the Role

We are seeking experienced, senior-level analysts who specialize in one or more of the following areas:

• Content Integrity & Scaled Enforcement – Detecting, reviewing, and acting on policy violations, harmful content, and emerging abuse patterns at scale.

• Emerging Risk Operations – Identifying, triaging, and mitigating new and complex safety, policy, or integrity challenges in a rapidly evolving AI landscape.

In this role, you will own high-sensitivity workflows, act as an incident manager for complex cases, and build scalable operational systems; including tooling, automation, and vendor processes that reinforce user safety and trust while meeting our legal, ethical, and product obligations.

We use a hybrid work model of 3 days in the San Francisco office per week and offer relocation assistance to new employees.

Please note: This role may involve exposure to sensitive content, including material that is sexual, violent, or otherwise disturbing.

In This Role, You Will:

• Handle and resolve high-priority cases in your area of specialization (scaled content enforcement, fraud/scams, privacy/regulatory, or emerging risks).

• Perform in-depth risk evaluations and investigations using internal tools, product signals, and third-party data.

• Act as incident manager for escalations requiring nuanced policy, legal, or regulatory interpretation.

• Partner with cross-functional teams to design and implement world-class operational workflows, decision trees, and automation strategies.

• Build feedback loops from casework to inform product, engineering, and policy improvements.

• Develop and maintain playbooks, SOPs, macros, and knowledge resources for internal teams and vendors.

• Lead or contribute to cross-functional projects, from zero-to-one process builds to global operational scale-ups.

• Monitor operational health through case quality audits, SLA adherence, escalation accuracy, and user satisfaction metrics.

• Train and support vendor teams, ensuring consistent quality and alignment with OpenAI’s trust and safety standards.

You Might Thrive in This Role If You:

• Have 5+ years of experience in one or more of: trust & safety, fraud prevention, scam investigation, privacy/legal operations, compliance, or other risk/integrity domains ideally in a global or high-growth tech environment.

• Leverage OpenAI technology to enhance workflows, improve decision-making, and scale operational impact.

• Bring deep domain expertise in your specialization area and familiarity with relevant legal, policy, and technical frameworks.

• Have a track record of scaling operations, building processes, and working cross-functionally to improve performance and safety outcomes.

• Possess exceptional analytical skills able to detect patterns, assess risk, and recommend policy or product changes based on evidence.

• Communicate with clarity, empathy, and precision especially in sensitive user-facing contexts.

• Thrive in ambiguous, high-autonomy environments and balance speed with diligence.

Are comfortable with frequent context switching, managing multiple projects, and prioritizing impact.

What We Offer

• Competitive salary and equity package

• Comprehensive benefits, including medical, dental, and vision insurance

• 401(k) retirement plan with employer match

• Paid parental leave and medical and caregiver leave

• Flexible PTO and paid company holidays

• Mental health and wellness support

• Annual learning and development stipend

• Daily meals in our offices and meal delivery credits

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends

How to Apply

If you are a motivated and experienced professional looking to join a dynamic team, please submit your application, including your resume and a cover letter, to [insert contact information]. We look forward to hearing from you!

XML job scraping automation by YubHub

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $226K – $378K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

The Hardware Strategic Sourcing & Partnerships organization is responsible for the global supply of compute infrastructure powering OpenAI’s model training and inference. We lead strategy, supplier engagements, commercial architecture, execution, and long-term enablement across advanced systems including custom silicon, accelerators, CPU platforms, networking, memory, power delivery, cooling, and full rack solutions.

We are a small, high-impact team working across engineering, operations, finance, legal, and executive leadership to scale OpenAI’s fleet worldwide.

About the Role

We are seeking a Sr. Strategic Sourcing Manager to own and lead sourcing strategy and global supplier partnerships for the High Speed Interconnects (e.g., power systems, high-speed interconnect, memory subsystems, networking modules, mechanical enclosures, thermal systems, etc.). You will be the single-threaded leader across supplier strategy, selection, negotiations, and commercial/operational execution.

You will be accountable for enabling massive growth, reducing long-term cost curves, securing supply resilience, and aligning supplier technology roadmaps with OpenAI’s future system architecture needs.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

Key Responsibilities

1. Own the category end-to-end: strategy, business case, supplier selection, executive alignment, and operational enablement

1. Lead complex commercial negotiations including MSAs, NRE, cost models, open-book pricing, ramp/capacity commitments, and risk-buy frameworks

1. Build and scale a reliable global supply base with redundancy and geopolitical compliance, including mapping and influencing sub-tier suppliers to ensure resilience across the extended supply chain.

1. Translate engineering requirements into actionable sourcing plans with tier-1 manufacturing partners

1. Drive cost benchmarking and teardown insights to shape long-term cost-down strategies

1. Maintain tight alignment with Operations, Capacity Planning, Finance, and Program Management to ensure supply readiness against growth milestones

1. Build executive-level relationships with suppliers to ensure priority allocation and roadmap synchronization

1. Define scalable sourcing processes and dashboards for risk, cost, and performance transparency

1. Mentor and uplift sourcing peers by role-modeling strong cross-functional leadership and commercial excellence

Qualifications

• 8+ years of strategic sourcing or supplier management experience in advanced electronics, cloud infrastructure, telecom, or semiconductor supply chains

• Demonstrated success owning a category and supplier portfolio at scale (supply assurance, commercial strategy, cost roadmap), including leading complex negotiations

• Strong understanding of electronic and module-level cost drivers (e.g., power, PCBAs, connectors, cooling, memory, networking)

• Proven ability to influence and partner with Engineering, Program Management, Legal, and Finance at senior levels

• Executive presence and ability to communicate clearly in high-stakes supplier and leadership forums

• Comfort with fast-paced ambiguity and decisive decision-making in compressed timelines

Preferred Qualifications

• Experience in hyperscale datacenter supply chain environments

• Familiarity with export controls and high-risk country strategies

• Technical background in \[mechanical/electrical engineering, high-speed IO, thermal systems, or rack-scale architecture\]

• Experience building sourcing playbooks, processes, and scalable operational mechanisms

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations

XML job scraping automation by YubHub

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Lead system signal integrity (SI) design for AI supercomputer product in the data center application.

• Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies

• Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity

• Perform simulation and modeling to identify and troubleshoot signal integrity issues

• Lead system interconnect design, bring up and qualification

• As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.

You might thrive in this role if you:

• Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications

• Have a strong bias toward action, and won’t take no for an answer.

• Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level

• Have experience with PCB, connector and cable design

• Have a strong intrinsic desire to learn and fill in missing skills; and an equally strong talent for sharing that information clearly and concisely with others.

• Are comfortable with ambiguity and rapidly changing conditions.

XML job scraping automation by YubHub

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Consumer Products

Compensation

• $293K – $325K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

About the Team

The Software team builds both external- and internal-facing products across io. Our internal tools power teams across hardware, operations, design, research, and software, enabling the organization to move quickly and operate at scale. We focus on usability, reliability, and security while supporting rapid iteration and experimentation.

About the Role

As a Full-Stack Engineer, you will design and build end-to-end web systems that serve both customers and internal teams. You’ll own the design and implementation of full-stack solutions—from early prototypes to production-ready systems—making thoughtful trade-offs around usability, security, and long-term maintainability.

We’re looking for pragmatic builders with strong product instincts who move fast without compromising quality or security. You’ll work closely with designers, engineers, and cross-functional partners to identify pain points, prototype solutions, and take them from zero-to-one into reliable systems.

This role is based in San Francisco, CA. We use a hybrid work model of four days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Design, build, and maintain web applications for external customers.
• Design, build, and maintain internal tools used across hardware, research, design, operations, and software teams.
• Rapidly prototype and iterate on new tools in close collaboration with stakeholders.
• Architect and deliver full-stack solutions with a strong emphasis on usability and security.
• Evaluate third-party and open-source solutions and make sound build vs. buy decisions.
• Establish best practices for internal tooling, including code quality, reliability, and security.

You might thrive in this role if you:

• Have 7+ years of professional software engineering experience, with a focus on full-stack web development.
• Are proficient in rapidly building user-facing products and internal applications.
• Have experience working from zero-to-one on early-stage products and iterating quickly based on feedback.
• Bring a strong understanding of security principles and best practices for protecting sensitive data.
• Are familiar with a broad range of modern front-end and back-end frameworks and tools.

_(Nice to have)_ Have experience building internal tools for multidisciplinary teams (hardware, research, operations).

_(Nice to have)_ Have a track record of effectively selecting and integrating third-party or open-source solutions.

_(Nice to have)_ Have strong design instincts and experience collaborating closely with designers.

_(Nice to have)_ Are familiar with infrastructure and deployment for internal systems (e.g., containerization, CI/CD).

_(Nice to have)_ Have experience balancing speed with security and reliability in production environments.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

XML job scraping automation by YubHub

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Security

Compensation

• $230K – $325K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Privacy Engineering team sits at the intersection of Security, Privacy, Legal, and Core Infrastructure. Our mission is to build data infrastructure and systems to support our privacy, legal, and security teams—securely, quickly, and at scale. Our guiding principles include: defensibility by default, enabling researchers, preparing for future transformative technologies, and building a robust security culture.

About the Role

We’re looking for a Software Engineer who can design and operate technical systems that support legal compliance workflows, including secure data processing and document review. You’ll partner daily with Legal, Security, IT, and partner engineering teams to turn legal processes into concrete technical workflows. This role is ideal for an engineer who loves large-scale data problems and understands the rigor required when the results may be scrutinized.

This position is located in San Francisco. Relocation assistance is available.

In this role, you will:

• Design and operate data storage pipelines that can operate at scale.

• Build search & discovery services (e.g., Spark/Databricks, index layers, metadata catalogs) based on the needs of partner teams.

• Automate secure data transfers—encrypting, checksumming, and auditing exports to reviewers.

• Stand up locked-down compute environments that balance usability with security controls.

• Instrument monitoring and KPIs that maintain accountability of data holds and productions.

• Collaborate cross-functionally to codify SOPs, threat models, and chain-of-custody documentation that withstand scrutiny.

You might thrive in this role if you:

• Have hands-on experience building or operating large-scale data-lake or backup systems (Azure, AWS, GCP).

• Know your way around Terraform or Pulumi, CI/CD, and can turn ad-hoc legal requests into repeatable pipelines.

• Comfortable working with discovery workflows (legal holds, enterprise document collections, secure review) or eager to build expertise quickly.

• Able to communicate technical concepts — from storage governance to block-ID APIs — clearly to teams such as Legal, Engineering, and others.

• Have shipped secure solutions that balance speed, cost, and evidentiary defensibility—and can articulate the trade-offs.

• Communicate crisply, document rigorously, and enjoy working across disciplines under tight deadlines.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

XML job scraping automation by YubHub

Location

Remote - US; New York City; San Francisco; Seattle

Employment Type

Full time

Location Type

Remote

Department

Security

Compensation

• SF, Seattle or NYC $230K – $385K • Offers Equity
• Zone A $207K – $346.5K • Offers Equity
• Zone B $184K – $308K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
• 401(k) retirement plan with employer match
• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
• Mental health and wellness support
• Employer-paid basic life and disability coverage
• Annual learning and development stipend to fuel your professional growth
• Daily meals in our offices, and meal delivery credits as eligible
• Relocation support for eligible employees
• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

Security is at the foundation of OpenAI’s mission to ensure that artificial general intelligence benefits all of humanity.

The Security team protects OpenAI’s technology, people, and products. We are technical in what we build but operational in how we execute, and we support every product and research effort at OpenAI. Our tenets include prioritizing for impact, enabling researchers and developers, preparing for future transformative technologies, and fostering a strong, collaborative security culture.

About the Role

OpenAI is seeking a Security Software Engineer to join the Infrastructure Security (InfraSec) team.

InfraSec safeguards the core of OpenAI’s research and production environments—GPU supercomputing clusters, multi-cloud infrastructure, datacenters, networking, storage, and the critical services that power our frontier AI models. Our charter spans everything from bare-metal hardware and firmware to Kubernetes clusters, service meshes, and the data pathways that carry highly sensitive model weights and user data.

As a Security Software Engineer, you will design and build critical foundational services, such as authentication systems, egress/ingress proxies, access brokers, and key management platforms, that demand high standards of reliability, scalability, and software craftsmanship. These systems form the security backbone of OpenAI’s supercomputing environment and must remain robust under intense scale and adversarial pressure.

In this role, you will:

• Architect and implement production-grade security services (e.g., auth services, access brokers, secure proxies, key-management infrastructure) that provide strong guarantees across hardware, operating systems, Kubernetes, networks, and CI/CD.
• Partner with infrastructure and research engineers to embed security into high-performance compute clusters, enabling rapid model training and deployment without compromising protection.
• Develop automation and detection tooling to continuously identify and mitigate risks in large-scale cloud and on-prem environments.
• Drive high-impact initiatives such as line-speed encryption, machine identity, and network isolation, continuously raising the security bar for emerging AI workloads.
• Lead or participate in design reviews and threat models to ensure new systems launch with strong security foundations and operational excellence.

You will thrive in this role if you have:

• Strong software engineering skills in languages such as Python, Go, Rust, or C/C++, with a track record of shipping and operating high-reliability distributed services.
• Experience building or operating critical security infrastructure (e.g., auth services, service-to-service proxies, certificate or key-management systems).
• Deep understanding of security principles, best practices, and common vulnerabilities.
• Expertise in securing large-scale cloud platforms (e.g., Azure, AWS, GCP), including multi-cloud networks and cloud-agnostic system design.
• Familiarity with container and orchestration security (Kubernetes, service meshes) and modern authentication/authorization standards (OIDC, mTLS, SPIFFE/SPIRE).
• A proactive mindset, with the ability to identify and address security gaps or inefficiencies through automation and tooling.
• A track record of delivering scalable solutions and driving impactful changes across infrastructure in real-world projects.
• Strong analytical and problem-solving skills, with an ability to think critically and objectively assess security risks.
• Excellent communication skills, with the ability to convey complex security concepts to technical and non-technical stakeholders.
• Excitement about collaborating

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San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $226K – $378K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

The Hardware Strategic Sourcing & Partnerships organization is responsible for the global supply of compute infrastructure powering OpenAI’s model training and inference. We lead strategy, supplier engagements, commercial architecture, execution, and long-term enablement across advanced systems including custom silicon, accelerators, CPU platforms, networking, memory, power delivery, cooling, and full rack solutions.

We are a small, high-impact team working across engineering, operations, finance, legal, and executive leadership to scale OpenAI’s fleet worldwide.

About the Role

We are seeking a Sr. Strategic Sourcing Manager to own and lead sourcing strategy and global supplier partnerships for the Memory Storage & CPUs category (e.g., power systems, high-speed interconnect, memory subsystems, networking modules, mechanical enclosures, thermal systems, etc.). You will be the single-threaded leader across supplier strategy, selection, negotiations, and commercial/operational execution.

You will be accountable for enabling massive growth, reducing long-term cost curves, securing supply resilience, and aligning supplier technology roadmaps with OpenAI’s future system architecture needs.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

Key Responsibilities

1. Own the category end-to-end: strategy, business case, supplier selection, executive alignment, and operational enablement

1. Lead complex commercial negotiations including MSAs, NRE, cost models, open-book pricing, ramp/capacity commitments, and risk-buy frameworks

1. Build and scale a reliable global supply base with redundancy and geopolitical compliance, including mapping and influencing sub-tier suppliers to ensure resilience across the extended supply chain.

1. Translate engineering requirements into actionable sourcing plans with tier-1 manufacturing partners

1. Drive cost benchmarking and teardown insights to shape long-term cost-down strategies

1. Maintain tight alignment with Operations, Capacity Planning, Finance, and Program Management to ensure supply readiness against growth milestones

1. Build executive-level relationships with suppliers to ensure priority allocation and roadmap synchronization

1. Define scalable sourcing processes and dashboards for risk, cost, and performance transparency

1. Mentor and uplift sourcing peers by role-modeling strong cross-functional leadership and commercial excellence

Qualifications

• 8+ years of strategic sourcing or supplier management experience in advanced electronics, cloud infrastructure, telecom, or semiconductor supply chains

• Demonstrated success owning a category and supplier portfolio at scale (supply assurance, commercial strategy, cost roadmap), including leading complex negotiations

• Strong understanding of electronic and module-level cost drivers (e.g., power, PCBAs, connectors, cooling, memory, networking)

• Proven ability to influence and partner with Engineering, Program Management, Legal, and Finance at senior levels

• Executive presence and ability to communicate clearly in high-stakes supplier and leadership forums

• Comfort with fast-paced ambiguity and decisive decision-making in compressed timelines

Preferred Qualifications

• Experience in hyperscale datacenter supply chain environments

• Familiarity with export controls and high-risk country strategies

• Technical background in \[mechanical/electrical engineering, high-speed IO, thermal systems, or rack-scale architecture\]

• Experience building sourcing playbooks, processes, and scalable operational mechanisms

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

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About the Team

OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

OpenAI's Hardware organization builds supercompute platforms from silicon and boards to full rack-scale systems to power advanced AI workloads. This role owns end-to-end quality for high-speed interconnect hardware across the product lifecycle: early design influence, supplier/contract manufacturer readiness, qualification, ramp, and fleet quality in lab and data center environments.

You will be the quality lead for advanced interconnect components and assemblies, including high-speed copper cables, cable cartridges, patch panels, backplane/cable-backplane solutions, high-speed connectors, and related electro-mechanical interfaces. You will partner closely with electrical, mechanical, SI/PI, systems, reliability, operations, and external vendors to prevent escapes and drive rapid, data-driven containment and corrective action.

Responsibilities

• Own quality for advanced interconnect components and assemblies: high-speed connectors, high-speed copper cables, cable cartridges (e.g., ultra-pass / cable cassette style assemblies), patch panels & optics, and backplane/cable-backplane interconnect solutions.

• Drive quality-by-design: participate in design reviews, DFM/DFx, tolerance stacks, material and plating selections, connector mating strategy, strain relief, and assembly methods to reduce variation and field failures.

• Define and track quality and reliability metrics (DPPM, yield, escapes, RMA/FRACAS trends, Cpk/Ppk where applicable) for interconnects across NPI and mass production.

• Build and execute qualification strategies for cables/connectors/patch panels (mechanical, environmental, electrical, and reliability), including test coverage, sample plans, clear pass/fail criteria, defining installation criteria and processes, optics termination quality management and setting fiber standards criteria.

• Partner with engineering and operations to drive smooth ramp: risk assessments, pilot build learnings, change control, and readiness reviews (EVT/DVT/PVT/MP or equivalent phases).

• Own supplier and CM performance management: scorecards, audits (process and quality system), and follow-up to close findings with verified effectiveness

• Work with suppliers to improve manufacturing throughput, stability, and yields for cable and connector assembly processes (e.g., wire prep, welding/crimping, overmolding/injection molding, plating, and assembly fixturing).

• Lead rapid containment and root-cause investigations for failures found during bring-up, system integration tests, reliability testing, and fleet deployments.

• Own the end-to-end corrective action process (8D, 5-Whys, Ishikawa, DOE as needed): define problem statements, isolate variables, validate root cause, implement fixes, and verify effectiveness.

• Partner with SI/PI and test teams to correlate electrical performance issues (e.g., link margin, BER, eye closure, impedance discontinuities, PAM4, TDR and VNA) with manufacturing and mechanical drivers (connector wear, plating, contamination, misalignment, cable routing, assembly variation).

• Support integration and deployment of OpenAI supercompute racks in lab and data center environments; identify quality risks tied to shipping, handling, installation, and service operations.

Requirements

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.

• 5+ years of experience in quality engineering, with a focus on high-speed interconnects and electro-mechanical assemblies.

• Strong understanding of quality principles, including Six Sigma, Lean, and Design for Manufacturability (DFM).

• Experience with quality management systems, such as ISO 9001, and regulatory requirements, such as IEC 62368.

• Strong analytical and problem-solving skills, with the ability to analyze complex data and identify root causes.

• Excellent communication and collaboration skills, with the ability to work effectively with cross-functional teams.

• Experience with test and measurement equipment, such as oscilloscopes, signal generators, and network analyzers.

• Familiarity with simulation tools, such as ANSYS and COMSOL.

• Experience with data analysis and visualization tools, such as Excel, Python, and Tableau.

Preferred Qualifications

• Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.

• 8+ years of experience in quality engineering, with a focus on high-speed interconnects and electro-mechanical assemblies.

• Experience with advanced quality tools, such as Failure Mode and Effects Analysis (FMEA) and Design of Experiments (DOE).

• Familiarity with artificial intelligence and machine learning concepts and applications.

• Experience with cloud-based quality management systems, such as Salesforce and ServiceNow.

Salary and Benefits

• Salary: $123K – $285K

• Offers Equity

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

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Collaborate to define product goals Conceive, design, evaluate, and produce novel gaming hardware Work closely with contract manufacturers to prototype and produce hardware at scales from tens to millions of units

Electrical engineers at Valve have significant industry experience. We usually don’t hire recent graduates.

Members of our team typically have the following skills:

Proven start-to-finish design skills with industry-standard CAD/EDA tools (Altium Designer experience strongly preferred), including schematic entry, PCB layout, component definition, and CAD library management Hands-on electronics prototyping experience, including soldering and rework of fine-pitch SMT components Strong lab skills, including the use of common test and measurement equipment (oscilloscopes, logic analyzers, etc.) to debug and characterize complex electronic circuits Experience with embedded systems design and common digital communication interfaces (USB, SPI, I2C) Experience working directly on-site with manufacturing partners A proven track record of designing and shipping high-volume consumer electronics products Experience in design for manufacture and design for test (DFM/DFT) of electronic devices Ability to think and work across a variety of subject areas

Bachelor's degree (or equivalent work experience) in electrical engineering or a related field

Our team includes individuals with expertise in the following areas:

Analog circuit design and simulation (e.g. SPICE) Low-power design, including battery management and charging circuits for portable devices RF/wireless circuit design, including design of antennas and for EMC Firmware development for 8, 16, 32-bit microcontrollers (e.g. ARM) High speed/HDI board design Digital Signal Processing (DSP) High speed video interfaces (HDMI, Display Port, LVDS, MIPI) Regulatory compliance testing (e.g. FCC/CE/UL) C/C++ software development Test automation FPGA/ASIC design

What We Offer

An organization where 100% of time is dedicated as groups see fit The opportunity to collaborate with experts across a range of disciplines A work environment and flexible schedule in support of families and domestic partnerships A culture eager to become stronger through diversity of all forms Exceptional health insurance coverage Unrivaled employer match for our 401(k) retirement plan Generous vacation and family leave On-site amenities in support of health and efficiency Fertility and adoption assistance Reimbursement for child care during interviews

Valve strives to improve the diversity of our teams to better serve our diverse global audience. We welcome and encourage individuals from all backgrounds to apply.

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What you'll do

• Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
• Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

What you need

• Bachelor's and/or masters with a minimum 10+yrs of Industry experience or equivalent
• At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)
• Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure
• Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB

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What you'll do

• Develop and implement high-performance PCIe-based designs on FPGA platforms, ensuring optimal functionality and efficiency.
• Collaborate closely with cross-functional teams to gather requirements, evaluate design tradeoffs, and deliver robust FPGA solutions that satisfy project goals.

What you need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in FPGA design and development.
• Proficiency in HDL languages such as Verilog.
• Strong expertise with industry-standard FPGA development tools like Vivado.
• In-depth understanding of digital design principles, including clock domains and timing analysis.
• Experience with high-speed interfaces (PCIe or Ethernet).
• Excellent analytical, debug, and problem-solving skills.
• Ability to collaborate effectively in a multi-disciplinary, team-based environment.
• Strong verbal and written communication skills.

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Microsoft AI are looking for a talented Member of Technical Staff, Hardware Health, to ensure these systems deliver sustained reliability, performance, and availability across exascale-class deployments.

About the Role

We work closely with research, hardware, datacenter, and platform engineering teams to develop predictive health models, failure detection frameworks, and autonomous remediation systems that keep our AI clusters operating at frontier scale. Our team is responsible for Copilot, Bing, Edge, and generative AI research.

Accountabilities

• Design and develop next-generation hardware health monitoring and diagnostic frameworks for large GPU clusters (NVL16/NVL72/GB200+ scale).
• Build predictive analytics pipelines leveraging telemetry, power, and thermal data to anticipate hardware degradation and systemic issues.
• Collaborate with silicon, firmware, and datacenter engineers to identify root causes and remediate large-scale hardware anomalies.
• Define system health KPIs (e.g., NIS/RIS, MTBF, failure domain analysis) and integrate them into real-time observability platforms.
• Lead incident triage for high-impact GPU, network, and cooling issues across distributed clusters.
• Drive automation in health management to reduce manual intervention to the top 5% of anomalies.
• Partner with cross-functional teams to influence hardware design for reliability, thermal efficiency, and serviceability.

The Candidate we're looking for

Experience:

• Bachelor's Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Technical skills:

• Experience working with large-scale HPC or GPU systems (NVIDIA H100/GB200 or equivalent).
• Deep understanding of GPU architecture, high-speed interconnects (NVLink, InfiniBand, RoCE), and large datacenter topologies.
• Proficiency in hardware telemetry, diagnostics, or failure analysis tools.

Personal attributes:

• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Benefits

• Competitive salary.
• Comprehensive benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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Microsoft AI are looking for a talented Member of Technical Staff, Hardware Health, to ensure these systems deliver sustained reliability, performance, and availability across exascale-class deployments.

About the Role

We work closely with research, hardware, datacenter, and platform engineering teams to develop predictive health models, failure detection frameworks, and autonomous remediation systems that keep our AI clusters operating at frontier scale. Our team is responsible for Copilot, Bing, Edge, and generative AI research.

Accountabilities

• Design and develop next-generation hardware health monitoring and diagnostic frameworks for large GPU clusters (NVL16/NVL72/GB200+ scale).
• Build predictive analytics pipelines leveraging telemetry, power, and thermal data to anticipate hardware degradation and systemic issues.
• Collaborate with silicon, firmware, and datacenter engineers to identify root causes and remediate large-scale hardware anomalies.
• Define system health KPIs (e.g., NIS/RIS, MTBF, failure domain analysis) and integrate them into real-time observability platforms.
• Lead incident triage for high-impact GPU, network, and cooling issues across distributed clusters.
• Drive automation in health management to reduce manual intervention to the top 5% of anomalies.
• Partner with cross-functional teams to influence hardware design for reliability, thermal efficiency, and serviceability.

The Candidate we're looking for

Experience:

• Bachelor's Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Technical skills:

• Experience working with large-scale HPC or GPU systems (NVIDIA H100/GB200 or equivalent).
• Deep understanding of GPU architecture, high-speed interconnects (NVLink, InfiniBand, RoCE), and large datacenter topologies.
• Proficiency in hardware telemetry, diagnostics, or failure analysis tools.

Personal attributes:

• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Benefits

• Competitive salary.
• Comprehensive benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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What you'll do

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.

What you need

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.

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What you'll do

• Reviewing and interpreting SerDes standards to define, develop, and refine innovative transceiver architectures and detailed analog sub-block specifications for high-speed Multi-Gbps NRZ & PAM4 SerDes IP.
• Investigating and architecting advanced circuit solutions that address performance bottlenecks, driving significant improvements in power, area, and speed while ensuring robust and reliable silicon performance.

What you need

• Strong understanding of analog circuit design and verification techniques.
• Experience with high-speed SerDes IP development and advanced process nodes such as FinFET and gate-all-around technologies.

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What you'll do

• Guiding customers through the integration of Synopsys UCIe IP into their ASIC SoC and systems, addressing both technical and process challenges.
• Providing expert advice on IIP configuration, simulation, synthesis, floorplanning, static timing analysis (STA), and design-for-test (DFT) strategies.

What you need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Minimum 10 years of experience in ASIC design, verification, or applications engineering within advanced technology nodes (10nm/7nm/5nm/3nm).
• Hands-on expertise in mixed-signal and high-speed interface design and integration, ASIC front-end and/or back-end implementation, including simulation, synthesis, floorplanning, and DFT.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Leading silicon validation of IP functionality and performance, ensuring alignment with architectural intent.
• Supporting hardware bring-up and firmware integration for early product-version characterization.

What you need

• BSc or MSc in Electrical or Computer Engineering.
• 10+ years of experience in silicon validation, high-speed interfaces, and system-level performance analysis.

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What you'll do

• Driving innovation in high-speed interface DDR IP products, facilitating the development of cutting-edge solutions and SI/PI methodologies.
• Enhancing customer satisfaction by providing expert SI/PI support and guidance for interface IP integration at both pre- and post-sales stages.

What you need

• Proven expertise in signal and power integrity for high-speed interfaces, including mixed-signal design and off-chip system signaling.

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What you'll do

• Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
• Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.

What you need

• 5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.
• Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.
• Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).
• Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.

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What you'll do

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in SystemVerilog and Verilog for RTL development.

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What you'll do

• Designing and developing physical layouts for high-speed analog and mixed-signal IP blocks, including SerDes, RX, TX, PLL, and custom logic paths.
• Collaborating with a team of experienced layout engineers to deliver optimized, reliable, and manufacturable designs.

What you need

• BTech/MTech in Electronics or Electrical Engineering.
• 6+ years of hands-on experience in analog/mixed-signal IP layout and verification for high-speed analog circuits.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Providing expert assistance to customers for system-level performance issues and troubleshooting.
• Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development.
• Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Reviewing SerDes standards and architecture documents to develop comprehensive analog sub-block specifications.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Proposing and executing design and verification strategies that leverage advanced simulator features for highest-quality design outcomes.

What you need

• BS/BTech degree and 5+ years of experience in IC design, or MS/MTech with 3+ years of experience or PhD degree in a related field.
• In-depth familiarity with transistor-level circuit design and solid CMOS fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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What you'll do

You will design, develop, troubleshoot, and debug software programs for PCIe IP evaluation and test chip platforms.

• Designing, developing, troubleshooting, and debugging software programs for PCIe IP evaluation and test chip platforms.
• Developing scalable software tools, APIs, and architectures focused on evaluation software for Synopsys PCIe evaluation boards.

What you need

• Comprehensive expertise in PCIe protocol, SERDES, and hands-on experience with evaluation boards, silicon validation, or test chips.
• Advanced proficiency in Python, C++, or similar programming languages for embedded, driver, or system-level development.

Why this matters

Accelerate the evaluation and adoption of Synopsys's latest PCIe IP and test chips by delivering robust, user-friendly software tools. Enable seamless hardware bring-up and protocol validation, empowering both customers and internal teams to assess performance and compliance efficiently.

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What you'll do

• Build and iterate on onboarding, sign-up, paywall, checkout, and retention flows to improve conversion and LTV.
• Run rapid A/B tests and funnel experiments (e.g. UI variants, pricing tests, onboarding flows) and use data to decide what to ship and scale.

What you need

• 5+ years industry experience
• Strong Swift fundamentals and a proven track record of working with a modern iOS stack built with Swift, SwiftUI (iOS16+) and UIKit
• Experience with experimentation platforms (e.g. Statsig, LaunchDarkly, Firebase A/B Testing) and analytics tools (e.g. Amplitude, Mixpanel, Snowplow).

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What you'll do

• Help shape the vegetation vision for the project, work with Art Directors and Lead Artists to bring our worlds to life.
• Set the quality bar by creating benchmark vegetation assets - from hero trees to ground cover.
• Collaborate with Environment Artists and Level Designers to ensure vegetation supports gameplay, composition, and biome storytelling.
• Help evolve vegetation pipelines, workflows, and best practices.
• Work with Technical Art to balance beauty and performance across platforms.
• Support planning and prioritisation conversations to ensure vegetation is delivered at the right quality and scale.
• Provide feedback, mentorship, and guidance to teammates and external partners.
• Stay curious - exploring new techniques, tools, and ideas that push the vegetation craft forward.

What you need

• A senior-level vegetation artist with a portfolio demonstrating exceptional visual quality and technical execution in real-time environments.
• 7+ years of experience creating high-quality environment or vegetation art for shipped AAA titles.
• Deep knowledge of vegetation workflows - modelling, texturing, shaders, wind, LODs — and tools such as Maya, SpeedTree, Houdini, Substance, and photogrammetry pipelines.
• A solid understanding of optimisation and large-scale world building.
• Someone who enjoys collaborating, sharing knowledge, and raising the bar for the whole team.

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