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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4ed1875c-bd2"},"title":"Physical Design Lead (With STA & Timing Constraints Expertise)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</li>\n<li>Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.</li>\n<li>Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.</li>\n<li>Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power &amp; IR drop signoff to debug and resolve critical implementation bottlenecks.</li>\n<li>Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.</li>\n<li>Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock &amp; reset architecture improvements for enabling high speed timing closure, PPA improvements.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. 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