What Makes a Honda, is Who makes a Honda
\nHonda has a clear vision for the future, and it’s a joyful one. We are looking for individuals with the skills, courage, persistence, and dreams that will help us reach our future-focused goals. At our core is innovation. Honda is constantly innovating and developing solutions to drive our business with record success. We strive to be a company that serves as a source of “power” that supports people around the world who are trying to do things based on their own initiative and that helps people expand their own potential. To this end, Honda strives to realize “the joy and freedom of mobility” by developing new technologies and an innovative approach to achieve a “zero environmental footprint.”
\nWe are looking for qualified individuals with diverse backgrounds, experiences, continuous improvement values, and a strong work ethic to join our team.
\nIf your goals and values align with Honda’s, we want you to join our team to Bring the Future!
\nJob Purpose
\nThe Design Research Senior Engineer in the CoE Division conducts sensing for NA market and consumer trends, extract emerging technologies, formulate hypothesis and propose research initiatives to provide value toward NA Honda’s business direction.
\nKey Accountabilities
\nConduct sensing for NA market and consumer trends, extract emerging technologies, and propose research initiatives.
\nContinuously summarize and correlate sensing results and conclusions with internal stakeholders.
\nPropose and carry out advanced research of emerging technologies utilizing Agile methodologies to prove hypothesis and define value with speed.
\nIndependently manage technical project resources while maintaining leading knowledge of state-of-the-art principles and theories.
\nPropose new technology research themes for implementation into the Honda technical strategy through existing meeting structure and cadence.
\nDevelops and maintains strong relationships with internal and external research partners, industry experts, consortium members, university staff, and policy leaders to gather expertise and grow capability.
\nWithin defined technical pillar, identify root cause of highly technical and multidisciplinary problems and develop plans, designs, test systems, materials, techniques and processes to achieve objectives.
\nGain knowledge and expertise in emerging technologies, document findings, and inform others to grow the overall technical capability in North America.
\nQualifications, Experience, and Skills
\nMinimum Educational Qualifications:
\nBachelor’s of Science in Engineering field or equivalent relevant experience in science/engineering research capacity.
\nMinimum Experience:
\n5 or more years with focus on digital chip architectures, benchmarking, open-source IP / ISA (RISC), ARM, familiarity with CPU / GPU / NPU, FPGAs, SoCs (System-on-Chip) and heterogenous integration.
\nFamiliarity with Assembly language.
\nOther highly desirables: Prior experience with industry standard EDA tools (e.g. - Synopsys / Cadence &c) for IC chip design. Exp in HDLs - e.g. - Verilog / VHDL
\nOther Job-Specific Skills:
\nPassion for research, solving hard problems, and challenging the status quo.
\nAbility to learn new topics of apply principles to design and manufacturing challenges.
\nWorking knowledge of Agile processes and methodologies
\nDesign experiments to test hypothesis and prove them out.
\nUtilize agile process and methodologies to conduct sensing and research initiatives
\nConfidently make autonomous decisions bounded by the research mission and understanding of the company business model.
\nAbility to efficiently manage resources to achieve project initiatives and schedules
\nClearly communicate new research and technology concepts and ideas to technical team members and management.
\nScientifically analyze data provided from tests and experiments to gather knowledge and understanding of the subject of research.
\nOversee overall research project schedule, budget, and direction.
\nWorkstyle
\nThis position will require the employee to work at our ADC, Raymond, OH office at least 4 days per workweek. One remote workday a week may be possible with prior departmental approval.
\nWhat differentiates Honda and make us an employer of choice?
\nTotal Rewards:
\nCompetitive Base Salary (pay will be based on several variables that include, but not limited to geographic location, work experience, etc.)
\nPaid Overtime
\nRegional Bonus (when applicable)
\nIndustry-leading Benefit Plans (Medical, Dental, Vision, Rx)
\nPaid time off, including vacation, holidays, shutdown
\nCompany Paid Short-Term and Long-Term Disability
\n401(K) Plan with company match + additional contribution
\nRelocation assistance (if eligible)
\nCareer Growth:
\nAdvancement Opportunities
\nCareer Mobility
\nEducation Reimbursement for Continued Learning
\nTraining and Development programs
\nAdditional Offerings:
\nTuition Assistance & Student Loan Repayment
\nLifestyle Account
\nChildcare Reimbursement Account
\nElder Care Support
\nWellbeing Program
\nCommunity Service and Engagement Programs
\nProduct Programs
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_24665b43-498","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Honda","sameAs":"https://careers.honda.com","logo":"https://logos.yubhub.co/careers.honda.com.png"},"x-apply-url":"https://careers.honda.com/us/en/job/10679/Senior-ASIC-Design-Research-Engineer","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$90,200.00 - $112,700.00","x-skills-required":["digital chip architectures","benchmarking","open-source IP / ISA (RISC)","ARM","CPU / GPU / NPU","FPGAs","SoCs (System-on-Chip)","heterogenous integration","Assembly language","Synopsys / Cadence","Verilog / VHDL"],"x-skills-preferred":[],"datePosted":"2026-04-22T17:20:50.174Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Raymond"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Automotive","skills":"digital chip architectures, benchmarking, open-source IP / ISA (RISC), ARM, CPU / GPU / NPU, FPGAs, SoCs (System-on-Chip), heterogenous integration, Assembly language, Synopsys / Cadence, Verilog / VHDL","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":90200,"maxValue":112700,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8142c2c7-bfb"},"title":"Principal STA Engineer","description":"Overview
\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nJob Description
\nAs a Principal STA Engineer, you will be responsible for owning full-chip and block-level STA sign-off across all PVT corners and operational modes. You will drive timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.
\nResponsibilities
\nThe Impact You Will Have
\nWhat You’ll Need
\nWho You Are
\nThe Team You’ll Be A Part Of
\nYou will join a dynamic, highly skilled SOC engineering team dedicated to delivering world-class silicon solutions at the forefront of semiconductor technology.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_8142c2c7-bfb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/austin/principal-sta-engineer/44408/93189758160","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$170,000-$255,000","x-skills-required":["STA","timing sign-off","SoCs","Primetime","Tempus","Tcl","Python","Perl","EM/IR","reliability impacts on timing","full-chip integration","hierarchical STA methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:05.689Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"STA, timing sign-off, SoCs, Primetime, Tempus, Tcl, Python, Perl, EM/IR, reliability impacts on timing, full-chip integration, hierarchical STA methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":170000,"maxValue":255000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_00fdc4b4-f89"},"title":"Senior System Level Test Engineer","description":"We are now looking for a Senior System Level Test Engineer to implement the world's leading SoCs, GPUs, and ASICs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
\nWhat you'll be doing:
\nWhat we need to see:
\nWidely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
\nYou will also be eligible for equity and benefits.
\nApplications for this job will be accepted at least until March 13, 2026.
\nThis posting is for an existing vacancy.
\nNVIDIA uses AI tools in its recruiting processes.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_00fdc4b4-f89","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-System-Level-Test-Engineer_JR2013156","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering","12+ years of experience in Systems level test, systems validation, and/or bench testing","Experience in new silicon bring up at the system level","Experience in driving SLT testing and deployment for HVM","Experience with testing and characterization of high power SOCs and High Speed I/Os"],"x-skills-preferred":["C#","C/C++","PERL","Python",".NET framework"],"datePosted":"2026-03-09T20:45:48.152Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering, 12+ years of experience in Systems level test, systems validation, and/or bench testing, Experience in new silicon bring up at the system level, Experience in driving SLT testing and deployment for HVM, Experience with testing and characterization of high power SOCs and High Speed I/Os, C#, C/C++, PERL, Python, .NET framework"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f500c2e7-79c"},"title":"Senior Post Silicon Validation Engineer","description":"We are seeking a Senior Post Silicon Validation Engineer to join our team. As a Senior Post Silicon Validation Engineer, you will be responsible for leading the design, automation, and validation of System Level Tests (SLT) for High Volume Manufacturing (HVM) for complex, high power, high speed System-on-Chip (SoC) designs.
\nYour primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.
\nIn addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.
\nYou will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.
\nFinally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.
\nTo be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.
\nAdditionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.
\nIf you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_f500c2e7-79c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Post-Silicon-Validation-Engineer_JR2013152","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering","12+ years of relevant industry experience","Experience in post-silicon electrical validation of high power, high speed, complex SoCs","Proven driver and leader of a full system validation from end to end (silicon out to production start) with attention to detail and a passion for root causing issues","Silicon validation experience, preferably in the area of SerDes, LSIO, Logic, and Memory","Experience in system marginality validation","Good understanding of lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.","Strong understanding of Firmware and able to debug and create new test cases","Software proficiency in Python for test scripting, data handling, and reporting","Knowledge of board and package design, signal integrity, data handling, and reporting"],"x-skills-preferred":["Python","Firmware","Lab equipment","Measurement techniques","Signal integrity","Data handling","Reporting"],"datePosted":"2026-03-09T20:43:50.606Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering, 12+ years of relevant industry experience, Experience in post-silicon electrical validation of high power, high speed, complex SoCs, Proven driver and leader of a full system validation from end to end (silicon out to production start) with attention to detail and a passion for root causing issues, Silicon validation experience, preferably in the area of SerDes, LSIO, Logic, and Memory, Experience in system marginality validation, Good understanding of lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc., Strong understanding of Firmware and able to debug and create new test cases, Software proficiency in Python for test scripting, data handling, and reporting, Knowledge of board and package design, signal integrity, data handling, and reporting, Python, Firmware, Lab equipment, Measurement techniques, Signal integrity, Data handling, Reporting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fd5bf729-eff"},"title":"Embedded Software Engineer (m/f/d)","description":"Are you passionate about engineering and its application to acoustics and audio reproduction? We're looking for an Embedded Software Engineer to join our innovative team for creating audio products.
\nAt ADAM Audio, our commitment to excellence and cutting-edge engineering drives our mission to deliver ground-breaking solutions to our customers. As an Embedded Software Engineer, you will be collaborating closely with cross-functional and multi-cultural teams across the company and external partners, to define, prototype and develop products from early sketches on to market introduction and maintenance.
\nOn a day-to-day basis, you'll be responsible for providing the firmware code for our hardware products, including evaluation of new technologies, debugging prototype hardware and ensuring your code is suitable for mass production and complies with latest market regulations (CE, FCC, CRA etc.). You'll have the opportunity to shape the direction of our embedded projects and you'll be involved in the project's lifecycles.
\nYou'll be refining product specifications, producing innovative designs and solutions and engaging with a multi-discipline team. You'll be planning your activities, estimating your work and collaborating to meet deadlines and product requirements as well as working hands-on at functional prototypes and evaluation boards to debug and test electronic hardware designs with your code on it.
\nIndividual and team development is important, and we'll support you as you look for ways to grow and improve your personal knowledge and skills. We'll also be looking for you to own and help improve our approach to embedded software engineering, including best practices, processes, and tools. There will also be opportunities to share knowledge and practices with all companies across the Focusrite group.
\nResponsibilities
\nRequirements
\nWhat we offer
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_fd5bf729-eff","directApply":true,"hiringOrganization":{"@type":"Organization","name":"ADAM Audio GmbH","sameAs":"https://apply.workable.com","logo":"https://logos.yubhub.co/j.com.png"},"x-apply-url":"https://apply.workable.com/j/1AC1114357","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"Depending on experience","x-skills-required":["micro-controllers","audio DSP","low-level programming","ARM-based-microcontrollers","RTOS","C","C++","Zephyr","test equipment","oscilloscopes","logic analysers","bus analysers","audio analysers","compliance regulations","standards","USB-connectivity","wireless-connectivity","Ethernet-connectivity","battery powered devices","Bluetooth","RF SoCs","Qualcomm","Airoha","Bestec","networking protocols","Ethernet","WiFi","BLE","problem-solving","debugging","lab work","test equipment","soldering"],"x-skills-preferred":["German language skills"],"datePosted":"2026-03-09T16:13:41.089Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Berlin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"micro-controllers, audio DSP, low-level programming, ARM-based-microcontrollers, RTOS, C, C++, Zephyr, test equipment, oscilloscopes, logic analysers, bus analysers, audio analysers, compliance regulations, standards, USB-connectivity, wireless-connectivity, Ethernet-connectivity, battery powered devices, Bluetooth, RF SoCs, Qualcomm, Airoha, Bestec, networking protocols, Ethernet, WiFi, BLE, problem-solving, debugging, lab work, test equipment, soldering, German language skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c79f57de-0e6"},"title":"R&D Engineering-Sign Off, Principal Engineer","description":"As a member of the IP Digital Design Methodology team, you will work with global teams to define best in class ASIC design standards and flows and assist IP development teams. You will be involved with next generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nYou are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.
\nYour technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.
\nYou will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.
\nYou will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.
\nYou will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.
\nYou will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nYou will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
\nYou will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.
\nYou will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.
\nYou will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_c79f57de-0e6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/r-and-d-engineering-sign-off-principal-engineer-15192/44408/91625669328","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$166000-$249000","x-skills-required":["ASIC Digital Signoff Engineer","EM and IR flows","High-speed digital IP cores and/or SOCs development","Static Timing Analysis (STA)","Power Analysis","EM/IR for advanced node designs","Synopsys tools","High-speed interface protocols"],"x-skills-preferred":["StarRC","ICV","HDMI","MIPI","PCIe","SATA","Ethernet","USB","DP","DDR"],"datePosted":"2026-03-09T11:02:21.865Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Digital Signoff Engineer, EM and IR flows, High-speed digital IP cores and/or SOCs development, Static Timing Analysis (STA), Power Analysis, EM/IR for advanced node designs, Synopsys tools, High-speed interface protocols, StarRC, ICV, HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, DDR","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":166000,"maxValue":249000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1b7bdffa-bff"},"title":"Senior Embedded Software Engineer, Android Platform","description":"Redefining computing relies on us creating hardware and software that seamlessly merge virtual reality and the real world. To create this illusion, we are designing and developing completely new ways of using cameras, complex imaging pipelines, and computer vision algorithms.
\nWe are looking for a Senior Embedded Software Engineer to develop firmware for our advanced VR/XR products on the Qualcomm and Android platform, working in an embedded environment. You have experience developing high quality software for resource-constrained systems. You have an understanding of electronics, and are able to navigate your way through schematics.
\nThis is a highly technical space, and you will be working with some of the industry’s leading experts. You do not need to have a background in VR/XR, but you will need to show an interest and aptitude for bridging the gap between customers and deep technology. You can get into the detail of topics, but also to provide clear written and oral synthesis.
\nExperience building hardware products and/or products that require researching and inventing new technology is preferred. This position is based in Finland. Varjo uses hybrid work mode and you'll be able to choose either to work at the office or remotely. To effectively perform in this role, we expect that you will need to visit our Helsinki office whenever necessary to work with prototype hardware.
\nWhat you’ll be doing
\nOur expectations
\nNext steps
\nBy joining us, you’ll get:
\nAs we are developing the next computing paradigm, we need a versatile team to help ensure that the new realities are designed for everyone. Our multicultural team consists of talents from all around the world, and our daily working language is English. We believe in the power of diversity – where different experiences, backgrounds, and ideas drive innovation and results.
\nEven if your profile is not a perfect match but you want to learn and grow, we’d love to hear from you. Ready to jump into the exciting world of VR/XR? Apply now by including your CV and a link to your LinkedIn profile.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_1b7bdffa-bff","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Varjo","sameAs":"https://apply.workable.com","logo":"https://logos.yubhub.co/j.com.png"},"x-apply-url":"https://apply.workable.com/j/C71C4BCA96","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Android BSP","Platform development","AOSP bring-up on ARM/Qualcomm SoCs","Linux kernel","Device trees","Qualcomm toolchains","C/C++","Scripting (Python or Bash)","Git","CI/CD","Embedded development toolchains"],"x-skills-preferred":["Yocto","U-Boot","Embedded build systems","XR/VR or multimedia pipelines on Android"],"datePosted":"2026-03-08T17:56:07.721Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Helsinki"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Android BSP, Platform development, AOSP bring-up on ARM/Qualcomm SoCs, Linux kernel, Device trees, Qualcomm toolchains, C/C++, Scripting (Python or Bash), Git, CI/CD, Embedded development toolchains, Yocto, U-Boot, Embedded build systems, XR/VR or multimedia pipelines on Android"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_57cc6c48-a0b"},"title":"Senior Firmware Engineering","description":"Summary
\nMicrosoft are looking for a talented Senior Firmware Engineering at their Beijing office. This role sits at the heart of strategic decision-making, turning market data into actionable insights for a company that's revolutionising haptic entertainment technology. You'll work directly with leadership to shape the company's direction in the cinema and simulation markets.
\nAbout the Role
\nAs a firmware engineer on our team, you will play a key role in enabling real-time intelligence on resource-constrained hardware. Your work will involve designing and optimizing embedded systems, integrating sensors and connectivity modules, and ensuring ultra-low-power performance without compromising user experience. You will collaborate closely with cross-disciplinary experts in hardware, software, and AI to bring innovative ideas from prototype to product.
\nAccountabilities
\nThe Candidate we're looking for
\nExperience:
\nTechnical skills:
\nPersonal attributes:
\nBenefits
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_57cc6c48-a0b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Microsoft","sameAs":"https://microsoft.ai","logo":"https://logos.yubhub.co/microsoft.ai.png"},"x-apply-url":"https://microsoft.ai/job/senior-firmware-engineering-2/","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["embedded firmware","SoCs","low-power","real-time constraints","firmware development","wearable devices"],"x-skills-preferred":["AI","hardware","software"],"datePosted":"2026-03-06T07:31:54.995Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Beijing"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"embedded firmware, SoCs, low-power, real-time constraints, firmware development, wearable devices, AI, hardware, software"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e57b3780-0c9"},"title":"Principle Firmware Engineer","description":"Summary
\nMicrosoft AI are looking for a talented Principle Firmware Engineer at their Beijing office. This role sits at the heart of strategic decision-making, turning market data into actionable insights for a company that's revolutionising haptic entertainment technology. You'll work directly with leadership to shape the company's direction in the cinema and simulation markets.
\nAbout the Role
\nAs a firmware engineer on our team, you will play a key role in enabling real-time intelligence on resource-constrained hardware. Your work will involve designing and optimizing embedded systems, integrating sensors and connectivity modules, and ensuring ultra-low-power performance without compromising user experience. You will collaborate closely with cross-disciplinary experts in hardware, software, and AI to bring innovative ideas from prototype to product.
\nAccountabilities
\nThe Candidate we're looking for
\nExperience:
\nTechnical skills:
\nPersonal attributes:
\nBenefits
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_e57b3780-0c9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Microsoft AI","sameAs":"https://microsoft.ai","logo":"https://logos.yubhub.co/microsoft.ai.png"},"x-apply-url":"https://microsoft.ai/job/principle-firmware-engineer-2/","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["embedded firmware","SoCs","low-power","real-time constraints","firmware development","wearable devices"],"x-skills-preferred":["AI","machine learning","data analysis"],"datePosted":"2026-03-06T07:27:30.136Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Beijing"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"embedded firmware, SoCs, low-power, real-time constraints, firmware development, wearable devices, AI, machine learning, data analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_509e3a3b-0fb"},"title":"ASIC Physical Design, Sr Staff","description":"Opening. This role is a key member of the Interface IP Design Methodology team, working with global teams to define best practice ASIC design standards and flows. The team is responsible for next-generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nWhat you'll do
\nDevelop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.
\nWork with leading edge designs and teams to drive the industry best PPA for IP designs.
\nEvaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.
\nDevelop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
\nWork as a liaison between EDAG tool and IP design teams.
\nContinuously improve and refine design processes to enhance efficiency and performance.
\nWhat you need
\nBS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.
\nKnowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
\nDirect hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.
\nAbility to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
\nGood analysis, debugging, and problem-solving skills.
\nSolid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nFamiliarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.
\nWorking knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_509e3a3b-0fb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-staff/44408/91568840304","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["BS or MS in EE","10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs","Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions","Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools","Ability to facilitate cross-functional collaboration","Good analysis, debugging, and problem-solving skills","Solid written and verbal communication skills"],"x-skills-preferred":["Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools)","Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR"],"datePosted":"2026-02-11T16:09:21.948Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BS or MS in EE, 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs, Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions, Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools, Ability to facilitate cross-functional collaboration, Good analysis, debugging, and problem-solving skills, Solid written and verbal communication skills, Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools), Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_81bbd9fe-0bd"},"title":"Firmware Manager - Audio","description":"We are seeking a highly skilled Firmware Manager - Audio to lead and mentor an audio firmware team, including task planning, technical guidance, and performance management. The successful candidate will own audio firmware architecture and technical direction for gaming peripheral products, overseeing development of audio protocol (USB, Bluetooth, 2.4 GHz wireless), DSP control, codecs, and latency optimization.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_81bbd9fe-0bd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"CORSAIR","sameAs":"https://edix.fa.us2.oraclecloud.com"},"x-apply-url":"https://edix.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/8687","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["embedded firmware development","audio firmware for consumer or gaming devices","MCUs/SoCs, RTOS, DSPs, and low-level driver development"],"x-skills-preferred":["CI/CD for embedded systems","power profiling tools and energy-aware design"],"datePosted":"2026-02-03T15:02:47.465Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"New Taipei City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"embedded firmware development, audio firmware for consumer or gaming devices, MCUs/SoCs, RTOS, DSPs, and low-level driver development, CI/CD for embedded systems, power profiling tools and energy-aware design"}]}