{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/simulators"},"x-facet":{"type":"skill","slug":"simulators","display":"Simulators","count":22},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c79ae434-27a"},"title":"Senior HILS Application Engineer I","description":"<p><strong>What Makes a Honda, is Who makes a Honda</strong></p>\n<p>Honda has a clear vision for the future, and it’s a joyful one. We are looking for individuals with the skills, courage, persistence, and dreams that will help us reach our future-focused goals. At our core is innovation. Honda is constantly innovating and developing solutions to drive our business with record success.</p>\n<p>We are looking for qualified individuals with diverse backgrounds, experiences, continuous improvement values, and a strong work ethic to join our team.</p>\n<p>If your goals and values align with Honda’s, we want you to join our team to Bring the Future!</p>\n<p><strong>JOB PURPOSE:</strong></p>\n<p>The HILS Application Engineer III is responsible for the design, assembly, validation, and test deployment of HILS (Hardware-in-the-Loop Simulation) systems to support vehicle embedded software development.</p>\n<p><strong>KEY ACCOUNTABILITIES:</strong></p>\n<p>Creates and maintains software validation test plans to ensure complete coverage of test requirements by a given project development milestone. Responsible for the complete design of a HIL Simulator which includes simulator hardware selection, plant model specification and programming, I/O channel selection, and simulator/controller harness design. Prepares test automation scripts to meet testing requirements from the system function team. Accurately reports test results and conditions so that correct system judgments may be made. Documents test conduct and results, problems and resolutions and results of investigations in an established database. Coordinates the strategy to design, purchase, and deploy new HILS systems with the Global Engineering Center and System Suppliers Collects, implements, and maintains prototype control software and physical system models from related function groups.</p>\n<p><strong>QUALIFICATIONS, EXPERIENCE, &amp; SKILLS:</strong></p>\n<p><strong>Minimum Educational Qualifications:</strong></p>\n<p>A Bachelor&#39;s or equivalent degree / diploma in Mathematics / Computer Science / Electrical or Electronics Engineering or, Software Engineering or equivalent relevant work experience.</p>\n<p><strong>Minimum work experience:</strong></p>\n<p>3 or more years of relevant experience in the industry.</p>\n<p><strong>Required qualifying skills:</strong></p>\n<p>Must have strong demonstrable skills in Matlab / Simulink, in the control field. Working knowledge of embedded control (real-time), simulators and software. Acceptable platforms are dSPACE, National Instruments, Vector, and/or OEM Proprietary Tools A working knowledge of electrical and signal measurement tools and software. Working knowledge of vehicle systems and networks. Python programming skills.</p>\n<p><strong>Other Job-Specific Skills:</strong></p>\n<p>Strong quantitative/analytical problem-solving skills are required. Working knowledge of system modelling using CAE (Computer Aided Engineering) and analysis Ability to work effectively with team members and with peers across the organization. Decision-making skills, able to make sound decisions on mildly complex matters. Ability to multi-task and work with minimal supervision. Effective communication skills (written, verbal and presentation) Ability to manage time effectively and productively Can clarify and confirm understanding with Team Leaders and staff</p>\n<p><strong>Workstyle:</strong></p>\n<p>Must be able to work onsite at our Auto Development Center (ADC), in Raymond, OH. One remote workday a week may be possible with prior departmental approval.</p>\n<p><strong>What differentiates Honda and make us an employer of choice?</strong></p>\n<p><strong>Total Rewards:</strong></p>\n<p>Competitive Base Salary (pay will be based on several variables that include, but not limited to geographic location, work experience, etc.) Paid Overtime Regional Bonus (when applicable) Industry-leading Benefit Plans (Medical, Dental, Vision, Rx) Paid time off, including vacation, holidays, shutdown Company Paid Short-Term and Long-Term Disability 401K Plan with company match + additional contribution Relocation assistance (if eligible)</p>\n<p><strong>Career Growth:</strong></p>\n<p>Advancement Opportunities Career Mobility Education Reimbursement for Continued Learning Training and Development programs</p>\n<p><strong>Additional Offerings:</strong></p>\n<p>Tuition Assistance &amp; Student Loan Repayment Lifestyle Account Childcare Reimbursement Account Elder Care Support Wellbeing Program Community Service and Engagement Programs Product Programs</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c79ae434-27a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Honda","sameAs":"https://careers.honda.com","logo":"https://logos.yubhub.co/careers.honda.com.png"},"x-apply-url":"https://careers.honda.com/us/en/job/10676/Senior-HILS-Application-Engineer-I","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$82,800.00 - $103,500.00","x-skills-required":["Matlab","Simulink","Embedded control","Real-time","Simulators","Software","dSPACE","National Instruments","Vector","OEM Proprietary Tools","Electrical and signal measurement tools","Vehicle systems","Networks","Python"],"x-skills-preferred":[],"datePosted":"2026-04-22T17:25:01.400Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Raymond"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Automotive","skills":"Matlab, Simulink, Embedded control, Real-time, Simulators, Software, dSPACE, National Instruments, Vector, OEM Proprietary Tools, Electrical and signal measurement tools, Vehicle systems, Networks, Python","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":82800,"maxValue":103500,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c18f4d79-e07"},"title":"RF Communications Engineer, Space","description":"<p>Anduril Industries is seeking a RF Communications Engineer for our Space team. As a RF Communications Engineer, you will contribute to the design of all satellite communications subsystems, including bus TT&amp;C, mission data links, and inter-satellite links. You will possess deep knowledge of RF and optical systems, including link budget ownership, subsystem design, and the integration of NSA-approved Type 1 encryption. You will author space-to-ground ICDs and become familiar with Anduril&#39;s ground software enterprise and orbital flight software systems.</p>\n<p>The Spacecraft Comms team will work closely with related teams, such as the spacecraft design, ground, and flight software, to help improve both the ground and satellite-based capabilities. Your primary responsibility will be the successful design, test, and operations of the various communications links onboard Anduril&#39;s fleet of spacecraft.</p>\n<p>This role is directly tied to ongoing, funded programs within Anduril&#39;s Space Business Line. The programs require building and fielding a resilient, software-defined spacecraft systems across numerous mission threads. You will work with mission partners and customers to deploy reliable and robust capabilities on operationally-relevant fielding timelines to meet complex challenges across the DOD and IC.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Contributing to the spacecraft communications subsystems for various spacecraft programs in all orbital regimes</li>\n<li>Integrating with legacy systems to unlock 21st-century capabilities</li>\n<li>Developing modern, software-defined approaches to autonomous spacecraft communications leveraging proliferated constellations of ground and space-based assets</li>\n<li>Owning space-to-ground and space-to-space ICDs and designs for communication subsystems</li>\n<li>Collaborating across multiple teams to plan, build, and test complex functionality</li>\n<li>Coordinating with end-users, other operators, and customers to turn needs into features while balancing user experience with engineering constraints</li>\n<li>Supporting challenging schedules during ground testing, launch windows, and on-orbit operations of the spacecraft systems</li>\n</ul>\n<p>Required qualifications include:</p>\n<ul>\n<li>Strong engineering background from industry or school, ideally in areas/fields such as Electrical Engineering, RF Engineering, Computer Science, or other engineering degree</li>\n<li>Experience conducting spacecraft operations and satellite command and control with an emphasis on system reliability and uptime</li>\n<li>Flexible and agile problem-solving skills</li>\n<li>Working knowledge of and experience with MATLAB</li>\n<li>Ability to quickly understand and navigate complex systems and detailed requirements</li>\n<li>Experience with RF subsystem design for space-space and space-ground in multiple orbital regimes</li>\n<li>Experience with optical inter-satellite and optical space-ground systems</li>\n<li>Capable of solving complex technical problems with little oversight</li>\n<li>Clear communication and organizational skills, including creating documentation and training materials</li>\n<li>Currently possesses and is able to maintain an active U.S. Top Secret security clearance</li>\n</ul>\n<p>Preferred qualifications include:</p>\n<ul>\n<li>Experience with Python, Go, C++, and/or Linux systems</li>\n<li>A desire to work on critical software and hardware designs in the space domain</li>\n<li>Experience testing comms subsystems in laboratory environments that mimic the space environmental constraints</li>\n<li>Experience with testing/validation leveraging FlatSats, Hardware-in-the-Loop testbeds, and digital spacecraft simulators through nominal and fault scenarios</li>\n<li>Exposure to ground station operations and providers</li>\n<li>Exposure to US satellite operations policy and constraints for relevant mission threads in all orbits</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c18f4d79-e07","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anduril Industries","sameAs":"https://www.andurilindustries.com/","logo":"https://logos.yubhub.co/andurilindustries.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/andurilindustries/jobs/5075880007","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$146,000-$194,000 USD","x-skills-required":["RF Engineering","Electrical Engineering","Computer Science","MATLAB","Python","Go","C++","Linux systems","Top Secret security clearance"],"x-skills-preferred":["FlatSats","Hardware-in-the-Loop testbeds","digital spacecraft simulators"],"datePosted":"2026-04-18T15:56:38.668Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Costa Mesa, California, United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RF Engineering, Electrical Engineering, Computer Science, MATLAB, Python, Go, C++, Linux systems, Top Secret security clearance, FlatSats, Hardware-in-the-Loop testbeds, digital spacecraft simulators","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":146000,"maxValue":194000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_21b84b4c-3f3"},"title":"Senior Robotics Engineer","description":"<p>About Mistral</p>\n<p>At Mistral AI, we believe in the power of AI to simplify tasks, save time, and enhance learning and creativity. Our technology is designed to integrate seamlessly into daily working life.</p>\n<p>We are a global company with teams distributed between France, the USA, the UK, Germany, and Singapore.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Deploy state-of-the-art AI models for mobile manipulation, built in-house, on real robots</li>\n</ul>\n<ul>\n<li>Architect and optimise data pipelines for cutting-edge robotics model training on massive datasets</li>\n</ul>\n<ul>\n<li>Set up and maintain fleets of robots of various types</li>\n</ul>\n<ul>\n<li>Conduct experiments and validate robotic systems in real-world environments</li>\n</ul>\n<ul>\n<li>Interact and learn from all Mistral&#39;s engineers and researchers</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>You have hands-on experience developing software for real-world robotics</li>\n</ul>\n<ul>\n<li>Mastery of Python and proven experience as a developer</li>\n</ul>\n<ul>\n<li>You have high engineering competence. This means being able to design complex software and make it usable in production</li>\n</ul>\n<ul>\n<li>You are a self-starter, autonomous and a team player</li>\n</ul>\n<ul>\n<li>You have a proactive approach with a &#39;get things done&#39; spirit</li>\n</ul>\n<ul>\n<li>You are flexible and adaptable to collaborate effectively with other engineers and researchers</li>\n</ul>\n<p><strong>Nice to Have</strong></p>\n<ul>\n<li>Experience in building and deploying AI systems on real physical robots</li>\n</ul>\n<ul>\n<li>Experience with hardware development, mechanical and CAD design, and 3D printing</li>\n</ul>\n<ul>\n<li>Experience with robotics simulators</li>\n</ul>\n<ul>\n<li>Experience with maintaining large, high-quality code bases</li>\n</ul>\n<ul>\n<li>Proficiency in coding for robotic control, such as ROS</li>\n</ul>\n<ul>\n<li>Hands-on experience with sensor integration and actuator control</li>\n</ul>\n<ul>\n<li>Knowledge of control theory, machine learning, or computer vision as applied to robotics</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Competitive cash salary and equity</li>\n</ul>\n<ul>\n<li>Food: Daily lunch vouchers</li>\n</ul>\n<ul>\n<li>Sport: Monthly contribution to a Gympass subscription</li>\n</ul>\n<ul>\n<li>Transportation: Monthly contribution to a mobility pass</li>\n</ul>\n<ul>\n<li>Health: Full health insurance for you and your family</li>\n</ul>\n<ul>\n<li>Parental: Generous parental leave policy</li>\n</ul>\n<ul>\n<li>Visa sponsorship</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_21b84b4c-3f3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Mistral AI","sameAs":"https://mistral.ai","logo":"https://logos.yubhub.co/mistral.ai.png"},"x-apply-url":"https://jobs.lever.co/mistral/ef744f52-3ceb-42f1-84f6-1c8bde220eb1","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Python","AI","Robotics","Software Development","Data Pipelines","ROS"],"x-skills-preferred":["Hardware Development","Mechanical Design","CAD","3D Printing","Robotics Simulators","Sensor Integration","Actuator Control","Control Theory","Machine Learning","Computer Vision"],"datePosted":"2026-04-17T12:48:00.221Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Paris"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Python, AI, Robotics, Software Development, Data Pipelines, ROS, Hardware Development, Mechanical Design, CAD, 3D Printing, Robotics Simulators, Sensor Integration, Actuator Control, Control Theory, Machine Learning, Computer Vision"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9dfaf7ad-b1c"},"title":"AI Scientist - Robotics","description":"<p>About Mistral</p>\n<p>At Mistral, we are on a mission to democratize AI, producing frontier intelligence for everyone, developed in the open, and built by engineers all over the world.</p>\n<p>We develop models for the enterprise and for consumers, focusing on delivering systems which can really change the way in which businesses operate and which can integrate into our daily lives. All while releasing frontier models open-source, for everyone to try and benefit.</p>\n<p><strong>Job Description</strong></p>\n<p>We are hiring experts in the training of large language models and distributed systems. Join us to be part of a pioneering company shaping the future of AI.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Research and develop novel AI methods for general-purpose mobile manipulation robots</li>\n<li>Build tooling and infrastructure to allow training, evaluation and analysis of AI models at scale</li>\n<li>Work cross-functionally with other scientists, engineers and product teams to deploy AI systems on real robot platforms</li>\n</ul>\n<p><strong>About You</strong></p>\n<ul>\n<li>You have hands-on experience either building and deploying AI systems on physical robots or developing large vision-language models</li>\n<li>You are a highly proficient software engineer in at least one programming language (preferably Python)</li>\n<li>You have hands-on experience with AI frameworks (preferably PyTorch)</li>\n<li>You have high engineering competence. This means being able to design complex software and make it usable in production</li>\n<li>You are a self-starter, autonomous and a team player</li>\n</ul>\n<p><strong>Nice to Have</strong></p>\n<ul>\n<li>You have experience in one or more of the following: navigation, manipulation, simulators, 3D, embodied reasoning or vision-language-action models</li>\n<li>You can navigate the full MLOps stack, for instance, fine-tuning, evaluation and deployment</li>\n<li>You have a strong publication record in a relevant scientific domain</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>In France:</p>\n<ul>\n<li>Competitive cash salary and equity</li>\n<li>Food: Daily lunch vouchers</li>\n<li>Sport: Monthly contribution to a Gympass subscription</li>\n<li>Transportation: Monthly contribution to a mobility pass</li>\n<li>Health: Full health insurance for you and your family</li>\n<li>Parental: Generous parental leave policy</li>\n<li>Visa sponsorship</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9dfaf7ad-b1c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Mistral","sameAs":"https://www.mistral.ai/","logo":"https://logos.yubhub.co/mistral.ai.png"},"x-apply-url":"https://jobs.lever.co/mistral/60f9dc5b-6d1c-4236-be38-be7233669f00","x-work-arrangement":"hybrid","x-experience-level":null,"x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Python","PyTorch","AI frameworks","software engineering","complex software design"],"x-skills-preferred":["navigation","manipulation","simulators","3D","embodied reasoning","vision-language-action models"],"datePosted":"2026-04-17T12:46:16.247Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Paris"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Python, PyTorch, AI frameworks, software engineering, complex software design, navigation, manipulation, simulators, 3D, embodied reasoning, vision-language-action models"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_455b32d6-da0"},"title":"IP Verification (USB)- Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p>You Are:\nYou are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.</p>\n<p>You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.</p>\n<p>What You’ll Be Doing:\nSpecify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\nDevelop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\nDesign, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\nPerform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\nCollaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\nLeverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\nContribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.</p>\n<p>The Impact You Will Have:\nEnsure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\nDrive innovation in verification methodologies, setting new standards for efficiency and coverage.\nEnhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\nStrengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\nMentor and support junior engineers, fostering a culture of learning and continuous improvement.\nContribute to the success of global, multi-site R&amp;D teams by providing expertise and driving cross-functional collaboration.</p>\n<p>What You’ll Need:\nBSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.\nExpertise in developing HVL (System Verilog)-based verification environments and testbenches.\nStrong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\nProficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\nSolid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\nFamiliarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\nDemonstrated ability to work with functional coverage-driven methodologies and quality metric goals.</p>\n<p>Who You Are:\nAnalytical thinker with strong problem-solving and debugging skills.\nExcellent verbal and written communication abilities.\nTeam player who thrives in collaborative, multi-site environments.\nProactive, self-motivated, and able to take initiative on challenging projects.\nDetail-oriented, quality-focused, and driven by a desire to excel.\nAdaptable and eager to continuously learn and apply new technologies.</p>\n<p>The Team You’ll Be A Part Of:\nYou will join the Solutions Group’s DesignWare IP Verification R&amp;D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.</p>\n<p>Rewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>A peek inside our office</p>\n<p>Benefits:\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_455b32d6-da0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/ip-verification-usb-staff-engineer/44408/92684730560","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["System Verilog","UVM/OVM/VMM","HVL-based test environments","Industry-standard simulators (VCS, NC, MTI)","Debugging tools","Functional coverage-driven methodologies","Quality metric goals","MIPI-I3C","UFS","AMBA","Ethernet","DDR","PCIe","USB","Perl","TCL","Python","VIP development","Formal verification"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:02.691Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"System Verilog, UVM/OVM/VMM, HVL-based test environments, Industry-standard simulators (VCS, NC, MTI), Debugging tools, Functional coverage-driven methodologies, Quality metric goals, MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, USB, Perl, TCL, Python, VIP development, Formal verification"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_410ca56b-a94"},"title":"Analog Design, Principal Engineer (SerDes)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p>You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.</p>\n<p>With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.</p>\n<p>Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.</p>\n<p>You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.</p>\n<p>Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.</p>\n<p>You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.</p>\n<p>As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.</p>\n<p>You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.</p>\n<p>Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.</p>\n<p>Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.</p>\n<p>Track and review the technical progress of sub-block owners, ensuring alignment with project goals.</p>\n<p>Interpret SerDes standards and architecture documents to develop detailed analog specifications.</p>\n<p>Identify and refine circuit implementations, optimizing for power, area, and performance targets.</p>\n<p>Propose and execute design and verification strategies using advanced simulator features for robust outcomes.</p>\n<p>Oversee physical layout to minimize parasitics, device stress, and process variation impacts.</p>\n<p>Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.</p>\n<p>Present simulation data and technical insights for peer and customer reviews.</p>\n<p>Mentor and review the progress of junior engineers, fostering growth and technical excellence.</p>\n<p>Document design features, methodologies, and test plans for internal and customer use.</p>\n<p>Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.</p>\n<p>Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.</p>\n<p>Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.</p>\n<p>Contribute to the success of global customers by delivering robust, silicon-proven analog macros.</p>\n<p>Enhance cross-functional collaboration across design, layout, and digital teams.</p>\n<p>Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.</p>\n<p>Influence the direction of advanced analog design methodologies and verification strategies.</p>\n<p>Provide technical leadership in customer engagements and peer reviews.</p>\n<p>Support continuous improvement in design processes and documentation practices.</p>\n<p>PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.</p>\n<p>Expertise in transistor-level circuit design and strong CMOS design fundamentals.</p>\n<p>Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.</p>\n<p>Leadership experience in guiding small teams through macro-level design projects.</p>\n<p>In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.</p>\n<p>Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.</p>\n<p>Awareness of ESD and reliability issues, including circuit techniques and layout strategies.</p>\n<p>Proficiency with EDA tools for schematic entry, physical layout, and design verification.</p>\n<p>Experience with SPICE simulators for detailed circuit analysis.</p>\n<p>Familiarity with analog behavioral modeling and simulation control using Verilog-A.</p>\n<p>Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.</p>\n<p>Analytical thinker with exceptional problem-solving skills.</p>\n<p>Collaborative leader and effective communicator.</p>\n<p>Detail-oriented and methodical in approach.</p>\n<p>Adaptable and open to learning new technologies.</p>\n<p>Mentor and role model for junior engineers.</p>\n<p>Self-motivated and proactive in driving project outcomes.</p>\n<p>Committed to excellence, reliability, and innovation.</p>\n<p>You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.</p>\n<p>The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.</p>\n<p>Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>Synopsys Canada ULC values the diversity of our workforce.</p>\n<p>We are committed to provide access &amp; opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.</p>\n<p>Should you require an accommodation, please contact <a href=\"mailto:hr-help-canada@synopsys.com\">hr-help-canada@synopsys.com</a>.</p>\n<p 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Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2f9b4dd6-6f1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/emulation-applications-engineer-sr-staff-15518/44408/92669904624","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$157000-$235000","x-skills-required":["Emulation and/or Prototyping flows, systems, and methodologies","Verilog, System Verilog, and VHDL","Verification concepts and functional simulators","Scripting languages","Simulation flows, Assertion, DPI, and Transactors"],"x-skills-preferred":["Synthesis and timing analysis concepts","Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality","Xilinx & Altera architecture and toolchains","SW/HW debug methodologies and standard SW/HW debug tools"],"datePosted":"2026-04-05T13:21:37.842Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Emulation and/or Prototyping flows, systems, and methodologies, Verilog, System Verilog, and VHDL, Verification concepts and functional simulators, Scripting languages, Simulation flows, Assertion, DPI, and Transactors, Synthesis and timing analysis concepts, Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality, Xilinx & Altera architecture and toolchains, SW/HW debug methodologies and standard SW/HW debug tools","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4815342e-ce8"},"title":"Analog Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p>You Are:</p>\n<p>You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Develop and specify SERDES transceiver architectures and sub-blocks based on standards.</li>\n<li>Design, simulate, and verify high-speed analog circuits for optimal power and performance.</li>\n<li>Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.</li>\n<li>Present technical results internally and externally to customers and industry groups.</li>\n<li>Oversee physical layout to address parasitics and reliability concerns.</li>\n<li>Document features and test plans, and support post-silicon analysis and updates.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Advance industry-leading SERDES IP for next-generation SoCs.</li>\n<li>Enhance product differentiation and customer value.</li>\n<li>Streamline design processes for quality and time-to-market.</li>\n<li>Mentor junior team members and share best practices.</li>\n<li>Influence technical direction and innovation at Synopsys.</li>\n<li>Support customer success and product reliability.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.</li>\n<li>Expertise in transistor-level CMOS design and SERDES sub-circuits.</li>\n<li>Proficiency with schematic, layout, and verification tools; SPICE simulators.</li>\n<li>Experience with scripting languages (Verilog-A, TCL, Python, etc.).</li>\n<li>Strong communication and documentation skills.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Technical leader and mentor</li>\n<li>Collaborative and proactive</li>\n<li>Analytical and detail-oriented</li>\n<li>Adaptable and innovative</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4815342e-ce8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/kanata/analog-design-engineer/44408/93286401584","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["High-speed SERDES IP","Transistor-level CMOS design","SERDES sub-circuits","Schematic, layout, and verification tools","SPICE simulators","Scripting languages (Verilog-A, TCL, Python, etc.)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:26.629Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Kanata"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"High-speed SERDES IP, Transistor-level CMOS design, SERDES sub-circuits, Schematic, layout, and verification tools, SPICE simulators, Scripting languages (Verilog-A, TCL, Python, etc.)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f8851d08-dec"},"title":"Research Scientist, Robotics","description":"<p><strong>Job Title</strong></p>\n<p>Research Scientist, Robotics</p>\n<p><strong>Role Details</strong></p>\n<p>We are looking for Research Scientists to join the Robotics team at Google DeepMind. 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Visa sponsorship.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_341239c4-263","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Mistral AI","sameAs":"https://mistral.ai"},"x-apply-url":"https://jobs.lever.co/mistral/ef744f52-3ceb-42f1-84f6-1c8bde220eb1","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"Competitive cash salary and equity","x-skills-required":["Python","ROS","Machine Learning","Computer Vision","Control Theory","Sensor Integration","Actuator Control"],"x-skills-preferred":["Hardware Development","Mechanical Design","CAD Design","3D Printing","Robotics Simulators","Maintaining Large Code Bases"],"datePosted":"2026-03-10T11:32:18.772Z","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Python, ROS, Machine Learning, Computer Vision, Control Theory, Sensor Integration, Actuator Control, Hardware Development, Mechanical Design, CAD Design, 3D Printing, Robotics Simulators, Maintaining Large Code Bases"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a15e1d6-e69"},"title":"AI Scientist - Robotics","description":"<p>About this role</p>\n<p>We are hiring experts in the training of large language models and distributed systems to join our research team.</p>\n<p>Key responsibilities:</p>\n<ul>\n<li>Research and develop novel AI methods for general-purpose mobile manipulation robots</li>\n<li>Build tooling and infrastructure to allow training, evaluation and analysis of AI models at scale</li>\n<li>Work cross-functionally with other scientists, engineers and product teams to deploy AI systems on real robot platforms</li>\n</ul>\n<p>About you</p>\n<ul>\n<li>You have hands-on experience either building and deploying AI systems on physical robots or developing large vision-language models</li>\n<li>You are a highly proficient software engineer in at least one programming language (preferably Python)</li>\n<li>You have hands-on experience with AI frameworks (preferably PyTorch)</li>\n<li>You have high engineering competence. This means being able to design complex software and make it usable in production</li>\n</ul>\n<p>Ideal candidates will have experience in one or more of the following:</p>\n<ul>\n<li>Navigation, manipulation, simulators, 3D, embodied reasoning or vision-language-action models</li>\n<li>The full MLOps stack, for instance, fine-tuning, evaluation and deployment</li>\n</ul>\n<p>Benefits in France</p>\n<ul>\n<li>Competitive cash salary and equity</li>\n<li>Food: Daily lunch vouchers</li>\n<li>Sport: Monthly contribution to a Gympass subscription</li>\n<li>Transportation: Monthly contribution to a mobility pass</li>\n<li>Health: Full health insurance for you and your family</li>\n<li>Parental: Generous parental leave policy</li>\n<li>Visa sponsorship</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a15e1d6-e69","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Mistral","sameAs":"https://www.mistral.ai/"},"x-apply-url":"https://jobs.lever.co/mistral/60f9dc5b-6d1c-4236-be38-be7233669f00","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["AI","Robotics","Python","PyTorch","Software Engineering"],"x-skills-preferred":["Navigation","Manipulation","Simulators","3D","Embodied Reasoning","Vision-Language-Action Models","MLOps"],"datePosted":"2026-03-10T11:22:55.596Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Paris"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"AI, Robotics, Python, PyTorch, Software Engineering, Navigation, Manipulation, Simulators, 3D, Embodied Reasoning, Vision-Language-Action Models, MLOps"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5f4e85a9-296"},"title":"Staff Analog Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15391</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.</p>\n<p>You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.</p>\n<p>Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</li>\n</ul>\n<ul>\n<li>Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</li>\n</ul>\n<ul>\n<li>Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</li>\n</ul>\n<ul>\n<li>Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</li>\n</ul>\n<ul>\n<li>Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.</li>\n</ul>\n<ul>\n<li>Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.</li>\n</ul>\n<ul>\n<li>Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.</li>\n</ul>\n<ul>\n<li>Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.</li>\n</ul>\n<ul>\n<li>Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.</li>\n</ul>\n<ul>\n<li>Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</li>\n</ul>\n<ul>\n<li>Proven expertise with FinFET technologies and CMOS tape-outs.</li>\n</ul>\n<ul>\n<li>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</li>\n</ul>\n<ul>\n<li>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</li>\n</ul>\n<ul>\n<li>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</li>\n</ul>\n<ul>\n<li>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</li>\n</ul>\n<ul>\n<li>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</li>\n</ul>\n<ul>\n<li>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</li>\n</ul>\n<ul>\n<li>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</li>\n</ul>\n<ul>\n<li>Excellent communication and documentation skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and open-minded, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Detail-oriented and thorough, with a commitment to delivering high-quality results.</li>\n</ul>\n<ul>\n<li>Analytical thinker with strong problem-solving abilities and a proactive approach.</li>\n</ul>\n<ul>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in fast-paced, dynamic environments.</li>\n</ul>\n<ul>\n<li>Committed to fostering an inclusive, innovative, and supportive workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a world-class analog and mixed-signal R&amp;D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and patern</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5f4e85a9-296","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/staff-analog-design-engineer/44408/92076328848","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability","schematic entry","physical layout","design verification tools","SPICE simulators","scripting languages","system-level budgeting","signal integrity"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:05:32.632Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, schematic entry, physical layout, design verification tools, SPICE simulators, scripting languages, system-level budgeting, signal integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b01a6d01-525"},"title":"Researcher, Synthetic RL","description":"<p><strong>Job Posting</strong></p>\n<p><strong>Researcher, Synthetic RL</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Research</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$295K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>The Synthetic RL team develops reinforcement learning methods that leverage synthetic data, environments, and feedback to train and evaluate frontier AI models. The team explores approaches such as self-play, simulators, and other synthetic evaluations to push model capability, generalization, and alignment beyond what is possible with the current prevailing methodology.</p>\n<p><strong>About the Role</strong></p>\n<p>As a <strong>Research Scientist</strong> on the Synthetic RL team, you will develop novel reinforcement learning techniques that use synthetic environments and feedback to improve large-scale models. You’ll work closely with other researchers to design experiments, analyze learning dynamics, and translate research insights into training approaches used in production systems.</p>\n<p>We’re looking for researchers who enjoy working on open-ended problems, value fast iteration, and want their work to directly shape how frontier models are trained.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Research and develop reinforcement learning algorithms</li>\n</ul>\n<ul>\n<li>Design and run experiments to study training dynamics and model behavior at scale</li>\n</ul>\n<ul>\n<li>Collaborate with engineers and researchers to integrate successful approaches into model training pipelines</li>\n</ul>\n<p><strong>You might thrive in this role if you:</strong></p>\n<ul>\n<li>Have a strong background in reinforcement learning, machine learning research, or related fields</li>\n</ul>\n<ul>\n<li>Have strong engineering and statistical analysis skills</li>\n</ul>\n<ul>\n<li>Enjoy exploring new problem spaces where data, objectives, and evaluation are imperfect or evolving</li>\n</ul>\n<ul>\n<li>Are motivated by seeing research ideas influence real-world AI systems</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b01a6d01-525","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/60d3700b-ba82-4fa6-a6bb-7b2b67070510","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$295K – $445K • Offers Equity","x-skills-required":["reinforcement learning","machine learning research","engineering","statistical analysis"],"x-skills-preferred":["self-play","simulators","synthetic evaluations"],"datePosted":"2026-03-06T18:40:07.490Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"reinforcement learning, machine learning research, engineering, statistical analysis, self-play, simulators, synthetic evaluations","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":295000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_568dcff2-ed1"},"title":"RTL & Co-design Engineer (junior)","description":"<p><strong>RTL &amp; Co-design Engineer (junior)</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.</p>\n<p>This role is based in San Francisco, CA. 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You will provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.</p>\n<ul>\n<li>Serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling.</li>\n<li>Provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.</li>\n<li>Lead product demonstrations, evaluations, and proof-of-concept projects that showcase PrimeLib&#39;s capabilities in real-world scenarios.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>BS/MS in Electrical Engineering, Computer Engineering, or a related field (PhD preferred).</li>\n<li>8+ years of experience in semiconductor design, library characterization, or EDA application engineering.</li>\n<li>Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries.</li>\n<li>Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators.</li>\n<li>Advanced scripting skills (Python, Perl, TCL) for automation and flow customization.</li>\n<li>Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models).</li>\n<li>Excellent verbal and written communication skills, with a proven ability to present complex technical concepts to varied audiences.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Accelerate customer adoption and success with PrimeLib, directly influencing the design of next-generation semiconductor products.</p>\n<p><strong>What you’ll be doing</strong></p>\n<ul>\n<li>Serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling.</li>\n<li>Provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.</li>\n<li>Lead product demonstrations, evaluations, and proof-of-concept projects that showcase PrimeLib&#39;s capabilities in real-world scenarios.</li>\n<li>Troubleshoot and resolve complex technical challenges related to timing, power, and signal integrity modeling.</li>\n<li>Collaborate with R&amp;D and product teams to influence the PrimeLib roadmap, advocating for customer needs and emerging technology trends.</li>\n<li>Develop and deliver technical training, best practices, and documentation to empower both customers and internal teams.</li>\n<li>Represent Synopsys and PrimeLib at industry conferences, technical forums, and customer workshops.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Accelerate customer adoption and success with PrimeLib, directly influencing the design of next-generation semiconductor products.</li>\n<li>Drive technical excellence and innovation by bridging customer requirements and R&amp;D advancements.</li>\n<li>Enhance Synopsys’ reputation as a trusted technology partner and thought leader in library characterization and EDA solutions.</li>\n<li>Shape the evolution of PrimeLib by capturing and relaying key customer insights to product development teams.</li>\n<li>Facilitate knowledge sharing and best practices that elevate the capabilities of customers and colleagues alike.</li>\n<li>Promote the adoption of advanced semiconductor process technologies through expert technical support and guidance.</li>\n<li>Build lasting relationships with Tier-1 semiconductor companies and industry leaders.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>BS/MS in Electrical Engineering, Computer Engineering, or a related field (PhD preferred).</li>\n<li>8+ years of experience in semiconductor design, library characterization, or EDA application engineering.</li>\n<li>Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries.</li>\n<li>Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators.</li>\n<li>Advanced scripting skills (Python, Perl, TCL) for automation and flow customization.</li>\n<li>Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models).</li>\n<li>Excellent verbal and written communication skills, with a proven ability to present complex technical concepts to varied audiences.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join a dynamic, high-impact Customer Application Services team focused on enabling customer success with Synopsys’ PrimeLib product. Our team works closely with R&amp;D, product management, and global customers to deliver technical excellence, foster innovation, and drive the adoption of industry-leading library characterization solutions.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_aed36d8a-c98","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/zapopan/senior-staff-field-application-engineer/44408/90581151904","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["BS/MS in Electrical Engineering, Computer Engineering, or a related field","8+ years of experience in semiconductor design, library characterization, or EDA application engineering","Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries","Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators","Advanced scripting skills (Python, Perl, TCL) for automation and flow customization","Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models)","Excellent verbal and written communication skills"],"x-skills-preferred":["Leadership","Collaboration","Problem-solving","Communication","Technical expertise"],"datePosted":"2026-01-21T15:06:18.837Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Zapopan, Jalisco, Mexico"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BS/MS in Electrical Engineering, Computer Engineering, or a related field, 8+ years of experience in semiconductor design, library characterization, or EDA application engineering, Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries, Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators, Advanced scripting skills (Python, Perl, TCL) for automation and flow customization, Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models), Excellent verbal and written communication skills, Leadership, Collaboration, Problem-solving, Communication, Technical expertise"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e21ac2ad-394"},"title":"Principal Verification Engineer","description":"<p>You are an experienced and innovative ASIC Digital Design Principal Engineer with a passion for verification and a keen eye for detail. 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