Your primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.

In addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.

You will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.

Finally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.

To be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.

Additionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.

If you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!

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What you'll do

• Leading silicon validation of IP functionality and performance, ensuring alignment with architectural intent.
• Supporting hardware bring-up and firmware integration for early product-version characterization.

What you need

• BSc or MSc in Electrical or Computer Engineering.
• 10+ years of experience in silicon validation, high-speed interfaces, and system-level performance analysis.

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What you'll do

You will design, develop, troubleshoot, and debug software programs for PCIe IP evaluation and test chip platforms.

• Designing, developing, troubleshooting, and debugging software programs for PCIe IP evaluation and test chip platforms.
• Developing scalable software tools, APIs, and architectures focused on evaluation software for Synopsys PCIe evaluation boards.

What you need

• Comprehensive expertise in PCIe protocol, SERDES, and hands-on experience with evaluation boards, silicon validation, or test chips.
• Advanced proficiency in Python, C++, or similar programming languages for embedded, driver, or system-level development.

Why this matters

Accelerate the evaluation and adoption of Synopsys's latest PCIe IP and test chips by delivering robust, user-friendly software tools. Enable seamless hardware bring-up and protocol validation, empowering both customers and internal teams to assess performance and compliance efficiently.

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What you'll do

• Conducting comprehensive testing on silicon implementations of high-speed analog integrated circuits in a cutting-edge R&D lab environment.
• Reviewing and debugging silicon under test, as well as supporting associated hardware systems to ensure optimal performance.

What you need

• Bachelor’s degree in Electrical Engineering (BSEE) or equivalent technical field with at least 3+ years of industry direct related experience.

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