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As a Silicon Power Engineer, you will be responsible for performing test case execution, debugging silicon issues related to correlation and functionality, and generating high-quality results and providing design feedback.</p>\n<p>You will work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic and high-energy work environment to bring industry-defining products to market.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Collaborating with cross-functional teams to craft essential next-generation product features that are important for performance, power optimization, and power management.</li>\n<li>Collaborating to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation.</li>\n<li>Working with various Arch &amp; Design teams to come up with test plans of new features.</li>\n<li>Collaborating with other validation &amp; bring-up teams to bring up/characterize silicon power and power saving features.</li>\n<li>Working with design &amp; estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.</li>\n<li>Developing power consumption models to be used in binning, productization, and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.</li>\n</ul>\n<p>We need to see:</p>\n<ul>\n<li>B. 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This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.</p>\n<p><strong>What you&#39;ll be doing:</strong></p>\n<ul>\n<li>Lead the design, automation, and validation of System Level Tests (SLT) for HVM (High Volume Manufacturing) for complex, high power, high speed SOCs.</li>\n<li>Develop and integrate test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals.</li>\n<li>Partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.</li>\n<li>Drive custom SLT development to optimize system performance, power efficiency, and test coverage.</li>\n<li>Oversee handler selection, enablement, and hardware integration – including PCB design, socket selection, and temperature control systems.</li>\n<li>Improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes.</li>\n<li>Collaborate closely with OSATs on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.</li>\n<li>Support silicon qualification and reliability testing (HTOL, Burn in) at the system level.</li>\n</ul>\n<p><strong>What we need to see:</strong></p>\n<ul>\n<li>MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience).</li>\n<li>12+ years of experience in Systems level test, systems validation, and/or bench testing.</li>\n<li>Experience in new silicon bring up at the system level.</li>\n<li>Experience in driving SLT testing and deployment for HVM.</li>\n<li>Experience with testing and characterization of high power SOCs and High Speed I/Os.</li>\n<li>Knowledge of network topology and experience in network connectivity.</li>\n<li>Proficient in C#, C/C++, PERL, Python, .NET framework.</li>\n<li>Experience in Security provisioning and knowledge of fuse programming implementation.</li>\n</ul>\n<p>Widely considered to be one of the technology world&#39;s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/</p>\n<p>You will also be eligible for equity and benefits.</p>\n<p>Applications for this job will be accepted at least until March 13, 2026.</p>\n<p>This posting is for an existing vacancy.</p>\n<p>NVIDIA uses AI tools in its recruiting processes.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_00fdc4b4-f89","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-System-Level-Test-Engineer_JR2013156","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering","12+ years of experience in Systems level test, systems validation, and/or bench testing","Experience in new silicon bring up at the system level","Experience in driving SLT testing and deployment for HVM","Experience with testing and characterization of high power SOCs and High Speed I/Os"],"x-skills-preferred":["C#","C/C++","PERL","Python",".NET framework"],"datePosted":"2026-03-09T20:45:48.152Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering, 12+ years of experience in Systems level test, systems validation, and/or bench testing, Experience in new silicon bring up at the system level, Experience in driving SLT testing and deployment for HVM, Experience with testing and characterization of high power SOCs and High Speed I/Os, C#, C/C++, PERL, Python, .NET framework"}]}