At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide,and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Collaborate with experienced mixed-signal design and verification teams to develop and verify high-speed NRZ and PAM-based SerDes products.

Engage in dynamic PHY IP development, tackling challenging problems and adapting to constant technological advances.

Participate in initial and ongoing training led by top experts, gaining exposure to advanced digital and analog design methodologies.

Contribute to scripting and automation tasks to support design verification processes.

B.E./B.Tech in Electronics, Electrical, Instrumentation, or related fields.

Fresh graduates from the class of 2025 or 2026 only.

Not currently enrolled in any M-Tech programs or postgraduate diplomas.

Not employed in any full-time positions at any company (limited internship experience is acceptable).

Strong digital and analog design aptitude (Mandatory).

Experience with UVM RNM Verification Methodology.

Good communication skills and a collaborative mindset.

Preferred: Understanding of PLLs, ADCs, DACs, LDOs, DSP basics, and hands-on scripting in Perl, Python, Tcl, or shell.

Program Length: 12 months apprenticeship program.

Location: Bengaluru, India.

Working Model: In-office.

Full-Time/Part-Time: Full-Time.

Start Date: May/June 2026.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. You thrive in a collaborative environment and are excited to work closely with global teams on the latest technology nodes. You have a strong understanding of semiconductor device physics and digital design, and you possess a solid foundation in CMOS fundamentals. Your familiarity with Unix/Shell/Python/TCL is an added advantage, and you are eager to leverage these skills to contribute to innovative projects. Your attention to detail and problem-solving abilities make you an ideal candidate for this role.

What You’ll Be Doing:

Designing and developing physical IP such as SERDES, DDR, and/or Memory as part of the Logic Libraries team. Collaborating with global teams to implement and optimize layout designs on the latest technology nodes. Utilizing your understanding of CMOS fundamentals to ensure high-quality and efficient design processes. Employing Unix/Shell/Python/TCL scripting to automate and enhance design workflows. Conducting design reviews and providing feedback to improve overall design quality and performance. Staying updated with the latest industry trends and technological advancements to ensure cutting-edge designs.

The Impact You Will Have:

Contributing to the development of high-performance silicon chips that power a wide range of applications. Enhancing the efficiency and reliability of physical IP design processes. Supporting the advancement of semiconductor technology through innovative layout designs. Collaborating with global teams to achieve project milestones and deliver high-quality designs. Improving the overall performance and functionality of Synopsys' technology solutions. Driving the continuous technological innovation that shapes the future of the industry.

What You’ll Need:

BSEE with 3+ years or MSEE with 1+ years of relevant experience in ASIC or IP verification. Strong understanding of semiconductor device physics and digital design principles. Solid foundation in CMOS fundamentals. Experience with Unix/Shell scripting and familiarity with Python/TCL. Proficiency in layout design and development of physical IP. Ability to work collaboratively with global teams and communicate effectively.

Who You Are:

Detail-oriented with strong analytical and problem-solving skills. Innovative and eager to stay updated with industry trends and advancements. Collaborative team player with excellent communication skills. Proactive and able to manage multiple tasks effectively. Passionate about semiconductor technology and its applications.

The Team You’ll Be A Part Of:

You’ll join a high-performing, globally distributed IP team that is at the forefront of automotive safety and reliability innovation. The team collaborates closely with product development, quality assurance, and customer engineering groups to deliver world-class automotive IP solutions. Together, you’ll champion functional safety standards, drive continuous improvement, and support customers in deploying safe, reliable automotive products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Principal ASIC Digital Design Engineer, you are a trailblazer who thrives in dynamic environments and is passionate about pushing the boundaries of semiconductor technology. You bring a deep understanding of digital design methodologies, paired with a creative approach to problem-solving and a tenacious drive to deliver robust solutions.

You are not only technically proficient in RTL coding and digital verification, but you also bring a practical understanding of synthesis flows, DFT, and production testing. Your scripting skills in Shell, Perl, Python, and TCL enable you to automate tasks and streamline development workflows.

You will design and verify advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions. You will develop RTL code, model analog blocks, and craft complex system-level testbenches in Verilog to validate functionality and performance.

You will collaborate with Application Engineers, Analog, and P&R teams to resolve technical issues, provide customer support, and ensure successful product deployment. You will mentor junior engineers, foster knowledge sharing, and contribute to a culture of innovation and continuous improvement.

You will drive the development of next-generation SerDes solutions, powering high-speed data transmission in cutting-edge applications. You will enable customers to achieve superior performance and reliability in their semiconductor products through innovative digital design.

You will need a Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification. You must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required. You must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows. Scripting experience in Shell, Perl, Python, and TCL is a plus.

You will join a highly experienced mixed-signal design and verification team, focused on advancing the capabilities of PAM-based SerDes products. The team is comprised of digital and mixed-signal engineers who work collaboratively from specification development through prototype testing.

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We are seeking an experienced RTL designer to join our team in Ho Chi Minh City. As an RTL Design Sr Staff Engineer, you will be responsible for designing and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog. You will also collaborate with analog and mixed-signal teams, automate workflows with scripting languages, debug complex hardware issues in lab bring-up and validation, document specifications and processes, and drive improvements in design and DFT/DFM flows.

Delivering reliable, high-speed memory IP for next-gen platforms, supporting rapid customer time-to-market, enhancing testchip team capabilities and innovation, mentoring and sharing expertise with peers, ensuring product quality through robust verification, and promoting a collaborative, learning-focused culture are some of the key responsibilities of this role.

To be successful in this position, you should have 6+ years of experience in RTL design/verification (SystemVerilog/Verilog), experience with high-speed interfaces (DDR/HBM preferred), skill in scripting (Python, Perl, Tcl, Shell), knowledge of ASIC/IP flows and DFT/DFM, and experience debugging complex hardware issues.

As a clear communicator and team player, analytical, proactive, and adaptable, open to learning and mentoring, you will thrive in this role.

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Responsibilities:

• Design, implement, and maintain secure CI/CD pipelines for automating deployment, configuration, and testing processes.
• Integrate security into the release workflow and ensure that all CI-CD tools are compliant from security perspective
• Understand developer workflows and Build Systems to improve build times
• Partner with other engineering teams and develop scalable tools and infrastructure to develop, test, debug and release software quickly
• Design, develop and deliver distributed engineering build tools and platforms for a variety of codebase languages
• Help maintain the backend infrastructure that supports our Dev test environments
• Develop and improve instrumentation for monitoring and logging the health and availability of services
• Follow best practices for development
• Participate in code and system design reviews

Requirements:

• 5+ years of software development experience.
• In-depth knowledge of running/managing UNIX-like operating systems (we use Ubuntu).
• Experience with containerisation technologies (e.g., Docker, Kubernetes) and securing containerised environments.
• Knowledge of implementing security in CI/CD pipelines
• Experience of various FOSS tools for monitoring, graphing, capacity planning, and logging.
• Experience with Cloud Computing platforms like Amazon AWS, Google Cloud Platform, Heroku.
• Experience with IaaC tools like Ansible, Puppet, Terraform.
• Ability to analyse bottlenecks in architecture and quickly debug to reach resolution for issues
• Have an automation mindset and ability to reason and work with complex systems.
• Excellent communication and documentation skills

Good to have:

• You’re familiar with building and writing in one of the following languages: Python, Shell, Java, Clojure
• You’re familiar with either of IntelliJ, VSCode, Emacs IDE and can help developers with their IDEs
• Familiar with the Challenges of Testing
• Comfortable using CLI tools for achieving day-to-day tasks.
• Systematic problem-solving approach, coupled with excellent communication skills and a sense of ownership and drive
• Drive task to the finish line with high quality and on time
• Experience in Designing and building solutions that are highly scalable, fault tolerant and cost-effective

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Your responsibilities will include: Troubleshooting and resolving complex customer issues related to the Databricks Platform by analysing core component metrics and logs. Providing suggestions and best practice guidance for improving performance in customer-specific environments and providing product improvement feedback. Helping the support team with detailed troubleshooting guides and runbooks. Contributing to automation and tooling programs to make daily troubleshooting efficient. Partnering with the engineering team and spreading awareness of upcoming features and releases. Identifying and contributing supportability features back into the product. Demonstrating ownership and coordinating with engineering and escalation teams to achieve resolution of customer issues and requests. Participating in weekend and weekday on-call rotation.

We look for candidates with 12+ years of industry experience, expertise in scripting using Python or Shell, and comfort with black box troubleshooting. Experience with supporting Java, Scala or Python based applications, distributed big data computing environments, SQL-based database systems, Linux and network troubleshooting, and cloud services such as AWS, Azure or GCP is also required.

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Responsibilities

• Quickly adapt to a rapidly changing environment and learn new emerging networking technologies
• Design and deploy consistent large scale networks rapidly, leveraging automation
• Participate in peer reviews, design discussions, and architectural decisions
• Troubleshoot complex problems and support internal and external customers
• Share your knowledge and guide junior team members, fostering a culture of continuous learning and improvement
• Effectively collaborate across teams and areas of expertise

Requirements

• 7+ years of experience as a Network Engineer
• Experience managing Hyperscale Clos fabrics
• Networking OS Experience - Cumulus Linux, Sonic, Arista EOS, Junos, Cisco NX-OS
• Expertise with major routing protocols (BGP, ISIS, OSPF)
• Experience with encapsulation protocols (EVPN/VXLAN or Geneve)
• Experience automating configuration management (Ansible, SaltStack, home grown)
• Familiarity with scripting/programming (Shell, Python)
• Operational experience with Git
• Large scale network design, maintenance, and operations
• Experience leading complex projects as part of a team
• Deep understanding of TCP/IP
• Strong Linux skills

Nice-to-Haves

• College education in Computer Science, Electrical Engineering
• Certifications like CCNA, CCNP, JNCIA
• Experience with Kubernetes and CNIs (Calico, Cilium)

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.

Technical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.

You bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You’ll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Fostering technical excellence and knowledge sharing across the organization.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Directly impact customer success by providing guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You’ll Need:

• 8+ years of experience in Firmware, ASIC design, verification, system validation, and technical roles.
• Be results driven
• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
• In-depth knowledge of system-level validation for high-speed interface PHY
• Proven track record of working cross-functionally and driving issues to closure
• Knowledge of mixed-signal design
• Experience in working in cross-functional collaborations
• Be an excellent communicator and a beacon for change

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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The impact you will have is accelerating time-to-market for Synopsys customers through robust, automated design flows. You will elevate the quality, reliability, and scalability of EDA methodologies and toolchains across multiple projects and technology nodes. You will influence the roadmap and strategic direction of Synopsys' automation and methodology offerings. You will empower engineering teams with state-of-the-art tools, training, and support to maximize productivity and innovation. You will enhance collaboration between R&D, application engineers, and customers by standardizing best practices and methodologies. You will reduce engineering overhead and manual intervention through data-driven process improvements and automation.

You will need 10+ years of experience in EDA methodology, CAD automation, or semiconductor process development (analog, mixed-signal, or digital domains). You will have proven leadership, mentoring, and project management skills in a cross-functional engineering environment. You will have deep hands-on expertise with industry-standard EDA tools (e.g., Synopsys Custom Compiler, Cadence Virtuoso, Calibre, ICV, or similar). You will have strong programming and scripting skills in Python, Perl, TCL, Shell, SKILL, or related languages, with a focus on automation and tool integration.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.

A technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.

You bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You'll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Mentoring and coaching engineering teams, fostering technical excellence and knowledge sharing across the organization.
• Collaborating with cross-functional groups and customers to resolve challenges, ensure quality design, and meet aggressive project milestones.
• Driving continuous improvement in functional and performance testing on hardware and test-chips, and leading architectural refinements based on analysis.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Driving cross-team synergy, technical mentorship, and a culture of continuous learning and inclusivity.
• Directly impact customer success by providing expert guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You'll Need:

• 15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.

• Be results driven

• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.

• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.

• In-depth knowledge of system-level validation for high-speed interface PHY

• Proven track record of working cross-functionally and driving issues to closure

• Knowledge of mixed-signal design

• Experience in working in cross-functional collaborations

• Be an excellent communicator and a beacon for change

• Excellent debugging, analytical, and problem-solving skills

• Working knowledge of scripting in languages such as Python and/or Perl

• Good understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon

• Good interpersonal skills, ability & desire to work as a standout colleague

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

#LI-DP1

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness
• Time Away
• Family Support
• ESPP
• Retirement Plans
• Compensation

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We are looking for a Software Engineer – Developer Productivity to help improve the productivity of the entire engineering team. You will be responsible for everything from our build and testing automation, to the packaging and release of the final product.

Responsibilities

• Design, implement, and maintain secure CI/CD pipelines for automating deployment, configuration, and testing processes.
• Integrate security into the release workflow and ensure that all CI-CD tools are compliant from a security perspective.
• Understand developer workflows and build systems to improve build times.
• Partner with other engineering teams and develop scalable tools and infrastructure to develop, test, debug, and release software quickly.
• Design, develop, and deliver distributed engineering build tools and platforms for a variety of codebase languages.
• Help maintain the backend infrastructure that supports our Dev test environments.
• Develop and improve instrumentation for monitoring and logging the health and availability of services.
• Follow best practices for development.
• Participate in code and system design reviews.

Requirements

• 5+ years of software development experience.
• In-depth knowledge of running/managing UNIX-like operating systems (we use Ubuntu).
• Experience with containerisation technologies (e.g., Docker, Kubernetes) and securing containerised environments.
• Knowledge of implementing security in CI/CD pipelines.
• Experience of various FOSS tools for monitoring, graphing, capacity planning, and logging.
• Experience with Cloud Computing platforms like Amazon AWS, Google Cloud Platform, Heroku.
• Experience with IaaC tools like Ansible, Puppet, Terraform.
• Ability to analyse bottlenecks in architecture and quickly debug to reach resolution for issues.
• Have an automation mindset and ability to reason and work with complex systems.
• Excellent communication and documentation skills

Good to Have

• Familiarity with building and writing in one of the following languages: Python, Shell, Java, Clojure.
• Familiarity with either of IntelliJ, VSCode, Emacs IDE and can help developers with their IDEs.
• Familiarity with the challenges of testing.
• Comfortable using CLI tools for achieving day-to-day tasks.
• Systematic problem-solving approach, coupled with excellent communication skills and a sense of ownership and drive.
• Drive task to the finish line with high quality and on time.
• Experience in designing and building solutions that are highly scalable, fault-tolerant, and cost-effective.

Benefits

• Hybrid setup.
• Worker's insurance.
• Paid Time Offs.
• Other employee benefits to be discussed by our Talent Acquisition team in India.

Helpshift embraces diversity. We are proud to be an equal opportunity workplace and do not discriminate on the basis of sex, race, color, age, sexual orientation, gender identity, religion, national origin, citizenship, marital status, veteran status, or disability status.

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Datacenter Networking Technician, AI Compute Deployment - Stargate

Location

Remote - US

Employment Type

Full time

Location Type

Remote

Department

Scaling

Compensation

• $86.4K – $228K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI, in close collaboration with our capital partners, is embarking on a journey to build the world’s most advanced AI infrastructure ecosystem. Our Stargate program develops and deploys massive, state-of-the-art data center campuses in partnership with industry leaders today—and through future OpenAI infrastructure projects tomorrow. We design for scale, speed, and reliability, and we need experienced technicians who can translate network blueprints into physical reality.

About the Role:

We are seeking a Senior Data Center Networking Technician who thrives in fast-moving build environments and is eager to roll up their sleeves during active datacenter deployments.

Your first assignment will focus on the physical bring-up of network infrastructure at a large partner-operated campus, collaborating with partner teams and their delivery vendors to achieve agreed performance and reliability targets. As that campus reaches steady state, you will transition to lead network deployment for future OpenAI data center projects, defining standards and guiding implementation across multiple locations.

_Candidates must be able to sit onsite in Abilene, Texas 5 days per week_

In this role you will:

• Serve as OpenAI’s technical lead technician during the current campus build, partnering with internal engineers and external contractors on design reviews, installation plans, and acceptance criteria.

• Spend significant time on the data-center floor performing inspections, assisting with cable routing/termination when needed, conducting fiber testing (OTDR, power levels, continuity), and resolving installation challenges in real time.

• Troubleshoot and optimize cabling routes, patching, and equipment turn-up to ensure clean, reliable handoff to network operations.

• Contribute to design discussions and peer reviews for structured cabling and physical network layouts, providing practical field feedback to engineering teams.

• Develop repeatable engineering standards, as-built documentation, and deployment playbooks to accelerate future OpenAI campuses

• Transition to hands-on design and deployment leadership for upcoming OpenAI data center expansions, owning network physical-layer deployment from design through commissioning.

You might thrive in this role if you:

• Have 7+ years of experience in large-scale datacenter network deployment, structured cabling, or physical-layer installation.

• Possess deep knowledge of fiber/copper plant design, cabling standards, and hyperscale network best practices.

• Excel in field work while applying seasoned technical judgment to solve complex installation and testing issues.

• Adapt quickly to changing build conditions and enjoy learning emerging networking technologies.

• Communicate clearly with construction, engineering, and operations teams to drive projects to completion.

• Are willing to be based at a partner campus during the initial build phase and to travel to future OpenAI data center projects.

Preferred Skills:

• Exposure to automation tools (Ansible, SaltStack) or scripting (Python, Shell) for configuration or documentation.

• Experience with hyperscale Clos fabrics or large-scale network design.

• Familiarity with routing and switching concepts (BGP, OSPF, EVPN/VXLAN) and basic Linux/network troubleshooting.

• Industry certifications such as BICSI, CCNA/CCNP, or equivalent.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we are building a team of talented individuals who share our values and are passionate about making a positive impact on the world.

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San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Consumer Products

Compensation

• $293K – $325K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

The Connectivity Software Engineering team is responsible for enabling seamless, secure, and high-performance wireless connectivity across OpenAI’s products. We design and optimize Bluetooth, BLE, Wi-Fi, and emerging wireless technologies to ensure robust device pairing, network performance, and interoperability. Our work spans kernel drivers, system services, and user-level tools, with a focus on real-world performance, scalability, and reliability.

About the Role

OpenAI is seeking a Connectivity Software Engineer to design, implement, and optimize wireless connectivity features across our product ecosystem. You’ll work at the intersection of systems software, wireless standards, and hardware integration—building robust pairing and provisioning flows, debugging low-level protocols, and driving performance under real-world RF constraints. You will also support certification, field interoperability, and fleet-scale connectivity infrastructure.

This role is based in San Francisco, CA. We use a hybrid work model of 4 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Design, implement, and debug Bluetooth/BLE and Wi-Fi features across kernel drivers, BlueZ/wpa\_supplicant/hostapd, and systemd/D-Bus services

• Deliver robust pairing, bonding, and provisioning flows (GATT/GAP, LE Audio/LC3, WPA3/802.1X, captive portals, NAN)

• Optimize link performance: throughput, latency, jitter, roaming, coexistence (BT↔Wi-Fi), and power modes (TWT, WoWLAN)

• Build reliable network management using NetworkManager/nmcli, nl80211/cfg80211/mac80211, DNS/DHCP/mDNS, P2P/SoftAP

• Instrument and analyze with packet captures and tooling (btmon/hcidump, Wireshark, iperf, eBPF/perf, spectrum sniffers)

• Drive interoperability and certification readiness (Bluetooth SIG, Wi-Fi Alliance) and resolve field issues with root-cause fixes

• Contribute to OTA-safe configuration, telemetry, and diagnostics for fleet-scale operation

You might thrive in this role if you:

• Have deep experience shipping wireless features on Linux-based products

• Are highly proficient in C/C++ with scripting experience (Python or shell) and systems debugging (gdb, strace, logs, packet traces)

• Possess deep knowledge of Bluetooth Classic/BLE (HCI, L2CAP, GATT/GAP, profiles) and Wi-Fi (802.11 a/b/g/n/ac/ax, WPA2/3, nl80211, NAN)

• Bring hands-on experience with BlueZ, wpa\_supplicant/hostapd, NetworkManager, and driver bring-up on ARM64 or x86 platforms

• Have a proven track record of improving real-world performance and reliability under RF constraints

Preferred qualifications:

• Experience with LE Audio (LC3), BLE Mesh, advanced roaming (802.11k/v/r), QoS/WMM, multicast/IGMP

• Coexistence tuning across radios (BT/Wi-Fi/UWB/mmWave) and antenna/RF fundamentals with test equipment workflows

• Familiarity with UWB (IEEE 802.15.4z, FiRa) ranging/integration; mmWave/Wi-Gig (802.11ad/ay)

• Experience with security and provisioning at scale (EAP-TLS, device identity, secure boot, disk/network hardening)

• Background in building factory test, interoperability, and certification test plans; upstream/open-source contributions

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

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What you'll do

You will play a key role in designing, maintaining, and scaling our Kubernetes-based infrastructure, supporting mission-critical applications, and automating operational workflows in a secure and resilient environment.

• Administer and maintain on-prem Kubernetes clusters, including installation, upgrades, patching, and monitoring.
• Automate infrastructure provisioning and configuration management using ArgoCD.
• Troubleshoot system, container, and network-level issues across distributed environments.

What you need

• Proven hands-on experience managing on-premises Kubernetes environments (kubeadm, containerd, etc.).
• Strong experience with ArgoCD for GitOps workflows and continuous delivery.
• Strong knowledge of observability and monitoring stacks, including Grafana Alloy, Prometheus, metrics pipelines, and alerting.

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