We're seeking an experienced Protection Relay Engineer/Specialist to join our Memphis team. This role will focus on the design, configuration, commissioning, and support of SEL-based protection and automation systems for high-reliability power infrastructure supporting our AI compute facilities.
\nResponsibilities:
\nBasic Qualifications:
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","url":"https://yubhub.co/jobs/job_5f6e02d7-438","directApply":true,"hiringOrganization":{"@type":"Organization","name":"xAI","sameAs":"https://www.xai.com/","logo":"https://logos.yubhub.co/xai.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/xai/jobs/4965890007","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["acSELerator QuickSet","SEL Grid Configurator","acSELerator Architect","IEC 61131-3 languages","SEL Logic Engine","DNP3","Modbus","IEC 61850 GOOSE/MMS","SEL protocols","Ethernet","serial interfaces","factory acceptance testing","site acceptance testing","relay setting validation","end-to-end functional verification","comprehensive documentation","one-line diagrams","logic diagrams","setting files","HMI screens","commissioning reports","technical support","system energization","troubleshooting","post-commissioning maintenance","project managers","SCADA engineers","field crews","schedule compliance","SEL firmware updates","NERC CIP cybersecurity requirements","industry best practices"],"x-skills-preferred":[],"datePosted":"2026-04-18T15:49:02.628Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Memphis, TN"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"acSELerator QuickSet, SEL Grid Configurator, acSELerator Architect, IEC 61131-3 languages, SEL Logic Engine, DNP3, Modbus, IEC 61850 GOOSE/MMS, SEL protocols, Ethernet, serial interfaces, factory acceptance testing, site acceptance testing, relay setting validation, end-to-end functional verification, comprehensive documentation, one-line diagrams, logic diagrams, setting files, HMI screens, commissioning reports, technical support, system energization, troubleshooting, post-commissioning maintenance, project managers, SCADA engineers, field crews, schedule compliance, SEL firmware updates, NERC CIP cybersecurity requirements, industry best practices"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fa0d2d73-870"},"title":"Senior Electrical Engineer - RF Systems","description":"Saronic Technologies is seeking a Senior Electrical Engineer specializing in Radio Frequency (RF) systems to join our Electrical Engineering – Advanced Development group. This role will focus on the research, evaluation, and integration of RF communications and sensing technologies - including radio transceivers, radar systems, antennas, and related electronics - supporting autonomous vessel networks and situational awareness.
\nThe ideal candidate has extensive experience in RF system design, testing, and benchmarking, with a strong foundation in wireless communications, spectrum management, and signal propagation in marine environments. This is a technically demanding, research-focused position with opportunities to influence system architecture and future platform capabilities.
\nKey Responsibilities:
\nRequired Qualifications:
\nPhysical Requirements:
\nBenefits:
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_fa0d2d73-870","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Saronic Technologies","sameAs":"https://www.saronictechnologies.com","logo":"https://logos.yubhub.co/saronictechnologies.com.png"},"x-apply-url":"https://jobs.lever.co/saronic/bde456c8-3965-49dd-ad74-6b34af89c16c","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Radio Frequency (RF) systems","RF system design","RF testing","RF benchmarking","Wireless communications","Spectrum management","Signal propagation","Marine environments","Autonomous vessel networks","Situational awareness","Radar systems","Antennas","Related electronics","RF instrumentation","Spectrum analyzers","Network analyzers","Signal generators","Power meters","Communications protocols","Ethernet","CAN","Serial interfaces","Wireless standards","LTE","SATCOM","Mesh networking"],"x-skills-preferred":[],"datePosted":"2026-04-17T12:58:01.992Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Radio Frequency (RF) systems, RF system design, RF testing, RF benchmarking, Wireless communications, Spectrum management, Signal propagation, Marine environments, Autonomous vessel networks, Situational awareness, Radar systems, Antennas, Related electronics, RF instrumentation, Spectrum analyzers, Network analyzers, Signal generators, Power meters, Communications protocols, Ethernet, CAN, Serial interfaces, Wireless standards, LTE, SATCOM, Mesh networking"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ae1562a1-6be"},"title":"Senior FPGA Architect","description":"Rigetti is seeking a Senior FPGA Architect to join the development of FPGA-based control hardware used to drive our quantum processors.
\nIn this role, you will define FPGA architectures, implement high-performance digital logic, and collaborate closely with hardware, firmware, and quantum engineering teams to build scalable, low-latency control systems.
\nKey responsibilities include:\nDeveloping and improving a custom microprocessor responsible for waveform generation and critical logic to operate a quantum computer\nWorking closely with hardware, firmware, and software teams to define architecture, data flow, and interfaces\nImplementing, simulating, and verifying designs including DSP pipelines, control logic, and high-speed I/O\nOptimizing designs for latency, resource utilization, and robustness in production environments\nDeveloping and maintaining testbenches, verification flows, and CI\nSupporting bring-up, lab validation, and debugging in collaboration with Quantum Engineering on actual quantum computers\nContributing to the long-term roadmap for the architecture of Rigetti’s control systems.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_ae1562a1-6be","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Rigetti Computing","sameAs":"https://www.rigetti.com","logo":"https://logos.yubhub.co/rigetti.com.png"},"x-apply-url":"https://jobs.lever.co/rigetti/efc17b70-a451-4aeb-8a37-70cb7201693b","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","VHDL","FPGA design","Digital signal processing","High-speed serial interfaces","Processor architecture design","Collaboration on cross-functional teams"],"x-skills-preferred":["RF/microwave or mixed-signal systems","ASIC design","Real-time control systems","Data acquisition","Instrumentation","Quantum computing","Test and measurement equipment","Scientific Python stack"],"datePosted":"2026-04-17T12:54:29.986Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, VHDL, FPGA design, Digital signal processing, High-speed serial interfaces, Processor architecture design, Collaboration on cross-functional teams, RF/microwave or mixed-signal systems, ASIC design, Real-time control systems, Data acquisition, Instrumentation, Quantum computing, Test and measurement equipment, Scientific Python stack"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ec579fde-89b"},"title":"R&D Engineering, Architect- FPGA Design-PCIe Protocol","description":"You are a visionary engineering leader with deep expertise in FPGA design and advanced protocol integration, ready to architect and deliver solutions that bridge real-world interfaces with cutting-edge emulation and prototyping platforms.
\nDesigning, developing, and maintaining Speed Adapter solutions for advanced protocols, including PCIe and CXL.\nImplementing protocol functionality on FPGA-based platforms to bridge real-world I/O with DUTs running at reduced speeds on emulation and prototyping systems.\nCollaborating with IP, emulation, and prototyping teams to deliver comprehensive, end-to-end system-level validation solutions.\nDeveloping and debugging RTL, firmware, and system-level components for Speed Adapter products.\nSupporting seamless integration with ZeBu and HAPS platforms, including creating example designs and reference flows.\nParticipating in customer escalations, conducting root-cause analysis, and delivering solutions for complex system-level issues.\nContributing to roadmap planning, feature definition, and technical differentiation versus competitive solutions.
\nEnable customers to connect pre-silicon designs to real devices, testers, and hosts with unmatched fidelity and performance.\nAdvance industry-leading system-level validation technology for top semiconductor and hyperscale customers.\nShape the adoption and implementation of next-generation protocols such as PCIe Gen6/Gen7 and CXL3.x/4.0.\nDrive innovation in hardware-assisted verification, influencing patent-pending technologies that differentiate Synopsys solutions.\nEnhance integration across IP, emulation, prototyping, and real-world connectivity to deliver robust validation platforms.\nSupport global teams and customers, fostering technical excellence and collaborative problem-solving.
\n12 years+ relevant experience\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.\nStrong hands-on experience with PCIe and/or CXL protocols, including implementation and debugging.\nSolid understanding of digital design, RTL development, and FPGA-based systems.\nExperience with system-level validation, emulation, or prototyping environments.\nFamiliarity with high-speed serial interfaces and real-world I/O connectivity.\nStrong debugging skills across RTL, firmware, and hardware/software boundaries.\nAbility to work effectively in a cross-geography, cross-functional team.
\nInnovative thinker with a strategic mindset.\nCollaborative team player who values diverse perspectives.\nExcellent communicator and technical mentor.\nResilient problem-solver, able to navigate ambiguity and complexity.\nCustomer-focused, with a commitment to delivering high-impact solutions.\nAdaptable and proactive, eager to stay ahead in a fast-evolving technology landscape.
\nYou'll join the Speed Adapter engineering team within Synopsys' HW-Assisted Verification (HAV) organization.\nThis talented group is dedicated to developing and deploying industry-leading Speed Adapter solutions that bridge advanced protocols and real-world interfaces with ZeBu emulation and HAPS prototyping platforms.\nThe team collaborates globally across IP, emulation, and prototyping domains to deliver robust, high-performance system validation solutions, directly impacting the success of top semiconductor and hyperscale customers.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.\nOur total rewards include both monetary and non-monetary offerings.\nYour recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work.\nSynopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses.\nSynopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.\nThe actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.\nYour recruiter can share more specific details on the total rewards package upon request.
\nAt Synopsys, innovation is driven by our incredible team around the world.\nWe feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.\nWe're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_ec579fde-89b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-architect-fpga-design-pcie-protocol/44408/92655118112","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$208,000 - $312,000","x-skills-required":["FPGA design","Advanced protocol integration","PCIe and CXL protocols","Digital design","RTL development","System-level validation","Emulation and prototyping environments","High-speed serial interfaces","Real-world I/O connectivity","Debugging skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:28.918Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"FPGA design, Advanced protocol integration, PCIe and CXL protocols, Digital design, RTL development, System-level validation, Emulation and prototyping environments, High-speed serial interfaces, Real-world I/O connectivity, Debugging skills","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":208000,"maxValue":312000,"unitText":"YEAR"}}}]}