As a Senior Circuit Designer, you will be responsible for designing embedded electronics from concept to functional prototype, including hardware selection, schematic & PCB design, board bring-up, and system level integration.

You will work closely with firmware/software engineers for processor/peripheral selection, board bring up, and troubleshooting.

You will also work in a fast-paced environment supporting new developments, active deployments, and customer operated hardware.

Concurrently, you will manage involvement in multiple projects at various stages.

Required qualifications include a Bachelor’s Degree in Electrical Engineering and 10+ years of experience designing, testing, and troubleshooting complex hardware, embedded systems, and products.

Experience with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C is also required.

Additionally, you should have experience with microprocessor and microcontroller selection, configuration, and interfacing, as well as competence with test equipment such as oscilloscopes, logic analyzers, debuggers, current-probes, and automation of tests.

Exceptional organization and communication skills are also necessary.

Salary range: $146,000-$194,000 USD.

Benefits include comprehensive medical, dental, and vision plans, income protection, generous time off, family planning & parenting support, mental health resources, professional development, commuter benefits, relocation assistance, and a retirement savings plan.

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In this role, you will work closely with an interdisciplinary technical team to route high-speed mixed-signal designs, interact with fabricators and assemblers, and manage signal integrity in complex PCBs.

Key responsibilities include:

• Working directly with engineers to produce printed circuit board designs supporting Anduril's products.
• Applying modern design standards and guidelines to create high-reliability, highly manufacturable assemblies.
• Implementing combinations of high-speed digital, precision analog, RF, and high-power designs.
• Leading the team in establishing internal guidelines for design for manufacturing (DFM), design for assembly (DFA), and overall quality fabrication and assembly outputs.
• Developing and refining team processes for PCB design, part creation, and library/database standards.
• Coordinating external PCB design resources during design surges.

Required qualifications include:

• A bachelor's degree in electrical engineering or similar and 5+ years of professional experience in PCB design OR 10+ years of professional experience in PCB design.
• Ability to read and interpret schematics and apply best practices appropriate for each design.
• Expertise in applying relevant IPC standards, CID, CID+ certification.
• Expertise in PCB fabrication processes, limitations, design rules, and best practice.
• Experience using Altium Designer CAD tools (Allegro is a plus).
• Experience with developing component libraries and library management.
• Excellent communication skills with multiple fab houses (ensuring boards are built to print).
• Excellent communication skills with multiple assembly houses (ensuring boards are built to BOM).
• Experience with a variety of board types, including high density and high layer count (greater than 16) digital designs, power electronics, flex circuits, and RF circuits.
• Experience with HDI (high density interconnect) and thicker boards (greater than 1.6mm).
• Experience with high speed digital interfaces and controlled impedance routing requirements like USB, PCIe, Ethernet, SERDES, and DDR memory.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred qualifications include:

• Familiarity with RF board design.
• Experience with high-pin count packages (FPGA fanout).
• Familiarity with basic signal and power integrity rules (how they affect layout).

US Salary Range $111,000-$147,000 USD

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This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms. You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centres, including our primary front and backend networks that train Grok and that customers use for inference.

Responsibilities:

• Design, validate, and productise high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).
• Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterisation.
• Investigate the opportunity for LPO and LRO in our network.
• Evaluate early co-packaged and near-packaged engines for switches and GPUs.
• Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.
• Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.
• Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.
• Perform system-level simulation of end-to-end fabric performance.
• Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
• Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.

Basic Qualifications:

• At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacentre environment.
• Master's or PhD degree in Electrical Engineering, Photonics or Physics.
• Deep knowledge of PAM4 SerDes performance, equalisation, jitter, crosstalk.
• Solid operational understanding of FEC, Retimers, TIAs and Drivers.
• Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.
• Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterisation.
• Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.
• Knowledge of SiPh design process, yield improvement and reliability testing.
• Familiarity with CPO technologies and challenges/risk areas.
• Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.
• Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.

Compensation and Benefits:

$180,000 - $440,000 USD

Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.

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We currently have 613 open roles

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a dedicated and detail-oriented engineer with a passion for unraveling the complexities of high-speed, mixed-signal circuits. You thrive in collaborative environments, working seamlessly with diverse teams to overcome technical challenges and achieve shared goals. Your strong theoretical foundation is complemented by extensive hands-on experience in silicon validation, and you excel in both designing and implementing test methodologies that push the boundaries of what’s possible.

You are adaptable and resourceful, eager to tackle new problems and continually expand your technical repertoire. Your curiosity drives you to stay up-to-date with the latest advancements in validation technologies, and you are comfortable navigating the fast-paced, ever-evolving landscape of semiconductor innovation. Whether you’re analyzing intricate data sets, designing custom test hardware, or troubleshooting in the lab, you approach each task with meticulous attention to detail and an unwavering commitment to quality and reliability.

You communicate effectively, translating complex technical findings into actionable insights for colleagues and customers alike. Your organizational skills ensure that your projects run smoothly from conception through to completion, and your enthusiasm for hands-on lab work is matched by your drive to mentor and share knowledge with others. If you’re eager to make a tangible impact on the next generation of high-speed silicon solutions, we want you on our team.

Collaborating with cross-functional teams,including analog and systems designers, applications engineers, and customers,to resolve technical challenges and demonstrate leading-edge product performance.

Analyzing and characterizing circuit behavior and limitations in both silicon validation and characterization environments.

Developing and executing comprehensive test plans to ensure products meet rigorous standards and protocol specifications.

Specifying, sourcing, and implementing advanced test equipment and components to support innovative test methodologies.

Generating detailed test reports, meticulously documenting results, methodologies, and recommendations for internal and external stakeholders.

Designing and developing custom test boards and hardware solutions to facilitate robust product validation and evaluation.

Debugging and troubleshooting electronic circuits, investigating and resolving product non-conformance issues to ensure top-tier quality.

Ensuring the delivery of high-performance, reliable silicon IP solutions that power next-generation technologies.

Driving continuous improvement in product quality and compliance with industry standards.

Accelerating time-to-market for cutting-edge mixed-signal IP by streamlining validation and verification processes.

Strengthening Synopsys’ reputation as an industry leader through exceptional technical execution and customer support.

Identifying and resolving critical bottlenecks in product development, leading to more robust and scalable solutions.

Contributing to a culture of innovation and knowledge sharing within the R&D team.

Master’s degree in Electrical or Electronics Engineering (or equivalent field).

Minimum 5 years of hands-on experience in post-silicon validation, lab instrumentation, characterization, and debug.

Strong knowledge of analog and mixed-signal circuit design and operation, including familiarity with ADC/DAC and SerDes architectures.

Proficiency in software programming (such as MatLab and Python) for test automation and comprehensive data analysis.

Demonstrated expertise in using advanced lab equipment (BERTs, oscilloscopes, VNAs, TDRs) for high-speed circuit validation.

Experience in schematic entry, PCB design, and layout as well as data analysis, data review, and data mining for test results.

Knowledge of signal integrity and power integrity principles, and familiarity with PAM-4 signaling test and debug.

An analytical thinker with a passion for hands-on problem solving and continuous learning.

Proactive, adaptable, and eager to take on new challenges in a fast-paced, innovative environment.

Excellent communicator, capable of conveying complex technical details to both technical and non-technical audiences.

Collaborative team player who thrives on cross-functional teamwork and knowledge sharing.

Detail-oriented, with a commitment to delivering high-quality results and driving process improvements.

You’ll join a high-performing R&D team based in Mississauga, renowned for its expertise in high-speed, mixed-signal IP development and validation. Our team is dedicated to technical excellence, continuous innovation, and collaborative problem-solving. Working closely with analog and systems designers, applications engineers, and customers, you’ll play a pivotal role in shaping the next generation of advanced silicon solutions. Our culture emphasizes mentorship, knowledge sharing, and professional growth, ensuring that every team member has the support and resources needed to thrive.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You will be a part of a fast-growing analog and mixed-signal R&D team, dedicated to developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You'll interact with a global, dynamic, multi-cultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

As a Staff Engineer, you will be responsible for:

Developing and/or validating analog circuits considering electrical specifications and reliability constraints. Documenting simulation results and analyzing performance. Evaluating the impact of parasitic effects related to layout implementations and working with the layout team to minimize such effects, improving performance, power, and area. Defining and planning analog design activities for high-speed SerDes products. Collaborating with a global team of engineers to integrate and verify design solutions. Continuously learning and applying the latest advancements in FinFET/GAA process nodes to enhance design efficiency.

You will contribute to the development of high-speed SerDes products that enable high-performance chip-to-chip communications. You will enhance the performance, power efficiency, and reliability of analog integrated circuits in advanced CMOS technologies. You will support the integration of more capabilities into System-on-Chip (SoC) designs, accelerating time-to-market for innovative products.

You will be a part of a dynamic, multicultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

The ideal candidate will have a good understanding of CMOS technologies and analog circuit design principles. They will have strong analysis, problem-solving, and organizational skills. They will have experience in analog and mixed-signal block design, with a focus on high-speed SERDES. They will be proficient in documenting and analyzing simulation results. They will be familiar with IC design packages and UNIX operating systems.

You will be a collaborative team player who thrives in a global, multicultural environment. You will be an effective communicator with strong written and verbal skills in English. You will be a proactive and self-motivated individual with a passion for innovation and continuous learning. You will be an analytical thinker with the ability to tackle complex design challenges and find creative solutions. You will be a detail-oriented engineer who values precision and accuracy in their work.

You will be rewarded with a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide,and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Internship Experience:

• Plan and execute system-level testing for PCIe6 and PCIe7 protocols, focusing on reproducing and debugging customer issues with SNPS PHY.
• Develop and maintain Python-based test scripts to automate validation processes.
• Utilize lab instrumentation to conduct hands-on experiments and gather critical data.
• Collaborate with engineering teams to report findings, discuss next steps, and contribute to solutions that directly impact customer satisfaction.
• Engage in creative problem-solving, proactively seeking new approaches to resolve complex technical challenges.

What You'll Need:

• Currently pursuing a master’s degree in Electronic Engineering, Computer Science, or a related field.
• Strong programming skills in Python,ability to develop and troubleshoot test automation scripts is essential.
• Previous experience with lab instrumentation and hands-on testing environments, is a plus.
• Familiarity with high-speed SerDes protocols such as PCIe.
• Proactive and persistent approach to problem-solving, with a curious mindset and eagerness to learn.
• Effective communication skills to clearly report findings and collaborate within a team.

Key Program Facts:

• Program Length: 6 months
• Location: Lagoas Park, Oeiras (Lisbon)
• Working Model: In-office
• Full-Time preferred
• Expected start Date: May timeframe preferred

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As a High-Speed Interface Digital Design Manager, you will be responsible for managing and mentoring engineers, fostering a culture of innovation, ownership, and continuous improvement. You will drive architecture specification, digital design, and verification activities for current and next-generation products, engaging with customers to manage escalations, facilitate pre- and post-sales discussions, and ensure their requirements are met.

Key responsibilities include:

• Leading a high-performing digital and verification engineering team focused on the design and delivery of advanced SerDes IP
• Managing and mentoring engineers, fostering a culture of innovation, ownership, and continuous improvement
• Driving architecture specification, digital design, and verification activities for current and next-generation products
• Engaging with customers to manage escalations, facilitate pre- and post-sales discussions, and ensure their requirements are met

Requirements include:

• Bachelor's or Master's degree in Electrical Engineering or related field
• 10+ years of hands-on digital design and verification experience in the semiconductor industry
• 5+ years of proven leadership and people management experience, preferably in ASIC or IP development environments
• Deep knowledge of the ASIC development flow, including architecture specification, digital design, and verification methodologies
• Experience with high-speed interface protocols (e.g., PCIe, Ethernet, USB) and digital signal processing techniques
• Expertise in managing customer escalations and facilitating technical discussions during pre- and post-sales phases
• Proficiency with industry-standard EDA tools, scripting, and project management platforms

Benefits include:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

If you are a strong leader with excellent team-building and mentoring skills, a customer-focused and results-oriented individual with sound decision-making abilities, a collaborative communicator able to build strong cross-functional alliances, organized, detail-oriented, and adept at managing multiple priorities efficiently, adaptable, proactive, and committed to continuous improvement, we encourage you to apply.

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As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.

Responsibilities:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

Requirements:

• Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.

Who You Are:

• Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.
• Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
• Collaborative team player who builds productive relationships and networks effectively.
• Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.
• Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.
• Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:

You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.

What You’ll Be Doing:

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.
• Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.
• Present technical results internally and externally to customers and industry groups.
• Oversee physical layout to address parasitics and reliability concerns.
• Document features and test plans, and support post-silicon analysis and updates.

The Impact You Will Have:

• Advance industry-leading SERDES IP for next-generation SoCs.
• Enhance product differentiation and customer value.
• Streamline design processes for quality and time-to-market.
• Mentor junior team members and share best practices.
• Influence technical direction and innovation at Synopsys.
• Support customer success and product reliability.

What You’ll Need:

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.
• Expertise in transistor-level CMOS design and SERDES sub-circuits.
• Proficiency with schematic, layout, and verification tools; SPICE simulators.
• Experience with scripting languages (Verilog-A, TCL, Python, etc.).
• Strong communication and documentation skills.

Who You Are:

• Technical leader and mentor
• Collaborative and proactive
• Analytical and detail-oriented
• Adaptable and innovative

The Team You’ll Be A Part Of:

A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.

What You’ll Be Doing:

• Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.

• Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.

• Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.

• Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.

• Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.

• Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.

The Impact You Will Have:

• Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.

• Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.

• Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.

• Drive advancements in deep submicron CMOS technology adoption and integration.

• Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.

• Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.

What You’ll Need:

• MSc in Electrical/Computer Engineering (or equivalent).

• Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.

• Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).

• Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.

• Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.

• Strong skills in UNIX environments, including shell scripting and command-line operations.

• Familiarity with scripting languages such as TCL and Python.

Who You Are:

• Excellent problem-solving, organizational, and communication skills.

• Self-motivated and proactive, with the ability to work independently and as part of a team.

• Effective collaborator who values diverse perspectives and fosters inclusive teamwork.

• Adaptable and open to new challenges, with a commitment to continuous improvement.

• Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.

The Team You’ll Be A Part Of:

You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking an experienced SerDes Analog Behavioral Modeling & Validation Engineer to join our team.

As a key member of our engineering team, you will be responsible for developing and refining behavioral models for high-speed SerDes blocks, collaborating with analog teams for SPICE-vs-model correlation and sign-off, and working with digital verification teams on edge-case coverage.

Responsibilities

• Collaborate with analog teams for SPICE-vs-model correlation and sign-off.
• Develop and refine behavioral models for high-speed SerDes blocks.
• Capture calibration, adaptation, and impairments in models.
• Work with digital verification teams on edge-case coverage.
• Automate comparison flows and improve model fidelity.
• Embed realistic non-idealities and verify behavioral netlists.

Impact

• Deliver high-trust models, reducing mixed-signal bugs.
• Enable realistic digital verification and improve coverage.
• Strengthen Synopsys' reputation for robust connectivity IP.
• Catch issues early and accelerate debug cycles.
• Foster collaboration between analog, modeling, and DV teams.

Requirements

• BSc, MSc, or PhD in Electrical/Computer Engineering with 5+ years experience.
• Expertise in SerDes analog blocks and modeling impairments.
• Fluency with SPICE tools and waveform analysis.
• Strong scripting/programming in Python, TCL, Perl, C/C++.
• Experience automating comparisons and reporting.

Team

You'll join a multidisciplinary group focused on modeling, validation, and verification of high-speed SerDes IP,bridging analog and digital domains for industry-leading solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are an expert in high-speed analog design, with hands-on experience in wireline or optical SerDes above 200GBaud. You excel with PLLs, ILOs, DLLs, and phase mixers, as well as transmitters, serializers, optical drivers, receiver analog front ends, TIAs, and data converters.

Designing advanced SerDes and clocking circuits for ultra-high-speed data. Developing transmitters, serializers, and optical drivers. Creating receiver analog front ends and TIAs. Optimizing signal integrity and power usage. Collaborating across global teams. Mentoring junior engineers.

Enable next-gen connectivity solutions. Strengthen Synopsys' technology leadership. Accelerate product innovation and time-to-market. Improve reliability and performance of industry-leading chips. Foster technical growth across teams. Influence industry standards.

Our ideal candidate has a BSEE with at least 8+ years of direct industry experience. They must have extensive analog/SerDes IC design experience above 200GBaud, expertise with PLLs, DLLs, ILOs, phase mixers, and related circuits, proficiency in EDA tools and advanced process technologies, strong signal integrity and layout skills, and lab validation and debugging experience.

Collaborative and proactive leader. Detail-oriented problem solver. Effective technical communicator. Innovative and curious. Supportive mentor.

Join an elite analog design team focused on high-speed connectivity and SerDes IP, collaborating globally to deliver breakthrough solutions.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are an experienced Analog Design Manager with a passion for high-speed SerDes technology. You have a proven track record in leading teams to develop cutting-edge analog integrated circuits. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP, combined with your strong leadership skills, enables you to guide a team through complex design challenges. You thrive in a collaborative environment, working alongside analog and digital designers from diverse backgrounds. Your technical proficiency is complemented by your ability to develop schedules and action plans that ensure project success. With excellent communication and documentation skills, you effectively present design activities and solutions to critical issues. You are committed to fostering an environment of continuous improvement and operational excellence.

What You’ll Be Doing:

Directing and guiding the activities of a team of analog designers developing high-speed SERDES IP. Conducting design reviews and evaluating the final results of simulation and electrical characterization reports. Presenting the results of design activities, technology assessments, or critical issue investigations and making recommendations for actions necessary to achieve desired results. Selecting, developing, and evaluating personnel to ensure the efficient operation of the team. Developing schedules and action plans to meet overall project timelines. Reviewing documented design features and test plans. Ensuring that the team follows processes and operational policies for maximum design quality. Consulting on the electrical characterization of the SerDes IP product and proposing solutions for post-silicon design updates.

What You’ll Need:

B.Tech/BE/M.Tech/MS in Electronics Engineering. 8+ years of experience in Analog Design for High-Speed SerDes applications. 3-5 years of experience in a management or supervisory role. In-depth familiarity with transistor level circuit design and sound CMOS design fundamentals. Detailed design experience with SerDes sub-circuits such as receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers,voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, and DAC, DSP, Signal Integrity Familiarity with both analog and digital circuits and issues related to interfacing and timing between them. Aware of ESD issues (i.e. circuit techniques, layout). Familiarity with custom digital design (i.e. highspeed logic paths). Knowledge of design for reliability (i.e. EM, IR, aging, etc.). Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.). Good communication and documentation skills.

The Impact You Will Have:

Driving the development of high-speed SerDes IP that meets industry standards and customer requirements. Fostering innovation and excellence within the analog design team. Ensuring the delivery of high-quality, reliable analog integrated circuits. Contributing to the advancement of Synopsys' technology portfolio in the analog and mixed-signal domains. Enhancing the performance and efficiency of our high-speed communication products. Supporting the growth and development of team members through effective leadership and mentorship.

Who You Are:

You are a proactive leader with a strong technical background in analog design. You possess excellent problem-solving skills and the ability to make sound decisions under pressure. Your collaborative nature allows you to work effectively with cross-functional teams. You are detail-oriented and have a keen eye for quality. Your passion for continuous learning and improvement drives you to stay updated with the latest industry trends and technologies. You are committed to fostering a positive and inclusive team culture, encouraging innovation and excellence.

The Team You’ll Be A Part Of:

You will be part of a fast-growing analog and mixed-signal R&D team developing high-speed analog integrated circuits in the latest FinFET process nodes. The team is composed of talented analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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ASIC/SoC Presales Applications Engineer - 16648

Sunnyvale, California, United States

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Category: EngineeringHire Type: Employee

Job ID 16648Base Salary Range $184000-$276000Date posted 03/31/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned ASIC, SoC, or Chiplet Architect, Manager, or Design Engineer, bringing extensive expertise in IC Digital, Mixed Signal, or Analog Design. Your technical prowess is matched by your ability to engage and inspire customers, translating complex engineering concepts into clear, impactful solutions. You thrive in fast-paced, dynamic environments and are adept at navigating competitive landscapes. Your organizational skills and self-motivation ensure you deliver on ambitious goals, while your creative approach to problem-solving enables you to overcome challenges with finesse. You build trust and rapport quickly, fostering long-lasting relationships with both internal teams and external stakeholders. With a Bachelor’s (15+ years) or Master’s (11+ years) degree in a relevant field, you understand industry protocols such as SerDes, UCIe, PCIe, DDR, USB, MIPI, or Ethernet, bringing added value to each engagement. You are passionate about driving technology forward and contributing to customer success, ready to make a significant impact at Synopsys.

What You’ll Be Doing:

• Presenting Synopsys solutions to senior managers and technical stakeholders, showcasing the value and capabilities of our IP portfolio.

• Engaging with customers to understand their unique requirements and challenges, proposing tailored technical solutions that meet their needs.

• Positioning Synopsys competitively in technical discussions, articulating differentiators and advantages in the marketplace.

• Liaising between technical, marketing, and sales teams to ensure seamless communication and alignment on project objectives.

• Driving strategy and execution for technical solution design, influencing customer architectures and product adoption.

• Supporting sales and business unit negotiations with expert insight into technical feasibility, solution fit, and value proposition.

The Impact You Will Have:

• Lead customer engagements, ensuring Synopsys solutions align perfectly with client requirements and goals.

• Collaborate across global teams to deliver innovative, winning solutions that drive business growth.

• Accelerate adoption of Synopsys products and platforms within key customer accounts.

• Provide critical technical insight, shaping the design and success of customer chip projects.

• Drive customer and business success by enabling efficient, high-performance SoC and ASIC design.

• Ensure successful delivery of complex SoC projects across multiple regions, supporting Synopsys' reputation as a market leader.

What You’ll Need:

• Deep expertise in IC design, including Digital, Mixed Signal, or Analog domains.

• Experience in customer-facing roles, technical sales, or sales support within the semiconductor industry.

• Exceptional communication skills, able to convey complex technical concepts to diverse audiences.

• Strong organizational and project management abilities, driving multiple projects to completion.

• Solid understanding of major semiconductor IP product lines and industry protocols (SerDes, UCIe, PCIe, DDR, USB, MIPI, Ethernet).

Who You Are:

A creative problem solver and strategic thinker, you excel at collaborating with diverse teams and stakeholders. You are driven by a passion for technology, innovation, and customer success, bringing a positive, solutions-oriented mindset to every challenge. Your adaptability and leadership enable you to thrive in high-pressure situations, while your integrity and commitment build trust across all levels of the organization.

The Team You’ll Be A Part Of:

You’ll join a collaborative group dedicated to delivering groundbreaking chip design solutions using Synopsys IP. The team works closely with Sales, R&D, and Marketing, fostering a supportive and innovative environment where your ideas and expertise will help shape next-generation semiconductor products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.

In addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.

You will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.

Finally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.

To be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.

Additionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.

If you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

Get an idea of what your daily routine around the office can be like

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15391

Remote Eligible

No

Date Posted

02/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.

You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.

Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.

What You’ll Be Doing:

• Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

• Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

• Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

• Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

• Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

• Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.

• Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.

The Impact You Will Have:

• Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.

• Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.

• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.

• Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.

• Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.

• Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.

What You’ll Need:

• MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

• Proven expertise with FinFET technologies and CMOS tape-outs.

• Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

• Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

• Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

• Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

• Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

• Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

• Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

• Excellent communication and documentation skills.

Who You Are:

• Collaborative and open-minded, eager to share knowledge and learn from others.

• Detail-oriented and thorough, with a commitment to delivering high-quality results.

• Analytical thinker with strong problem-solving abilities and a proactive approach.

• Excellent communicator, able to convey complex technical concepts clearly.

• Adaptable and resilient in fast-paced, dynamic environments.

• Committed to fostering an inclusive, innovative, and supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and patern

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You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.

What You’ll Be Doing:

• Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.
• Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.
• Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.
• Collaborating with R&D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.
• Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.

The Impact You Will Have:

• Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.
• Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.
• Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.
• Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.
• Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.
• Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design

What You’ll Need:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.
• Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.
• 7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.
• Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).
• Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.
• Experience in Unix/Linux development environments.

Who You Are:

• Collaborative team player with excellent communication skills and a global mindset.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.
• Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.
• Adaptable and eager to stay updated with the latest industry trends and technologies.
• Customer-focused, with a dedication to supporting and enabling client success.

The Team You’ll Be A Part Of:

You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Lead system signal integrity (SI) design for AI supercomputer product in the data center application.

• Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies

• Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity

• Perform simulation and modeling to identify and troubleshoot signal integrity issues

• Lead system interconnect design, bring up and qualification

• As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.

You might thrive in this role if you:

• Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications

• Have a strong bias toward action, and won’t take no for an answer.

• Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level

• Have experience with PCB, connector and cable design

• Have a strong intrinsic desire to learn and fill in missing skills; and an equally strong talent for sharing that information clearly and concisely with others.

• Are comfortable with ambiguity and rapidly changing conditions.

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What you'll do

• Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
• Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

What you need

• Bachelor's and/or masters with a minimum 10+yrs of Industry experience or equivalent
• At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)
• Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure
• Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB

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What you'll do

You will be responsible for developing analog sub-block specs based on SerDes standards, refining circuit architectures for optimal power, area, and performance, designing and verifying circuits using advanced simulation tools, collaborating on physical layout to minimize parasitics and variation, presenting simulation data to peers and customers, and documenting design features and test plans.

What you need

• MSc with 5+ years in analog IC design

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What you'll do

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.

What you need

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.

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What you'll do

• Reviewing and interpreting SerDes standards to define, develop, and refine innovative transceiver architectures and detailed analog sub-block specifications for high-speed Multi-Gbps NRZ & PAM4 SerDes IP.
• Investigating and architecting advanced circuit solutions that address performance bottlenecks, driving significant improvements in power, area, and speed while ensuring robust and reliable silicon performance.

What you need

• Strong understanding of analog circuit design and verification techniques.
• Experience with high-speed SerDes IP development and advanced process nodes such as FinFET and gate-all-around technologies.

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What you'll do

• Interpreting SerDes standards and digital, analog, and firmware architecture documents to develop verification environments and regression testcases in MATLAB;
• Evaluating and troubleshooting digital and mixed-signal circuits to ensure optimal performance and resolve complex design challenges;
• Collaborating with digital, firmware, and analog teams to solve verification challenges and improve design methodologies;
• Adapting and debugging internal verification environments to effectively replicate challenging scenarios;
• Identifying and implementing process improvements to enhance efficiency in design procedures and methodologies;
• Documenting verification environments, plans, and procedures to ensure clear communication and knowledge sharing across teams.

What you need

• 6-10 years of hands-on experience in FPGA design and verification, with a focus on IP-level functional verification;
• Proficiency in Verilog and MATLAB for digital design, verification, and FPGA prototyping with logical synthesis flows;
• Strong programming and scripting skills for test automation and data analytics (Python, C/C++, TCL);
• Strong understanding of digital and mixed-signal circuit evaluation, troubleshooting, and performance optimization techniques;
• Ability to interpret and apply digital architecture and SerDes standards documentation to develop robust verification solutions;
• Excellent technical documentation skills to ensure clear communication and knowledge transfer.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Leading silicon validation of IP functionality and performance, ensuring alignment with architectural intent.
• Supporting hardware bring-up and firmware integration for early product-version characterization.

What you need

• BSc or MSc in Electrical or Computer Engineering.
• 10+ years of experience in silicon validation, high-speed interfaces, and system-level performance analysis.

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What you'll do

• Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
• Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.

What you need

• 5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.
• Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.
• Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).
• Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.

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What you'll do

• Leading PHY protocol assessment work, translating standard requirements into PHY block level specifications and verification methodologies.
• Collaborating closely with design teams to conduct rapid studies, evaluate solutions, and assess tradeoffs for design issues.

What you need

• Master’s degree in Electronic Engineering or related field.
• Minimum 8 years of experience in SerDes design, communications protocols, or related technical roles.

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What you'll do

• Reviewing SerDes standards and architecture documents to develop comprehensive analog sub-block specifications.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Proposing and executing design and verification strategies that leverage advanced simulator features for highest-quality design outcomes.

What you need

• BS/BTech degree and 5+ years of experience in IC design, or MS/MTech with 3+ years of experience or PhD degree in a related field.
• In-depth familiarity with transistor-level circuit design and solid CMOS fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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What you'll do

We are seeking a highly experienced Architect specializing in high‑speed SerDes design with deep expertise in advanced analog/mixed‑signal circuits, XSR (Extra‑Short‑Reach) interfaces, and optical I/O technologies.

What you need

• 15+ years of experience in analog/mixed‑signal circuit design, SerDes PHYs, or related high‑speed I/O.

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What you'll do

Review SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

Investigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

Collaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

Oversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

Present and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

Document design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.

Analyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.

What you need

MTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

Proven expertise with FinFET technologies and CMOS tape-outs.

Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

Excellent communication and documentation skills.

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What you'll do

You are an accomplished analog and mixed-signal design engineer, passionate about pushing the boundaries of high-speed interface technology. With a strong foundation in Electrical, Electronics, or VLSI Engineering, you have hands-on expertise in custom analog circuit design, particularly in the nanometer CMOS domain.

• Designing and developing high-speed analog and mixed-signal (AMS) circuit macros, including analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, CDR circuits, and injection-locked loops for High-Speed PHY IP in planar and FinFET CMOS technologies.

What you need

• Bachelor’s degree (BE) plus 3+ years or Master’s degree (MTech) plus 2+ years of relevant experience in mixed-signal analog/custom circuit design, preferably in Electrical/Electronics/VLSI Engineering.

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What you'll do

Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.

• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.

What you need

• Collaborating with cross-functional teams including analog, digital, and layout engineers.

Why this matters

As a trusted leader in the analog design community, your attention to detail, ownership mindset, and commitment to quality position you for success.

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What you'll do

Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data.

• Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator).

What you need

BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience.

• Advanced proficiency in RNM, mixed-signal verification, and high-speed SerDes design.

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