The role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.

The impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.

To be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).

You will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.

Join a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a passionate and detail-oriented engineering professional who thrives in collaborative environments and enjoys working at the intersection of technology and customer engagement. You possess a deep understanding of VLSI and Design for Testability (DFT) methodologies, and you are eager to use your expertise to drive innovation in semiconductor design.

Collaborating with leading semiconductor design companies to understand their engineering methodologies and unique challenges. Partnering with Account and R&D teams to develop, implement, and optimize stable and scalable tool solutions tailored to customer needs. Gathering and refining technical requirements, providing regular updates, and ensuring alignment across cross-functional teams. Applying advanced Design for Testability (DFT) concepts, including scan insertion, to enhance the reliability and manufacturability of customer designs. Delivering impactful presentations and hands-on demonstrations to customers, highlighting the value and capabilities of Synopsys solutions. Monitoring industry developments and integrating the latest advancements into customer engagements and tool methodologies. Automating workflows and customizing solutions using scripting languages such as TCL, Python, or Perl.

Empowering semiconductor companies to streamline their design processes and achieve higher quality outcomes. Driving customer satisfaction by delivering robust, scalable, and innovative solutions that address real-world engineering challenges. Enhancing the adoption and effectiveness of Synopsys toolsets through expert guidance and technical support. Contributing to the evolution of industry best practices in Design for Testability and automation. Facilitating strong partnerships between Synopsys and its customers, fostering long-term collaboration and success. Enabling faster time-to-market and improved product reliability for customer designs. Helping Synopsys maintain its leadership position in semiconductor innovation and technology advancement.

Master’s degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or related field. 3+ years of relevant experience in semiconductor design, DFT, or related domains. Strong understanding of VLSI design principles and DFT methodologies. Expertise in DFT scan insertion and related verification techniques. Proficiency with scripting languages such as TCL, Python, or Perl for automation and tool customization. Experience with semiconductor design tools and tool flows is highly desirable.

Excellent communicator, able to present complex technical concepts clearly to diverse audiences. Collaborative team player who thrives in cross-functional environments. Analytical thinker with strong problem-solving skills and a proactive approach. Adaptable and resilient, comfortable working in a fast-paced and dynamic industry. Customer-focused, always seeking to deliver value and build positive relationships. Continuous learner, passionate about staying at the forefront of industry trends and technologies.

You’ll join a dynamic, highly skilled team of Application Engineers and Product Specialists dedicated to advancing semiconductor design methodologies and delivering value to customers. The team collaborates closely with Account Managers and R&D experts, ensuring that customer requirements are met with innovative, reliable, and scalable solutions. Together, you will contribute to Synopsys’ reputation for excellence, support each other’s growth, and drive the future of technological innovation in the semiconductor industry.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a DFT Applications Engineer, Staff, you will collaborate with semiconductor design companies to understand their methodologies, challenges, and requirements. You will work closely with Account and R&D teams to develop and implement stable, scalable tool solutions tailored to customer needs.

Responsibilities:

• Collaborate with semiconductor design companies to understand their methodologies, challenges, and requirements.
• Work closely with Account and R&D teams to develop and implement stable, scalable tool solutions tailored to customer needs.
• Gather detailed requirements and provide regular updates on solution progress to internal stakeholders and customers.
• Demonstrate expertise in Design for Testability (DFT), including scan insertion, and deliver impactful presentations to customers.
• Conduct technical demonstrations and training sessions, showcasing the benefits and capabilities of Synopsys solutions.
• Stay abreast of industry advancements, continuously updating your knowledge to ensure best-in-class solutions.
• Contribute to the development of automation and custom scripts to enhance tool functionality and customer productivity.

Impact:

• Enable customers to achieve higher quality and reliability in their semiconductor designs through advanced DFT methodologies.
• Drive customer satisfaction by delivering tailored, scalable, and robust solutions that address unique design challenges.
• Strengthen Synopsys' reputation as a trusted partner in the semiconductor industry by providing expert guidance and support.
• Accelerate adoption of Synopsys tools and technologies, contributing to the company’s growth and market leadership.
• Foster innovation by integrating latest industry trends and methodologies into customer solutions.
• Promote cross-team collaboration, ensuring seamless communication and alignment between Account, R&D, and customer teams.
• Support diversity and inclusion initiatives by contributing your unique perspective and fostering a welcoming work environment.

Requirements:

• Master’s degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant experience in semiconductor design or related areas.
• Strong understanding of VLSI and Design for Testability (DFT) concepts and methodologies.
• In-depth knowledge and practical experience with DFT scan insertion.
• Familiarity with semiconductor design tools and scripting languages (TCL, Python, Perl) for automation and customization.
• Excellent communication and presentation skills, with a proven ability to interact effectively with customers and internal teams.
• Ability to work collaboratively in a cross-functional team environment.
• Strong problem-solving skills and adaptability in a fast-paced, dynamic setting.

Who You Are:

• Innovative thinker with a customer-centric approach.
• Collaborative and open-minded team player.
• Proactive learner, eager to stay ahead of industry trends.
• Effective communicator, able to simplify complex technical topics.
• Resilient and adaptable, thriving in dynamic environments.
• Committed to diversity, inclusion, and fostering a supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a dedicated engineering team in Bangalore focused on delivering advanced solutions to semiconductor design companies. Our team values collaboration, innovation, and continuous learning, working closely with Account and R&D departments to ensure customer success. We foster a supportive environment where every member’s expertise and perspective contribute to our shared goals.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a DFT Senior/Staff Engineer, you will own DFT tasks at IP level, including scan chain stitching, ATPG, and simulation. You will create timing constraints for mission and DFT modes, work with design and physical implementation teams on synthesis and constraint validation, support customer IP integration and silicon bring-up, and lead and coach DFT team members.

The impact you will have includes improving testability and quality of IP cores, speeding up time-to-market for new chips, supporting seamless SoC integrations for customers, and mentoring team members and sharing best practices.

To be successful in this role, you will need a BS/MS/PhD in Electronics or a related field, 2+ years DFT design experience, expertise in scan insertion, ATPG, JTAG, and experience with Synopsys tools (Design Compiler, VCS, TetraMAX) is a plus. You will also need scripting skills (Perl, TCL, Python) and be detail-oriented, analytical, and a strong communicator.

Join our expert DFT Engineering team in Ho Chi Minh City, dedicated to advancing testability and reliability in semiconductor IP.

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At Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15995

Remote Eligible

No

Date Posted

03/05/2026

Alternate Job Titles:

• Staff ASIC Digital Design Engineer

• Staff DFT Engineer

• Staff SoC Testability Engineer

We Are:

At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.

You Are:

You are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.

What You’ll Be Doing:

• Define and implement DFT architecture for IP designs

• Perform SCAN insertion and ATPG simulation

• Analyze and improve test coverage

• Develop STA DFT timing constraints

• Prepare DFT integration guidelines for SoC

• Conduct quality checks and FMEDA/DFMEA analysis

The Impact You Will Have:

• Enhance product reliability and quality

• Support functional safety standards (ISO26262, FUSA)

• Streamline SoC integration

• Reduce debug cycles and time-to-market

• Mentor peers

• Drive innovation in test methodology

What You’ll Need:

• BS/MS/PhD in Electronics or related field

• 5+ years DFT design experience

• Expertise in Scan insertion, ATPG, JTAG

• Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)

• Scripting (Perl, TCL, Python) is a plus

Who You Are:

• Responsible and collaborative

• Excellent English communication

• Team player and problem solver

The Team You’ll Be A Part Of:

Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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