We're hiring a Field HW Engineer to work on-site at our data centre in Bruyères-le-Châtel. As a Field HW Engineer, you will be responsible for understanding end-to-end systems, executing complex/vendor-level interventions, and guiding L1 engineers on site.
\nYour work will involve hands-on troubleshooting and repair of compute, storage, interconnect and cooling systems to keep our large GPU/CPU cluster healthy and scalable. You will also be responsible for leading complex interventions, advanced diagnostics, guiding and uplifting L1s, process and automation, safety and compliance, and parts and logistics.
\nTo be successful in this role, you will need 5+ years of experience in data center/server hardware or L2/L3 hardware support, with proven complex hands-on work in production (HPC/AI/Cloud at scale). You should have end-to-end hardware expertise, including comfort with CPU/memory/PCIe cards, NICs, PSUs, drives, network, power and cooling. You should also be confident in analyzing BMC/IPMI logs, linux software logs and crashes simple CLI checks, and have methodical root cause analysis skills.
\nThe ideal candidate will be willing to travel between sites (Paris area or nearby regions, occasionally in Europe or US) and have a strong understanding of safety and discipline, including impeccable ESD/LOTO/PPE habits, zero rough handling, and clean, labeled, auditable work.
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\nYou are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.
\nYour technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.
\nYou will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.
\nYou will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.
\nYou will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.
\nYou will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nYou will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
\nYou will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.
\nYou will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.
\nYou will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nWhat you'll do
\nDevelop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.
\nWork with leading edge designs and teams to drive the industry best PPA for IP designs.
\nEvaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.
\nDevelop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
\nWork as a liaison between EDAG tool and IP design teams.
\nContinuously improve and refine design processes to enhance efficiency and performance.
\nWhat you need
\nBS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.
\nKnowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
\nDirect hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.
\nAbility to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
\nGood analysis, debugging, and problem-solving skills.
\nSolid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nFamiliarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.
\nWorking knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
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\nDesign and development of mechanical and electrical systems, including:
\nSystem modeling and simulation to validate performance and optimize functionality.
\nSystem integration: analyzing the impact of changes on the overall architecture.
\nTechnical supplier management: evaluating international components and adapting them to national suppliers.
\nCollaboration on hybridization systems and electronic architecture projects.
\nWhat you need
\nBachelor's degree in Mechanical, Electrical, Electronic, or Automotive Engineering.
\nMinimum of 5-10 years of experience in powertrain system development or similar automotive technologies, with focus on electrified powertrains.
\nDeep knowledge of hybrid powertrain architectures, including electric motor and battery integration.
\nExperience in managing engineering projects and multidisciplinary teams.
\nTechnical experience in electronic systems architecture, engine calibration, software, and product design.
\nAbility to manage economic aspects (CAPEX, OPEX, PRF evolution).
\nFamiliarity with tools such as SIEMENS NX, CATIA, ANSYS MECHANICAL, NASTRAN, FLOTHERM, FLO EFD, ESATAN, CRUISE M, EXCITE M.
\nWhy this matters
\nThis role contributes to conceptual and detailed design, requirements definition, subsystem integration, and functional validation, playing a key role in creating innovative platforms for critical applications.
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