You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.

Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.

Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.

Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.

Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

Conducting design reviews and offering constructive feedback to enhance quality and performance.

Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.

Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.

Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.

Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.

Fostering collaboration across global teams, leading to improved methodologies and best practices.

Maintaining the highest standards of quality, compliance, and performance in every design delivered.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

Responsibilities

• Collaborating with cross-functional teams during early design stages to optimize and define SIPI (Signal Integrity/Power Integrity) performance requirements, including bump mapping and power estimation.
• Designing and developing advanced silicon package solutions such as silicon interposers, RDL fanout packages, and silicon bridge packages.
• Modeling and analyzing advanced package designs to ensure optimal electrical, thermal, and mechanical performance.
• Representing Synopsys on business unit projects as a technical leader and subject matter expert in advanced packaging.
• Resolving a wide range of design and integration issues using creative, data-driven approaches.
• Supporting customer engagements in exploring and implementing advanced package solutions with Synopsys IPs.
• Collaborating with global teams to share best practices and drive innovation in advanced packaging methodologies.

Requirements

• Bachelor’s degree in Electrical or Electronic Engineering (Master’s or PhD preferred).
• Minimum of 10 years’ relevant experience in advanced package design, model extraction, and analysis.
• Expert knowledge of advanced circuit and transmission line theory.
• Hands-on experience with TSMC, Intel, Samsung, or OSAT advanced package technologies.
• Proficiency in multi-physics analysis (EMIR, Thermal, Thermal-Mechanical, Electromagnetic, etc.).
• Familiarity with both Windows and Linux operating systems.
• Experience with industry-standard EDA tools such as Cadence APD, Innovus, Integrity-3DIC, Synopsys ICC2, 3DIC Compiler, and Fusion Compiler.

What You’ll Need

• A creative problem solver with strong analytical and critical thinking skills.
• An excellent communicator, able to explain technical concepts to diverse audiences.
• A collaborative team player who values inclusivity, diversity, and shared success.
• Adaptable, quick to learn, and enthusiastic about adopting new technologies and methodologies.
• Detail-oriented, quality-driven, and committed to continuous improvement and innovation.
• Self-motivated with a strong sense of ownership and accountability.

The Team You’ll Be A Part Of

Join a global, highly skilled, and supportive team dedicated to advancing the forefront of package design and integration.

Our team works closely with R&D, product management, and customer engineering groups to foster innovation, technical excellence, and open communication.

Together, we tackle some of the most complex challenges in the semiconductor industry, supporting each other’s growth and celebrating our collective achievements.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.

Key responsibilities include:

• Designing and developing standard cell layouts
• Applying comprehensive sign-off checks
• Collaborating with global teams to resolve methodology issues and implement optimized layout designs
• Conducting design reviews and offering constructive feedback to enhance quality and performance

You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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Your responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

You will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

The impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.

To succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.

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