Key Responsibilities:

• Design and implement physical design flows for SLM IPs and subsystems, including state-of-the-art SLM Controllers and on-chip Monitors.
• Execute RTL2GDS flows on advanced process nodes (16nm to 3nm and beyond), ensuring robust performance and reliability.
• Perform static timing analysis, synthesis, and layout closure using industry-leading EDA tools, preferably Synopsys PrimeTime, ICC2, Design Compiler, or Fusion Compiler.
• Collaborate with cross-functional teams to integrate soft and mixed-signal IPs, optimize design margins, and address high-frequency, multi-voltage, and low-power requirements.
• Develop and enhance automation scripts (TCL/PERL) to streamline design processes and improve execution efficiency.
• Participate in project planning, execution, and mentoring, supporting both internal teams and external customers with technical expertise and guidance.
• Contribute to the signoff and verification of designs, ensuring compliance with quality and reliability standards.

Impact:

• Accelerate the integration and deployment of next-generation SLM products, enabling customers to bring differentiated solutions to market faster and with reduced risk.
• Optimize semiconductor lifecycle management through innovative hardware IP, test, and analytics, enhancing performance, power, area, and yield.
• Drive advancements in chip design and verification methodologies, supporting the evolution of process nodes and IP integration.
• Enhance reliability and scalability of technology products, contributing to breakthroughs in AI, IoT, automotive, and cloud sectors.
• Empower global teams and customers with robust solutions, technical guidance, and effective collaboration.
• Support Synopsys' leadership in the Era of Smart Everything, powering the technologies that shape our connected world.

Requirements:

• Strong experience in standard ASIC RTL2GDS physical implementation and signoff flows.
• Hands-on expertise in synthesis, pre-layout STA, post-layout STA, and CTS tools.
• BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience.
• Automation-focused mindset with proven experience in scripting (TCL/PERL) and custom flow development.
• Exposure to soft and mixed-signal IPs, high-frequency/multi-voltage designs, and low-power methodologies.
• Proficiency with EDA tools from any vendor, preferably Synopsys tools (PrimeTime, ICC2, Design Compiler, Fusion Compiler).
• Solid understanding of OCV, POCV, derates, crosstalk, and design margins.
• Experience in layout of digital blocks, timing constraints, STA, and timing closure.
• Experience with PVT-sensors and/or DFT/DFx technologies is a strong plus.

Who You Are:

• Collaborative and inclusive team player who values diversity and supports others.
• Excellent communicator, able to convey complex technical concepts clearly and effectively.
• Mentor and leader, providing guidance and support to peers and junior engineers.
• Adaptable and innovative, eager to learn and embrace new technologies and methodologies.
• Self-motivated with strong project execution and planning skills.
• Customer-focused, dedicated to delivering high-quality solutions and support.

The Team You’ll Be A Part Of:

You’ll join the rapidly expanding Hardware-Analytics and Test (HAT) business unit as a member of the SLM Hardware Group (SHG). The team is dedicated to developing advanced SLM IPs and subsystems, leveraging expertise in backend and physical design to deliver robust, high-performance solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub