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You are adept at communicating with both internal and external stakeholders, ensuring that your designs meet the highest standards of quality and performance.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.</li>\n<li>Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.</li>\n<li>Developing and executing comprehensive test plans to verify the functionality and performance of your designs.</li>\n<li>Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.</li>\n<li>Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team.</li>\n<li>Staying up to date with the latest industry trends and technologies, continuously improving your skills and knowledge.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.</li>\n<li>Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.</li>\n<li>Enhancing the overall quality and performance of Synopsys&#39; products through meticulous design and verification processes.</li>\n<li>Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.</li>\n<li>Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.</li>\n<li>Contributing to Synopsys&#39; reputation as a leader in the semiconductor industry through your expertise and innovative solutions.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC digital design and verification, with a strong background in RTL design, using industry standard HDLs; Verilog, SystemVerilog.</li>\n<li>Proficiency in using industry-standard EDA tools and methodologies for design and verification.</li>\n<li>Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC design, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).</li>\n<li>Broad knowledge of the full digital ASIC and IP development flow, including RTL design, lint, CDC, RDC, synthesis and STA.</li>\n<li>Experience with power analysis and RTL level power optimization techniques.</li>\n<li>Familiarity with verification languages and methodologies; SystemVerilog, SVA, UVM.</li>\n<li>Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.</li>\n<li>Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.</li>\n<li>A strategic thinker with the ability to implement goals that have a direct impact on department results.</li>\n<li>A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.</li>\n<li>A collaborative team player who thrives in dynamic and fast-paced environments.</li>\n<li>A lifelong learner who stays up to date with the latest industry trends and continuously seeks to improve their skills and knowledge.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. 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offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.\nOur total rewards include both monetary and non-monetary offerings.\nYour recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.\nSynopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses.\nSynopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.\nThe actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.\nYour recruiter can share more specific details on the total rewards package upon request.</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.\nWe feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.\nWe&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ec579fde-89b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-architect-fpga-design-pcie-protocol/44408/92655118112","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$208,000 - 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. 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If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7026ea72-dd8"},"title":"RTL Design, Sr Engineer","description":"<p>We are seeking a skilled RTL Design Engineer to join our team in Hanoi/Ho Chi Minh City/Da Nang. As a member of our team, you will be responsible for developing specifications and RTL for High Bandwidth Interface PHY IP. You will collaborate with Verification teams to ensure design accuracy and coordinate logic implementation phases across teams. You will also apply scripting skills for design automation and participate in onboarding in Da Nang and transitioning to Hanoi or Ho Chi Minh City.</p>\n<p>The successful candidate will have a BS/MS/PhD in Electronics Engineering or Telecommunications and 2+ years of experience in RTL design for ASIC or PHY IP. You will have experience with VCS, Verdi, Spyglass, Perl/TCL/Python and knowledge of clock domain crossing, APB, JTAG. Good English communication skills are essential.</p>\n<p>As a member of our team, you will advance industry-leading high bandwidth interface IP, ensure robust design and verification processes, drive innovation in RTL design and workflows, and enhance productivity through automation.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7026ea72-dd8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/rtl-design-sr-engineer-in-hanoi-hcmc-da-nang/44408/92454718896","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","ASIC design","PHY IP","VCS","Verdi","Spyglass","Perl","TCL","Python","clock domain crossing","APB","JTAG"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:17.483Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, ASIC design, PHY IP, VCS, Verdi, Spyglass, Perl, TCL, Python, clock domain crossing, APB, JTAG"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_106cfbf6-843"},"title":"Physical Design Specialist (PDS)","description":"<p>We&#39;re looking for a Physical Design Specialist (PDS) to join our team. As a PDS, you will support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p>Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro &amp; Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.</p>\n<p>You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</p>\n<p>As a member of our high-performing Customer Application Services team, you will collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Support customers in enjoying Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge.</li>\n<li>Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n<li>Collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</li>\n<li>Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.</li>\n<li>Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.</li>\n</ul>\n<p>Key Qualifications:</p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.</li>\n<li>Tool knowledge expected: Back end P&amp;R tools (Fusion Compiler, ICC2, Innovus)</li>\n<li>Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),</li>\n<li>Tool knowledge (preferred): STA (Primetime, Tempus)</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_106cfbf6-843","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-principal-engineer/44408/92840962656","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Place & Route (physical)","Synthesis (logical and physical)","STA experience and knowledge","Macro & Standard Cell Placement","Clock Tree Synthesis","Routing","Advanced Timing Optimization techniques","Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2)"],"x-skills-preferred":["RTL to GDSII full flow experience","Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis)","Clock Tree Synthesis methodologies like H-Tree, MS-CTS"],"datePosted":"2026-04-05T13:22:15.432Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge, Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques, Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2), RTL to GDSII full flow experience, Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis), Clock Tree Synthesis methodologies like H-Tree, MS-CTS"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8868aa47-ecb"},"title":"Solutions Engineering, Staff Engineer","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>We are seeking an experienced and highly motivated individual with a passion for technology and innovation. You will serve as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs) and working to enable IP as a product development platform. You will handle hands-on post-silicon test setups, collaborate on top-level physical design, board-level, and package-level designs, and develop post-silicon reports and conduct debug analysis.</p>\n<p>The successful candidate will drive the successful development and deployment of PVT IP sensors, enhance the reliability and performance of Synopsys&#39; silicon lifecycle monitoring solutions, ensure high-quality product development through meticulous testing and debugging, and contribute to the continuous innovation in chip design and software security.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Serving as the single point of contact for post-silicon debug activities</li>\n<li>Enabling Product Requirement Documents (PRDs)</li>\n<li>Working to enable IP as a product development platform</li>\n<li>Handling hands-on post-silicon test setups</li>\n<li>Collaborating on top-level physical design, board-level, and package-level designs</li>\n<li>Developing post-silicon reports and conducting debug analysis</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Hands-on experience in post-silicon test setups</li>\n<li>Sound knowledge of Digital/AMS chip design and post-silicon debug</li>\n<li>BS or MS degree in Electrical Engineering with 3+ years of experience</li>\n<li>Understanding of top-level physical design, board-level, and package-level designs</li>\n<li>Expertise in RTL development and physical design</li>\n</ul>\n<p>The ideal candidate will be a strong communicator with excellent teamwork and interpersonal skills, detail-oriented with a mindset geared towards IP debug and documentation, proactive learner with the ability to adapt to new IP functionalities, effective leader with strong people management skills, and highly motivated and capable of mentoring both internal teams and external customers.</p>\n<p>You will be part of the rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. This team is dedicated to conceptualizing, designing, and productizing state-of-the-art sensors that play a critical role in the silicon lifecycle monitoring process. Collaborate with a group of innovative and highly skilled professionals to drive the future of technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8868aa47-ecb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bhubaneswar/solutions-engineering-staff-engineer/44408/93159885488","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL development","physical design","post-silicon debug","Digital/AMS chip design","top-level physical design","board-level design","package-level design"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:07.011Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bhubaneswar"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL development, physical design, post-silicon debug, Digital/AMS chip design, top-level physical design, board-level design, package-level design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d01f9436-f2a"},"title":"R&D Engineering, Sr Staff Engineer","description":"<p>You are a highly skilled and knowledgeable professional with a passion for applied digital security of HW and SW implementations. With a PhD or advanced MS degree in Electrical Engineering or Computer Sciences, you bring profound expertise in implementations of cryptography and embedded security. You are an expert in side-channel and fault injection analysis and countermeasure development, and you are experienced with physical security evaluations.</p>\n<p>Your excellent presentation and communication skills enable you to interact effectively across teams and at various levels within the organisations. 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Touch device users, explore by touch or with swipe gestures.\\n\\n# Senior Technical Product Engineer\\n\\nSunnyvale, California, United States\\n\\nSave\\n\\nCategory: Product ManagementHire Type: Employee\\n\\n<strong>Job ID</strong> 15163<strong>Base Salary Range</strong> $192000-$288000<strong>Date posted</strong> 02/10/2026\\n\\n<strong>We Are:</strong>\\n\\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\\n\\n<strong>You Are:</strong>\\n\\nYou are an experienced and highly motivated engineer with a passion for semiconductor innovation and digital design solutions. You thrive in environments that challenge you to bridge customer needs with cutting-edge technology, and you excel at translating complex technical concepts into actionable product strategies. With a deep understanding of EDA tools,especially in areas like synthesis, RTL architecture, place and route and  ECO methodologies,you are eager to drive the development of next-generation solutions. You bring a strong analytical mindset, a collaborative spirit, and a customer-centric approach to every project. Your ability to engage directly with customers, understand their critical challenges, and translate those insights into high-value product features sets you apart. You are a thought leader, comfortable presenting at industry forums and representing Synopsys as a subject matter expert. You are adept at managing cross-functional teams, prioritizing product roadmaps, and ensuring releases meet the highest standards of quality and impact. Your enthusiasm for technology is matched by your commitment to inclusivity, mentorship, and continuous learning. If you are ready to lead transformative projects and be at the forefront of semiconductor innovation, Synopsys is the place for you.\\n\\n<strong>What You’ll Be Doing:</strong>\\n\\n- Engaging directly with customers to identify high-value problems, particularly around optimizing power, performance, and area (PPA), and achieving multi-physics closure in design.\\n\\n- Analyzing and interpreting market trends to inform the Synopsys SCA roadmap, with a focus on advanced nodes and GenAI/Agentic flows.\\n\\n- Collaborating with DRIs and field partners to pinpoint product gaps and evaluate new opportunities for tool enhancement and innovation.\\n\\n- Defining and prioritizing product roadmaps by crafting Market Requirements Documents (MRDs) and partnering with Product Engineers to develop Product Requirements Documents (PRDs).\\n\\n- Writing code prototypes for new features and products, serving as &quot;executable specifications&quot; to demonstrate functionality and requirements to development teams.\\n\\n- Managing release readiness, including defining criteria for Alpha, Beta, Limited Customer Availability (LCA), and General Availability (GA) stages.\\n\\n- Enabling partners and field teams with training, strategic campaigns, and benchmarks to ensure new products deliver on promised value.\\n\\n- Representing Synopsys as a subject matter expert at customer forums, including TRMs and MRMs, and driving thought leadership at industry conferences.\\n\\n<strong>The Impact You Will Have:</strong>\\n\\n- Accelerate the adoption of Synopsys solutions, driving improved PPA outcomes for customers.\\n\\n- Shape the direction of Synopsys’s product offerings by identifying and acting on emerging industry trends.\\n\\n- Build stronger customer relationships through direct engagement, enabling tailored solutions that address their most critical challenges.\\n\\n- Enhance Synopsys’s reputation as a technology leader by presenting at industry events and fostering thought leadership.\\n\\n- Streamline product development processes through executable specifications, ensuring clarity and alignment across teams.\\n\\n- Increase the commercial success of new products by ensuring release readiness and effective go-to-market strategies.\\n\\n- Elevate partner and sales enablement, empowering teams to communicate product value and drive adoption.\\n\\n<strong>What You’ll Need:</strong>\\n\\n- Deep technical expertise in EDA tools, especially in synthesis, RTL architecture, place and route and ECO methodologies.\\n\\n- Proven experience in product management, including roadmap prioritization, MRD/PRD development, and release readiness are a nice to have\\n\\n- Strong coding skills for prototyping features and creating executable specifications.\\n\\n- Ability to analyze market trends, customer feedback, and competitive landscapes to inform product strategy.\\n\\n- Experience collaborating with cross-functional teams (engineering, sales, marketing, partners) in a fast-paced environment.\\n\\n- Familiarity presenting at industry forums, conferences, and customer meetings as a subject matter expert.\\n\\n<strong>Who You Are:</strong>\\n\\n- Customer-centric, with a passion for solving complex technical challenges.\\n\\n- Analytical and strategic thinker, able to synthesize information and drive actionable decisions.\\n\\n- Collaborative leader, skilled at working across teams and building consensus.\\n\\n- Effective communicator, comfortable presenting to diverse audiences and stakeholders.\\n\\n- Adaptable, curious, and committed to continuous learning and improvement.\\n\\n- Inclusive and supportive, fostering a culture of mentorship and teamwork.\\n\\n<strong>The Team You’ll Be A Part Of:</strong>\\n\\nYou’ll join a passionate and innovative product management team at Synopsys, focused on delivering state-of-the-art solutions for semiconductor design, verification, and optimization. Our team works closely with engineering, sales, and marketing to ensure that our tools meet the evolving needs of our customers. Together, we drive product excellence, industry leadership, and customer success.\\n\\n<strong>Rewards and Benefits:</strong>\\n\\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\\n\\n<strong>#LI-SV1</strong></p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7330a4d3-ca6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/senior-technical-product-engineer/44408/91639673840","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$192000-$288000","x-skills-required":["eda tools","synthesis","rtl architecture","place and route","eco methodologies","product management","roadmap prioritization","mrp/prd development","release readiness","coding skills","market trends","customer feedback","competitive landscapes","cross-functional teams","presenting at industry forums"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:53.469Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"product management","industry":"technology","skills":"eda tools, synthesis, rtl architecture, place and route, eco methodologies, product management, roadmap prioritization, mrp/prd development, release readiness, coding skills, market trends, customer feedback, competitive landscapes, cross-functional teams, presenting at industry forums","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":192000,"maxValue":288000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_71dc7bd3-6ee"},"title":"Applications Engineering, Architect- Emulation","description":"<p>Engineer the Future with Us</p>\n<p>We currently have 614 open roles</p>\n<p><strong>Job Summary</strong></p>\n<p>You are a passionate and driven professional with a profound mastery of hardware-assisted verification (HAV), using emulation and FPGA prototyping methodologies, with a sharp focus on performance optimization. Your expertise covers the entire lifecycle of HW/SW product development, from early RTL verification to software bring up and platform delivery.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Drive advanced product capabilities and innovations in emulation runtime performance for industry-leading platforms.</li>\n<li>Engage in the full product lifecycle, from feature definition and implementation to rigorous testing, quality measurement, and customer deployment.</li>\n<li>Collaborate closely with internal stakeholders, including Application Engineering peers and R&amp;D teams, to deliver superior outcomes for customers.</li>\n<li>Provide technical leadership and product evaluation support to key emulation customers across the globe.</li>\n<li>Lead comprehensive root cause analyses to resolve and prevent emulation performance bottlenecks.</li>\n<li>Ensure the highest standards of verification for SoC designs, contributing to the creation of robust and reliable products.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>Minimum 12+ years of experience in emulation methodology, spanning early RTL verification to software bring up.</li>\n<li>Proven expertise in verification, with a focus on System on Chip (SoC) design bring-up and validation.</li>\n<li>Comprehensive knowledge of the architecture of emulation / FPGA prototyping platforms and their eco-systems.</li>\n<li>A good understanding of the compilation and runtime flows on these emulation platforms.</li>\n<li>Demonstrated experience in using debug features of these emulation platforms, and in conducting root cause analysis for emulation runtime performance issues.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Competitive salary and benefits package</li>\n<li>Opportunities for career growth and professional development</li>\n<li>Collaborative and dynamic work environment</li>\n<li>Recognition and rewards for outstanding performance</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>A collaborative team player who thrives in dynamic, fast-paced environments.</li>\n<li>Detail-oriented and analytical, with exceptional problem-solving skills.</li>\n<li>Curious, adaptable, and eager to embrace new challenges and responsibilities.</li>\n<li>An effective communicator, skilled at conveying complex technical information to diverse audiences.</li>\n<li>An innovative thinker with a passion for continuous improvement and learning.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You’ll join the Product Engineering (PE) team within the TPG division at Synopsys Bangalore office. This team is at the forefront of delivering and deploying next-generation performance technologies in ZeBu platforms to customers worldwide. As a pivotal member, you will engage in technically challenging projects with significant responsibilities and visibility, all while enjoying a supportive environment that fosters career growth, innovation, and professional development.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_71dc7bd3-6ee","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-architect-emulation/44408/80107531584","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["emulation methodology","hardware-assisted verification","FPGA prototyping","RTL verification","software bring up","System on Chip (SoC) design bring-up and validation","compilation and runtime flows","debug features","root cause analysis"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:48.648Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"emulation methodology, hardware-assisted verification, FPGA prototyping, RTL verification, software bring up, System on Chip (SoC) design bring-up and validation, compilation and runtime flows, debug features, root cause analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_44645300-ced"},"title":"Hardware Engineering, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.</p>\n<p>Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.</p>\n<p>Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys&#39; design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.</p>\n<p>2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.</p>\n<p>Analytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.</p>\n<p>You&#39;ll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&amp;D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you&#39;ll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_44645300-ced","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/hardware-engineering-sr-engineer/44408/93159885392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL simulation","logic synthesis","timing verification tools","DFT architectures","debug tools","SystemVerilog","UVM","Verilog","C/C++","Python","Tcl","EDA tools","VC Auto-Testbench","protocol compliance checking"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:43.007Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL simulation, logic synthesis, timing verification tools, DFT architectures, debug tools, SystemVerilog, UVM, Verilog, C/C++, Python, Tcl, EDA tools, VC Auto-Testbench, protocol compliance checking"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ae9d1be9-0e5"},"title":"Senior Staff Engineer - Solutions Engineering","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. 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As a Senior Staff Engineer, you will be responsible for serving as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs), working to enable IP as a product development platform, handling hands-on post-silicon test setups, collaborating on top-level physical design, board-level, and package-level designs, developing post-silicon reports, and conducting debug analysis.</p>\n<p>The successful candidate will have hands-on experience in post-silicon test setups, sound knowledge of Digital/AMS chip design and post-silicon debug, a BS or MS degree in Electrical Engineering with 6+ years of experience, understanding of top-level physical design, board-level, and package-level designs, and expertise in RTL development and physical design.</p>\n<p>As a Senior Staff Engineer, you will be part of the rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. 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You will collaborate closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading the design and verification of complex ASIC blocks and systems</li>\n<li>Collaborating with cross-functional teams to ensure seamless integration of all design components</li>\n<li>Developing and executing comprehensive test plans to verify the functionality and performance of your designs</li>\n<li>Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency</li>\n<li>Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team</li>\n</ul>\n<p>As a Principal Engineer, you will have a significant impact on the development of cutting-edge technology that shapes the future. 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Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li><p>Working closely with a world-class R&amp;D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.</p>\n</li>\n<li><p>Working closely with customers, you will bring detailed requirements into the factory to enable R&amp;D for strong, robust, and successful product development.</p>\n</li>\n<li><p>Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.</p>\n</li>\n<li><p>Driving the deployment and smooth execution of SLM solutions into customers’ projects.</p>\n</li>\n<li><p>Enabling customers to realize the value of silicon health monitoring in the context of 3DIC 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and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You have a strong passion for working with embedded processors or processor-based systems.</p>\n<p>You bring knowledge of HDL design, with a preference for experience in RISC processor architectures, DSP, AI (Neural Processing Unit), and multi-core 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You will be self-motivated and proactive in seeking solutions and driving projects forward.</p>\n<p>You will join a talented and diverse engineering team focused on developing and verifying cutting-edge Silicon Lifecycle Management IPs for next-generation chip solutions.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8409e0bb-24a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/rtl-design-and-verification-staff-engineer/44408/93169652816","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","EDA tools","Verilog","System Verilog","TCL scripting","Formal Verification methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:54.841Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, EDA tools, Verilog, System Verilog, TCL scripting, Formal Verification methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e0507188-1b6"},"title":"ASIC Digital Design, Architect","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as HBM, DDR, PCIe/CXL, AMBA and its applications. You can define and execute a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Defining and developing ASIC RTL design and verification at both chip and block levels.</li>\n<li>Creating and executing design plans for complex digital designs, particularly focusing on HBM, PCIe/CXL and AMBA protocols.</li>\n<li>Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.</li>\n<li>Utilizing advanced design and verification methodologies and tools to achieve high-quality results.</li>\n<li>Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.</li>\n<li>Communicating with internal and external stakeholders to align on project goals and deliverables.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enhancing the reliability and performance of Synopsys’ digital design processes.</li>\n<li>Driving innovations in HBM, PCIe/CXL and AMBA technology, contributing to the development of cutting-edge semiconductor solutions.</li>\n<li>Improving time-to-market for high-performance silicon chips through efficient methodologies.</li>\n<li>Building and nurturing a highly skilled development team, elevating overall project quality.</li>\n<li>Influencing strategic decisions that shape the future of Synopsys’ capabilities.</li>\n<li>Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC RTL design.</li>\n<li>In-depth knowledge of HBM, PCIe, CXL, AMBA and similar IO protocols and their applications.</li>\n<li>Proficiency in advanced digital design tools and methodologies.</li>\n<li>Strong problem-solving skills and the ability to work independently.</li>\n<li>Excellent communication skills for effective collaboration with diverse teams.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>A visionary leader with a strategic mindset.</li>\n<li>A mentor who fosters talent and encourages innovation.</li>\n<li>A proactive problem solver who thrives in complex environments.</li>\n<li>An effective communicator with the ability to convey technical concepts to a broad audience.</li>\n<li>A team player who values collaboration and diversity.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e0507188-1b6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/asic-digital-design-architect/44408/91458064944","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","HBM","DDR","PCIe/CXL","AMBA","advanced digital design tools","methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:54.282Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Dublin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, HBM, DDR, PCIe/CXL, AMBA, advanced digital design tools, methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e40da191-421"},"title":"Staff ASIC Digital Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Working closely with a world-class R&amp;D team, you&#39;ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.</li>\n<li>Working closely with customers, you will bring detailed requirements into the factory to enable R&amp;D for strong, robust, and successful product development.</li>\n<li>Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.</li>\n<li>Driving the deployment and smooth execution of SLM and Test solutions into customers&#39; projects.</li>\n<li>Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enhancing Synopsys&#39; Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.</li>\n<li>Driving the adoption of Synopsys&#39; SLM and DFT solutions at premier customer base worldwide.</li>\n<li>Influencing the development of next-generation SLM IPs and solutions.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li><p>BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.</p>\n</li>\n<li><p>8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.</p>\n</li>\n<li><p>Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.</p>\n</li>\n<li><p>Knowledge on memory defectivities soft errors and reliability.</p>\n</li>\n<li><p>Familiarity with error correcting codes such as Hamming and Hsiao.</p>\n</li>\n<li><p>Hands-on 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innovation.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering or Telecommunications.</li>\n</ul>\n<ul>\n<li>5+ years of RTL design experience for ASIC or PHY IP.</li>\n</ul>\n<ul>\n<li>Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).</li>\n</ul>\n<ul>\n<li>Knowledge of clock domain crossing, APB, JTAG protocols.</li>\n</ul>\n<ul>\n<li>Strong English communication skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Responsible, result-oriented, and self-motivated.</li>\n</ul>\n<ul>\n<li>Collaborative and proactive problem solver.</li>\n</ul>\n<ul>\n<li>Effective communicator and mentor.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a collaborative engineering team delivering innovative PHY IP solutions.</p>\n<p>Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.</p>\n<p><strong>Rewards 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Verification Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of HBM or PCIe/CXL and its applications. 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Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Health &amp; Wellness: Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>Time Away: In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Retirement Plans: Save for your future with our retirement plans that vary by region and country.</li>\n<li>Compensation: Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_05702639-4e7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/reading/asic-digital-ip-design-verification-architect/44408/91458064928","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design and verification","HBM or PCIe protocols and their applications","Advanced verification tools and methodologies","Strong problem-solving skills","Excellent communication skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:07.811Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Reading"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design and verification, HBM or PCIe protocols and their applications, Advanced verification tools and methodologies, Strong problem-solving skills, Excellent communication skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e4bdd5cd-618"},"title":"Senior Manager Formal Verification Applications Engineering","description":"<p>Join us to transform the future through continuous technological innovation. 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You will define formal verification methodologies to enhance customer productivity and streamline verification processes. You will lead the development of assertion IPs tailored to meet specific customer requirements.</p>\n<p>Accelerate the adoption of industry-leading formal verification solutions, enabling customers to achieve robust, high-quality silicon designs. Strengthen Synopsys&#39; reputation as a trusted partner for verification innovation and excellence. Drive customer success by delivering tailored consulting services and assertion IPs that address complex verification challenges. Enhance productivity and efficiency for customers through advanced formal methodologies and flows. Influence the direction of formal verification technology by collaborating with R&amp;D and Product Management teams. Foster a culture of technical excellence and inclusion within your team, empowering members to grow and contribute meaningfully. Enable strategic customers to meet critical industry requirements such as design security, automotive safety, and verification signoff.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e4bdd5cd-618","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/senior-manager-formal-verification-applications-engineering/44408/93365523248","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","Verification methodologies","Assertion-based verification","Unix/Linux automation shell scripting","Programming languages such as Tcl, Perl, and Python","Formal property verification testbench development","Floating point arithmetic operations","C/C++","IEEE math libraries","Security architecture","Automotive safety (FuSa)","Verification signoff with formal"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:43.796Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verification methodologies, Assertion-based verification, Unix/Linux automation shell scripting, Programming languages such as Tcl, Perl, and Python, Formal property verification testbench development, Floating point arithmetic operations, C/C++, IEEE math libraries, Security architecture, Automotive safety (FuSa), Verification signoff with formal"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6d8de738-1a7"},"title":"Staff Hardware Engineer","description":"<p>We are seeking a skilled Staff Hardware Engineer to join our team in Cairo. As a Staff Hardware Engineer, you will be responsible for defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development. You will develop and optimize RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability. You will also drive the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.</li>\n<li>Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</li>\n<li>Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.</li>\n<li>Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.</li>\n</ul>\n<p>As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p><strong>Responsibilities:</strong></p>\n<p>Define and develop ASIC RTL design and verification at both chip level and block level. Collaborate with cross-functional teams to design, implement, and verify PCIe interfaces. Perform RTL coding, synthesis, and simulation to ensure design functionality and performance. Conduct design reviews and provide technical guidance to junior engineers. Work closely with physical design teams to ensure seamless integration and optimization. Debug and resolve design issues to ensure timely delivery of high-quality products.</p>\n<p><strong>Impact:</strong></p>\n<p>Contribute to the development of high-performance silicon chips that power next-generation technologies. Enhance the functionality and performance of Synopsys&#39; PCIe solutions. Drive innovation and improve design methodologies within the team. Ensure the successful delivery of complex ASIC projects on time and within budget. Mentor and guide junior engineers, fostering a culture of continuous learning and development. Collaborate with cross-functional teams to deliver integrated and optimized solutions for our customers.</p>\n<p><strong>Requirements:</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, or a related field. Extensive experience in ASIC digital design and verification. Strong knowledge of PCIe protocols and interfaces. Proficiency in RTL coding (Verilog/SystemVerilog) and simulation tools. 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As a Mixed-Signal Verification Engineer at Synopsys, you will be responsible for executing mixed-signal CoSim verification tasks for system-level validation across analog and digital domains.</p>\n<p>Your primary responsibilities will include building and running CoSim simulations using established environments, integrating schematics and RTL, and adhering to procedures for reproducibility and traceability. You will also be responsible for debugging mixed-signal failures by collecting logs, waveforms, and reproducible steps, performing first-pass triage, and escalating issues with clear evidence to design and verification teams.</p>\n<p>In this role, you will collaborate with analog and digital designers to confirm expected behaviors, review corner cases, and align verification needs for day-to-day activities. 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Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c7306104-282","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/porto-salvo/mixed-signal-verification-engineer/44408/93403620512","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["System Verilog","CoSim","mixed-signal verification","analog and digital domains","RTL","verification methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:16:59.989Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Porto Salvo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"System Verilog, CoSim, mixed-signal verification, analog and digital domains, RTL, verification methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a3415fac-8d5"},"title":"ML HW-SW Co-design Software Manager","description":"<p>We are seeking a highly motivated and experienced Software Engineering Manager to join our HW-SW Co-design team and drive groundbreaking advances for machine learning acceleration.</p>\n<p>At Google DeepMind, we&#39;ve built a unique culture and work environment where long-term ambitious research can flourish. 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supporting micro-architecture and RTL development.</li>\n</ul>\n<ul>\n<li>Collaborate directly with customers to address their specific requirements and deliver tailored solutions.</li>\n</ul>\n<ul>\n<li>Manage key stages of SOC development, including design verification, DFT, physical design, and tapeout management.</li>\n</ul>\n<ul>\n<li>Work closely with partners on software, firmware, and packaging to ensure seamless integration of solutions.</li>\n</ul>\n<ul>\n<li>Participate in occasional travel and on-site engagements at customer premises to support project execution.</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Drive the successful delivery of advanced SOC projects across automotive, aerospace, and high-performance computing sectors.</li>\n</ul>\n<ul>\n<li>Enhance Synopsys’ reputation as an industry leader in SOC design and innovation.</li>\n</ul>\n<ul>\n<li>Mentor and support engineering talent, fostering a culture of continuous improvement and technical excellence.</li>\n</ul>\n<ul>\n<li>Increase customer satisfaction by providing high-quality, high-performance SOC solutions.</li>\n</ul>\n<ul>\n<li>Contribute to successful tapeouts and product launches, expanding Synopsys’ impact in the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Shape the development of smart, connected devices through your technical expertise and collaborative approach.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BSEE, MSEE, or Ph.D. in Electrical and/or Computer Engineering.</li>\n</ul>\n<ul>\n<li>At least 8 years of experience in SOC-level architecture and RTL development.</li>\n</ul>\n<ul>\n<li>Strong proficiency in SOC system architecture, micro-architecture, RTL development, design verification, DFT, and tapeout management.</li>\n</ul>\n<ul>\n<li>Solid understanding of high-performance computing architectures for mobile, data center, automotive, and edge computing SOCs.</li>\n</ul>\n<ul>\n<li>Experience with interconnect options (Arteris NOC, AMBA AXI, CXL, etc.) and SOC standard interfaces (PCIe, DDR, HBM, MIPI CSI/DSI, SPI, I2C).</li>\n</ul>\n<ul>\n<li>Implementation knowledge of CPU architectures (RISCV, ARC, X86, ARM).</li>\n</ul>\n<ul>\n<li>Hands-on experience with workflow tools (git, gitlab, github)</li>\n</ul>\n<ul>\n<li>Ability to travel and work on-site as needed; eligibility for government security clearances is a plus.</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You will join the System Solutions team, a group of passionate engineers dedicated to enabling customers with end-to-end SOC designs in advanced technologies.</p>\n<p>The team delivers comprehensive tool flows, develops innovative design methodologies, and provides customer-specific assistance.</p>\n<p>Our collaborative environment encourages continuous learning, knowledge sharing, and technical excellence, supporting customers from start-ups to industry leaders across a wide range of applications.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7a8bb995-8f1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/tokyo/soc-engineering-sr-staff-engineer/44408/92568976544","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SOC system architecture","micro-architecture","RTL development","design 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.</p>\n<p><strong>Responsibilities</strong></p>\n<p>Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</p>\n<p>Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.</p>\n<p>Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.</p>\n<p>Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.</p>\n<p>Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&amp;R-aware synthesis using tools such as Fusion Compiler.</p>\n<p>Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.</p>\n<p>Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.</p>\n<p>4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.</p>\n<p>Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.</p>\n<p>Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.</p>\n<p>Familiarity with high-speed design (&gt;600MHz), P&amp;R-aware synthesis, and EDA tools such as Fusion Compiler.</p>\n<p>Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.</p>\n<p>Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).</p>\n<p>Exposure to quality processes in IP design and verification is an advantage.</p>\n<p>Prior experience as a technical lead or mentor is highly desirable.</p>\n<p><strong>Who We Are Looking For</strong></p>\n<p>Innovative thinker with a solutions-oriented mindset and a passion for technology.</p>\n<p>Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.</p>\n<p>Natural leader with mentoring abilities, fostering inclusion and diversity within the team.</p>\n<p>Detail-oriented professional with strong analytical and problem-solving skills.</p>\n<p>Self-motivated, adaptable, and eager to drive technical excellence and process improvements.</p>\n<p>Committed to continuous learning and staying ahead of industry trends.</p>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_02d8b8e9-445","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-asic-rtl-design-engineer/44408/92577687840","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","Verilog/SystemVerilog","Simulation tools","Design flows","Linting","Static timing analysis","Formal checking","P&R-aware synthesis","Fusion Compiler","Version control systems","Scripting languages","Industry protocols","Ethernet","DDR","PCIe","USB","MIPI-UFS/Unipro","SD-MMC","AMBA"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:10:55.005Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, Verilog/SystemVerilog, Simulation tools, Design flows, Linting, Static timing analysis, Formal checking, P&R-aware synthesis, Fusion Compiler, Version control systems, Scripting languages, Industry protocols, Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1d6b52c9-024"},"title":"Principal Engineer","description":"<p>As a Principal Engineer at Synopsys, you will be responsible for driving end-to-end SOC development, from architectural definition through post-silicon validation and customer delivery. You will provide technical leadership and mentorship to teams of micro-architects, RTL developers, and cross-functional partners. You will engage directly with customers, addressing their unique needs and delivering solutions tailored to their requirements.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Managing the full SOC development lifecycle, including micro-architecture, RTL design, verification, DFT, physical design, and tapeout management.</li>\n<li>Collaborating with partners on software, firmware, and packaged part solutions, ensuring seamless integration and delivery.</li>\n<li>Occasionally traveling and working on-site at customer premises to support project execution and strengthen customer relationships.</li>\n</ul>\n<p>As a Principal Engineer, you will shape Synopsys&#39; role as a trusted partner for advanced SOC design across multiple industries, including automotive, aerospace, and high-performance computing. You will advance the adoption of cutting-edge technologies and design methodologies in customer projects. You will mentor and develop engineering talent, fostering technical excellence and innovation within the team.</p>\n<p>To succeed in this role, you will need:</p>\n<ul>\n<li>BSEE, MSEE, or Ph.D. in Electrical and/or Computer Engineering.</li>\n<li>Minimum 10 years of experience in SOC-level architecture and RTL development.</li>\n<li>Proficiency in SOC system architecture, micro-architecture, RTL development, design verification, DFT, and tapeout management.</li>\n<li>Expertise in high-performance computing architectures for mobile, data center, automotive, and edge computing SOCs.</li>\n<li>In-depth knowledge of interconnect options (Arteris NOC, AMBA AXI, CXL, etc.) and SOC standard interfaces (PCIe, DDR, HBM, MIPI CSI/DSI, SPI, I2C).</li>\n<li>Implementation experience with CPU architectures (RISCV, ARC, X86, ARM).</li>\n<li>Hands-on experience with workflow tools (git, gitlab, github).</li>\n<li>Ability to travel and work on-site as needed; eligibility for government security clearances is a plus.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1d6b52c9-024","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/tokyo/soc-engineering-principal-engineer/44408/92568976576","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SOC system architecture","micro-architecture","RTL development","design verification","DFT","physical design","tapeout management","high-performance computing architectures","interconnect options","SOC standard interfaces","CPU architectures","workflow tools"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:10:43.521Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Tokyo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SOC system architecture, micro-architecture, RTL development, design verification, DFT, physical design, tapeout management, high-performance computing architectures, interconnect options, SOC standard interfaces, CPU architectures, workflow tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_40a899dc-af8"},"title":"Senior/Staff ASIC Design Verification Engineer","description":"<p>Our organisation is seeking a skilled Senior/Staff ASIC Design Verification Engineer to join our team in Ho Chi Minh City, Vietnam. As a key member of our engineering team, you will be responsible for designing and developing cutting-edge semiconductor solutions. Your expertise in ASIC RTL design flow, RTL and GLS verification, and high-speed interface protocols will be essential in advancing our technology and enabling innovations in various industries.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.</li>\n<li>Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.</li>\n<li>Define, develop, and execute functional verification plans and test strategies.</li>\n<li>Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.</li>\n<li>Generate VCD files and perform power analysis/reporting using PrimeTime PX.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum of 2 years of experience in ASIC RTL design flow.</li>\n<li>Proficiency in RTL and GLS verification, with strong debugging capabilities.</li>\n<li>Excellent teamwork and communication skills, with professional proficiency in English.</li>\n<li>Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_40a899dc-af8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/senior-staff-asic-design-verification-engineer/44408/92568976592","x-work-arrangement":"onsite","x-experience-level":"senior/staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC RTL design flow","RTL and GLS verification","High-speed interface protocols","UVM-based methodologies","PrimeTime PX"],"x-skills-preferred":["High-speed interface protocols"],"datePosted":"2026-03-10T12:09:27.363Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design flow, RTL and GLS verification, High-speed interface protocols, UVM-based methodologies, PrimeTime PX, High-speed interface protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4b712e08-c1e"},"title":"Staff Engineer (Machine Learning)","description":"<p><strong>Job Description</strong></p>\n<p>At Synopsys, we&#39;re seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design &amp; Verification business. As a key member of this highly innovative team, you&#39;ll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.</li>\n<li>Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.</li>\n<li>Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.</li>\n<li>Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).</li>\n<li>Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.</li>\n<li>Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys&#39; product lines.</li>\n</ul>\n<p><strong>Impact:</strong></p>\n<ul>\n<li>Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.</li>\n<li>Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.</li>\n<li>Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys&#39; tools, driving industry-leading outcomes.</li>\n<li>Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.</li>\n<li>Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.</li>\n<li>Strengthen Synopsys&#39; position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelor&#39;s, Master&#39;s, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.</li>\n<li>5+ years of experience in chip design, EDA, or related fields.</li>\n<li>Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).</li>\n<li>Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.</li>\n<li>Solid understanding of Unix/Linux environments and design flow automation.</li>\n<li>Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.</li>\n<li>Familiarity with low power design techniques, computer architecture, and machine learning principles.</li>\n</ul>\n<p><strong>Who We&#39;re Looking For:</strong></p>\n<ul>\n<li>A creative problem solver who approaches challenges with curiosity and resilience.</li>\n<li>An effective communicator who collaborates well with multidisciplinary teams.</li>\n<li>Detail-oriented with a passion for quality and continuous improvement.</li>\n<li>Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.</li>\n<li>Committed to learning, growth, and sharing knowledge with others.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of:</strong></p>\n<p>You&#39;ll join the Machine Learning Center of Excellence (ML CoE) within Synopsys&#39; Silicon Design &amp; Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you&#39;ll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4b712e08-c1e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/staff-engineer-machine-learning/44408/92577691360","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["machine learning","chip design","EDA","Perl","Python","Tcl","shell scripting","Unix/Linux environments","design flow automation","RTL design","synthesis","place and route","verification","ATPG","custom-circuit design","signoff flows","low power design techniques","computer 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and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.</p>\n<p>As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.</p>\n<p>You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.</p>\n<p>You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.</p>\n<p>You will develop and implement advanced test plans and test environments at both unit and system levels.</p>\n<p>You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.</p>\n<p>You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.</p>\n<p>You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.</p>\n<p>This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.</p>\n<p>You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.</p>\n<p>You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.</p>\n<p>You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.</p>\n<p>You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.</p>\n<p>You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.</p>\n<p>You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.</p>\n<p>You will join the DesignWare IP Verification R&amp;D team, a group of talented and passionate engineers committed to advancing Synopsys&#39; leadership in semiconductor IP.</p>\n<p>The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.</p>\n<p>Collaboration, innovation, and a drive for excellence define our culture.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2a58c59b-da1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-design-verification-sr-staff-engineer-ddr/44408/89681053968","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC verification","System Verilog/UVM","HVL","Serial interface protocols","IP core development","Verification methodologies","Test plans and test environments","Functional coverage and code coverage metrics","Regressions and continuous improvement"],"x-skills-preferred":["DDR/LPDDR","RTL designers and architects","Chip architecture and circuit design","Semiconductor products"],"datePosted":"2026-03-10T12:07:42.010Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC verification, System Verilog/UVM, HVL, Serial interface protocols, IP core development, Verification methodologies, Test plans and test environments, Functional coverage and code coverage metrics, Regressions and continuous improvement, DDR/LPDDR, RTL designers and architects, Chip architecture and circuit design, Semiconductor products"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ab8cf079-959"},"title":"Sr/Staff AE for Physical Implementation RTL-GDS","description":"<p>This role combines the usage of industry-leading Synopsys implementation tools to solve critical design challenges of customers, working on the latest cutting-edge technology nodes, and enhancing QOR metrics to achieve best-in-class PPA and TAT targets of today&#39;s emerging semiconductor technologies.</p>\n<p>As a Staff Engineer, Application Engineering (AE), you will work on latest Synopsys implementation technologies (AI-ML Implementation, Physical Synthesis RTL-GDS, Multi Source CTS, Indesign Fusion technologies etc.) to solve complex PPA challenges Synopsys customers face.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Work on developing and debugging RTL-GDS implementation methodologies and flows.</li>\n<li>Provide technical solutions by identifying the design and/or EDA tool issues and providing appropriate solutions for customers.</li>\n<li>Effectively translate the findings into requirements for R&amp;D to improve both tool behaviors with enhancements as adaptive long-term solutions.</li>\n<li>Involved in the deployment of new technologies on the latest EDA versions and enabling customers to migrate to newer versions achieving the best PPA.</li>\n<li>Come up with proactive knowledge of customers&#39; pain point and come up with innovative solutions to address the same.</li>\n<li>Closely interacting with Synopsys R&amp;D team and product development team to develop future technologies.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>At least 5+ years of experience in Physical Implementation RTL-GDS.</li>\n<li>Candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs.</li>\n<li>Proficiency in Synopsys implementation tools is an advantage.</li>\n<li>The person must be self-motivated and dedicated with excellent debug skills.</li>\n<li>Requires proficiency in scripting (tcl / unix / perl).</li>\n<li>Excellent communication skills including the ability to interface with customers and business unit personnel are essential.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ab8cf079-959","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/sr-staff-ae-for-physical-implementation-rtl-gds/44408/92593032928","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Physical Implementation RTL-GDS","Synopsys implementation tools","Scripting (tcl / unix / perl)","Debugging","Methodology changes"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:05:13.350Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Implementation RTL-GDS, Synopsys implementation tools, Scripting (tcl / unix / perl), Debugging, Methodology changes"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b5f1283c-76e"},"title":"ASIC Digital Design, Sr Staff/Principal Engineer - DDR","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/09/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.</p>\n<p>You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>\n<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>\n<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>\n</ul>\n<ul>\n<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>\n</ul>\n<ul>\n<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>\n</ul>\n<ul>\n<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>\n</ul>\n<ul>\n<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>\n</ul>\n<ul>\n<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>\n</ul>\n<ul>\n<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>\n</ul>\n<ul>\n<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>\n</ul>\n<ul>\n<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>\n</ul>\n<ul>\n<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>\n</ul>\n<ul>\n<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>\n</ul>\n<ul>\n<li>Past experience of leading IP deign projects, team.</li>\n</ul>\n<ul>\n<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>\n</ul>\n<ul>\n<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>\n</ul>\n<ul>\n<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>\n</ul>\n<ul>\n<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>\n</ul>\n<ul>\n<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>\n<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>\n<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.</p>\n<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>\n<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b5f1283c-76e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","System architecture","ASIC solutions","High-performance protocols","DDR PHY","PCIe","USB","HBM","Verilog","SystemVerilog","Simulation tools","Design flows","Lint","CDC","Synthesis","Static timing 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You&#39;ll work directly with founders and senior leadership in a high-performance environment where your operational decisions materially shape company growth.</p>\n<p><strong>The Role</strong></p>\n<p>We are looking for a builder - someone who has built or scaled an agency, operated inside high-growth startups, or acted as the operational right hand to a founder. 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preferred</li>\n</ul>\n<p><strong>Operational Expertise</strong></p>\n<ul>\n<li>Deep understanding of service delivery economics and profitability</li>\n</ul>\n<ul>\n<li>Strong commercial acumen</li>\n</ul>\n<ul>\n<li>Experience managing cross-functional global teams</li>\n</ul>\n<ul>\n<li>Comfort with ambiguity and rapid change</li>\n</ul>\n<p><strong>Industry Background</strong></p>\n<p>Experience in one or more of the following:</p>\n<p>Info, Ed-Tech, Consulting, SaaS, AI, Digital Agencies, or Tech-enabled service businesses</p>\n<p><strong>Technical Proficiency (Preferred but not required)</strong></p>\n<p>Familiarity with:</p>\n<p>Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards</p>\n<p><strong>Lean / Systems Thinking</strong></p>\n<p>Knowledge of Lean principles, performance management systems, or structured operational frameworks is a plus.</p>\n<p><strong>Strongly Preferred Background</strong></p>\n<ul>\n<li>Former agency owner or operator</li>\n</ul>\n<ul>\n<li>Extensive startup experience</li>\n</ul>\n<ul>\n<li>Experience acting as second-in-command to a founder</li>\n</ul>\n<ul>\n<li>Proven history of scaling service-based businesses</li>\n</ul>\n<ul>\n<li>Experience building operational infrastructure in remote-first environments</li>\n</ul>\n<p><strong>This Role Is Likely Not a Fit If:</strong></p>\n<ul>\n<li>You prefer structured corporate environments</li>\n</ul>\n<ul>\n<li>You require heavy direction to operate</li>\n</ul>\n<ul>\n<li>You are uncomfortable with ambiguity</li>\n</ul>\n<ul>\n<li>You optimize for stability over growth</li>\n</ul>\n<ul>\n<li>You have primarily inherited mature systems rather than built them</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p><strong>What’s In It For You?</strong></p>\n<ul>\n<li>Competitive compensation (negotiable based on experience and impact)</li>\n</ul>\n<ul>\n<li>Performance-based quarterly bonuses</li>\n</ul>\n<ul>\n<li>Equity / share scheme eligibility after 12 months based on performance</li>\n</ul>\n<ul>\n<li>Direct mentorship and exposure to founders</li>\n</ul>\n<ul>\n<li>Remote flexibility</li>\n</ul>\n<ul>\n<li>Relocation to Dubai may be supported for proven high performers once operational impact is demonstrated</li>\n</ul>\n<p><strong>How to Apply</strong></p>\n<p>If you are ready to build, scale, and operate at founder-level intensity — we’d love to hear from you.</p>\n<p>Please submit:</p>\n<ul>\n<li>Your updated resume</li>\n</ul>\n<ul>\n<li>A short cover letter explaining why you are a strong operational fit</li>\n</ul>\n<ul>\n<li>A recorded video answering:</li>\n</ul>\n<ul>\n<li>Why did you apply for this role?</li>\n<li>What operational systems have you personally built or scaled?</li>\n<li>What were your day-to-day operational responsibilities?</li>\n<li>Why do you believe you are suited to operate at Sr. Manager/Director level in a high-growth environment?</li>\n</ul>\n<p>Please highlight what you have personally built, scaled, or transformed operationally.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_decf92a0-394","directApply":true,"hiringOrganization":{"@type":"Organization","name":"AI Acquisition","sameAs":"https://jobs.workable.com","logo":"https://logos.yubhub.co/view.com.png"},"x-apply-url":"https://jobs.workable.com/view/68RDMLfrLrfZL5KEDGgzeJ/remote-operations-manager-in-estonia-at-ai-acquisition","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["operations","startup leadership","agency environments","consulting","SaaS","high-growth businesses","service delivery economics","profitability","commercial acumen","cross-functional global teams","ambiguity","rapid change"],"x-skills-preferred":["Zapier","Make.com","Apollo.io","Smartlead/Instantly","Front.com","automation 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Manager</strong></p>\n<p><strong>at AI Acquisition</strong></p>\n<p><strong>Remote</strong>AustraliaOperations</p>\n<p>Posted 26 days ago</p>\n<p>Share job</p>\n<p><strong>Description</strong></p>\n<p>We are seeking a hands-on Ops Expert to architect and lead our operational infrastructure as we scale.</p>\n<p>This is not a corporate administrator role.</p>\n<p>We are specifically looking for a builder - someone who has built or scaled an agency, operated inside high-growth startups, or acted as the operational right hand to a founder.</p>\n<p>You must be comfortable:</p>\n<ul>\n<li>Creating structure from ambiguity</li>\n</ul>\n<ul>\n<li>Driving accountability across functions</li>\n</ul>\n<ul>\n<li>Translating founder vision into executable operational systems</li>\n</ul>\n<ul>\n<li>Operating in fast-paced, high-change environments</li>\n</ul>\n<p>You will work directly with the founders to design and enforce the systems, reporting structures, and performance standards that support aggressive growth while protecting profitability and delivery quality.</p>\n<p><strong>What You’ll Do</strong></p>\n<ul>\n<li>Architect the company’s operating system — workflows, reporting, accountability frameworks</li>\n</ul>\n<ul>\n<li>Translate founder strategy into operational roadmaps</li>\n</ul>\n<ul>\n<li>Streamline and refine internal systems from the ground up</li>\n</ul>\n<ul>\n<li>Identify bottlenecks early and implement decisive solutions</li>\n</ul>\n<ul>\n<li>Drive cross-functional alignment across delivery, talent, client success, and finance coordination</li>\n</ul>\n<ul>\n<li>Establish KPI dashboards and performance tracking across teams</li>\n</ul>\n<ul>\n<li>Protect margins by optimizing service delivery processes</li>\n</ul>\n<ul>\n<li>Lead and inspire a high-performance global team</li>\n</ul>\n<ul>\n<li>Enforce execution standards and operational discipline</li>\n</ul>\n<ul>\n<li>Build scalable systems that support growth without operational drag</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<p><strong>Experience</strong></p>\n<ul>\n<li>3+ years in operations, startup leadership, agency environments, consulting, SaaS, or high-growth businesses</li>\n</ul>\n<ul>\n<li>Proven track record building operational systems from zero (not just maintaining mature ones)</li>\n</ul>\n<ul>\n<li>Demonstrated experience scaling teams and driving measurable operational outcomes</li>\n</ul>\n<ul>\n<li>Former agency owners, startup operators, or founder right-hand leaders strongly preferred</li>\n</ul>\n<p><strong>Operational Expertise</strong></p>\n<ul>\n<li>Deep understanding of service delivery economics and profitability</li>\n</ul>\n<ul>\n<li>Strong commercial acumen</li>\n</ul>\n<ul>\n<li>Experience managing cross-functional global teams</li>\n</ul>\n<ul>\n<li>Comfort with ambiguity and rapid change</li>\n</ul>\n<p><strong>Industry Background</strong></p>\n<p>Experience in one or more of the following:</p>\n<p>Info, Ed-Tech, Consulting, SaaS, AI, Digital Agencies, or Tech-enabled service businesses</p>\n<p><strong>Technical Proficiency (Preferred but not required)</strong></p>\n<p>Familiarity with:</p>\n<p>Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards</p>\n<p><strong>Lean / Systems Thinking</strong></p>\n<p>Knowledge of Lean principles, performance management systems, or structured operational frameworks is a plus.</p>\n<p><strong>Strongly Preferred Background</strong></p>\n<ul>\n<li>Former agency owner or operator</li>\n</ul>\n<ul>\n<li>Extensive startup experience</li>\n</ul>\n<ul>\n<li>Experience acting as second-in-command to a founder</li>\n</ul>\n<ul>\n<li>Proven history of scaling service-based businesses</li>\n</ul>\n<ul>\n<li>Experience building operational infrastructure in remote-first environments</li>\n</ul>\n<p><strong>This Role Is Likely Not a Fit If:</strong></p>\n<ul>\n<li>You prefer structured corporate environments</li>\n</ul>\n<ul>\n<li>You require heavy direction to operate</li>\n</ul>\n<ul>\n<li>You are uncomfortable with ambiguity</li>\n</ul>\n<ul>\n<li>You optimize for stability over growth</li>\n</ul>\n<ul>\n<li>You have primarily inherited mature systems rather than built them</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p><strong>What’s In It For You?</strong></p>\n<ul>\n<li>Competitive compensation (negotiable based on experience and impact)</li>\n</ul>\n<ul>\n<li>Performance-based quarterly bonuses</li>\n</ul>\n<ul>\n<li>Equity / share scheme eligibility after 12 months based on performance</li>\n</ul>\n<ul>\n<li>Direct mentorship and exposure to founders</li>\n</ul>\n<ul>\n<li>Remote flexibility</li>\n</ul>\n<ul>\n<li>Relocation to Dubai may be supported for proven high performers once operational impact is demonstrated</li>\n</ul>\n<p><strong>How to Apply</strong></p>\n<p>If you are ready to build, scale, and operate at founder-level intensity — we’d love to hear from you.</p>\n<p>Please submit:</p>\n<ul>\n<li>Your updated resume</li>\n</ul>\n<ul>\n<li>A short cover letter explaining why you are a strong operational fit</li>\n</ul>\n<ul>\n<li>A recorded video answering:</li>\n</ul>\n<ul>\n<li>Why did you apply for this role?</li>\n<li>What operational systems have you personally built or scaled?</li>\n<li>What were your day-to-day operational responsibilities?</li>\n<li>Why do you believe you are suited to operate at Sr. Manager/Director level in a high-growth environment?</li>\n</ul>\n<p>Please highlight what you have personally built, scaled, or transformed operationally.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_05050297-720","directApply":true,"hiringOrganization":{"@type":"Organization","name":"AI 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agency environments, consulting, SaaS, high-growth businesses, service delivery economics, profitability, commercial acumen, cross-functional global teams, ambiguity, rapid change, Lean principles, performance management systems, structured operational frameworks, Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9f2980db-a80"},"title":"Operations Manager","description":"<p><strong>Operations Manager at AI Acquisition</strong></p>\n<p>We are seeking a hands-on Ops Expert to architect and lead our operational infrastructure as we scale.</p>\n<p><strong>Why Join Us?</strong></p>\n<p>We are a fast-growing, entrepreneurial company operating inside one of the fastest-growing sectors globally. You&#39;ll work directly with founders and senior leadership in a high-performance environment where your operational decisions materially shape company growth.</p>\n<p><strong>The Role</strong></p>\n<p>We are looking for a builder - someone who has built or scaled an agency, operated inside high-growth startups, or acted as the operational right hand to a founder. You must be comfortable:</p>\n<ul>\n<li>Creating structure from ambiguity</li>\n</ul>\n<ul>\n<li>Driving accountability across functions</li>\n</ul>\n<ul>\n<li>Translating founder vision into executable operational systems</li>\n</ul>\n<ul>\n<li>Operating in fast-paced, high-change environments</li>\n</ul>\n<p>You will work directly with the founders to design and enforce the systems, reporting structures, and performance standards that support aggressive growth while protecting profitability and delivery quality.</p>\n<p><strong>What You&#39;ll Do</strong></p>\n<ul>\n<li>Architect the company’s operating system — workflows, reporting, accountability frameworks</li>\n</ul>\n<ul>\n<li>Translate founder strategy into operational roadmaps</li>\n</ul>\n<ul>\n<li>Streamline and refine internal systems from the ground up</li>\n</ul>\n<ul>\n<li>Identify bottlenecks early and implement decisive solutions</li>\n</ul>\n<ul>\n<li>Drive cross-functional alignment across delivery, talent, client success, and finance coordination</li>\n</ul>\n<ul>\n<li>Establish KPI dashboards and performance tracking across teams</li>\n</ul>\n<ul>\n<li>Protect margins by optimizing service delivery processes</li>\n</ul>\n<ul>\n<li>Lead and inspire a high-performance global team</li>\n</ul>\n<ul>\n<li>Enforce execution standards and operational discipline</li>\n</ul>\n<ul>\n<li>Build scalable systems that support growth without operational drag</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<p><strong>Experience</strong></p>\n<ul>\n<li>3+ years in operations, startup leadership, agency environments, consulting, SaaS, or high-growth businesses</li>\n</ul>\n<ul>\n<li>Proven track record building operational systems from zero (not just maintaining mature ones)</li>\n</ul>\n<ul>\n<li>Demonstrated experience scaling teams and driving measurable operational outcomes</li>\n</ul>\n<ul>\n<li>Former agency owners, startup operators, or founder right-hand leaders strongly preferred</li>\n</ul>\n<p><strong>Operational Expertise</strong></p>\n<ul>\n<li>Deep understanding of service delivery economics and profitability</li>\n</ul>\n<ul>\n<li>Strong commercial acumen</li>\n</ul>\n<ul>\n<li>Experience managing cross-functional global teams</li>\n</ul>\n<ul>\n<li>Comfort with ambiguity and rapid change</li>\n</ul>\n<p><strong>Industry Background</strong></p>\n<p>Experience in one or more of the following:</p>\n<p>Info, Ed-Tech, Consulting, SaaS, AI, Digital Agencies, or Tech-enabled service businesses</p>\n<p><strong>Technical Proficiency (Preferred but not required)</strong></p>\n<p>Familiarity with:</p>\n<p>Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards</p>\n<p><strong>Lean / Systems Thinking</strong></p>\n<p>Knowledge of Lean principles, performance management systems, or structured operational frameworks is a plus.</p>\n<p><strong>Strongly Preferred Background</strong></p>\n<ul>\n<li>Former agency owner or operator</li>\n</ul>\n<ul>\n<li>Extensive startup experience</li>\n</ul>\n<ul>\n<li>Experience acting as second-in-command to a founder</li>\n</ul>\n<ul>\n<li>Proven history of scaling service-based businesses</li>\n</ul>\n<ul>\n<li>Experience building operational infrastructure in remote-first environments</li>\n</ul>\n<p><strong>This Role Is Likely Not a Fit If:</strong></p>\n<ul>\n<li>You prefer structured corporate environments</li>\n</ul>\n<ul>\n<li>You require heavy direction to operate</li>\n</ul>\n<ul>\n<li>You are uncomfortable with ambiguity</li>\n</ul>\n<ul>\n<li>You optimize for stability over growth</li>\n</ul>\n<ul>\n<li>You have primarily inherited mature systems rather than built them</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p><strong>What’s In It For You?</strong></p>\n<ul>\n<li>Competitive compensation (negotiable based on experience and impact)</li>\n</ul>\n<ul>\n<li>Performance-based quarterly bonuses</li>\n</ul>\n<ul>\n<li>Equity / share scheme eligibility after 12 months based on performance</li>\n</ul>\n<ul>\n<li>Direct mentorship and exposure to founders</li>\n</ul>\n<ul>\n<li>Remote flexibility</li>\n</ul>\n<ul>\n<li>Relocation to Dubai may be supported for proven high performers once operational impact is demonstrated</li>\n</ul>\n<p><strong>How to Apply</strong></p>\n<p>If you are ready to build, scale, and operate at founder-level intensity — we’d love to hear from you.</p>\n<p>Please submit:</p>\n<ul>\n<li>Your updated resume</li>\n</ul>\n<ul>\n<li>A short cover letter explaining why you are a strong operational fit</li>\n</ul>\n<ul>\n<li>A recorded video answering:</li>\n</ul>\n<ul>\n<li>Why did you apply for this role?</li>\n<li>What operational systems have you personally built or scaled?</li>\n<li>What were your day-to-day operational responsibilities?</li>\n<li>Why do you believe you are suited to operate at Sr. Manager/Director level in a high-growth environment?</li>\n</ul>\n<p>Please highlight what you have personally built, scaled, or transformed operationally.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9f2980db-a80","directApply":true,"hiringOrganization":{"@type":"Organization","name":"AI Acquisition","sameAs":"https://jobs.workable.com","logo":"https://logos.yubhub.co/view.com.png"},"x-apply-url":"https://jobs.workable.com/view/gexvZvPtjP3UoJfvSERKJE/remote-operations-manager-in-south-africa-at-ai-acquisition","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["operations","startup leadership","agency environments","consulting","SaaS","high-growth businesses","service delivery economics","profitability","commercial acumen","cross-functional global teams","ambiguity","rapid change"],"x-skills-preferred":["Zapier","Make.com","Apollo.io","Smartlead/Instantly","Front.com","automation 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You’ll work directly with founders and senior leadership in a high-performance environment where your operational decisions materially shape company growth.</p>\n<p><strong>The Role</strong></p>\n<p>We are looking for a builder - someone who has built or scaled an agency, operated inside high-growth startups, or acted as the operational right hand to a founder. You must be comfortable:</p>\n<ul>\n<li>Creating structure from ambiguity</li>\n</ul>\n<ul>\n<li>Driving accountability across functions</li>\n</ul>\n<ul>\n<li>Translating founder vision into executable operational systems</li>\n</ul>\n<ul>\n<li>Operating in fast-paced, high-change environments</li>\n</ul>\n<p>You will work directly with the founders to design and enforce the systems, reporting structures, and performance standards that support aggressive growth while protecting profitability and delivery quality.</p>\n<p><strong>What You’ll Do</strong></p>\n<ul>\n<li>Architect the company’s operating system — workflows, reporting, accountability frameworks</li>\n</ul>\n<ul>\n<li>Translate founder strategy into operational roadmaps</li>\n</ul>\n<ul>\n<li>Streamline and refine internal systems from the ground up</li>\n</ul>\n<ul>\n<li>Identify bottlenecks early and implement decisive solutions</li>\n</ul>\n<ul>\n<li>Drive cross-functional alignment across delivery, talent, client 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or operator</li>\n</ul>\n<ul>\n<li>Extensive startup experience</li>\n</ul>\n<ul>\n<li>Experience acting as second-in-command to a founder</li>\n</ul>\n<ul>\n<li>Proven history of scaling service-based businesses</li>\n</ul>\n<ul>\n<li>Experience building operational infrastructure in remote-first environments</li>\n</ul>\n<p><strong>This Role Is Likely Not a Fit If:</strong></p>\n<ul>\n<li>You prefer structured corporate environments</li>\n</ul>\n<ul>\n<li>You require heavy direction to operate</li>\n</ul>\n<ul>\n<li>You are uncomfortable with ambiguity</li>\n</ul>\n<ul>\n<li>You optimize for stability over growth</li>\n</ul>\n<ul>\n<li>You have primarily inherited mature systems rather than built them</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p><strong>What’s In It For You?</strong></p>\n<ul>\n<li>Competitive compensation (negotiable based on experience and impact)</li>\n</ul>\n<ul>\n<li>Performance-based quarterly bonuses</li>\n</ul>\n<ul>\n<li>Equity / share scheme eligibility after 12 months based on performance</li>\n</ul>\n<ul>\n<li>Direct mentorship and exposure to founders</li>\n</ul>\n<ul>\n<li>Remote flexibility</li>\n</ul>\n<ul>\n<li>Relocation to Dubai may be supported for proven high performers once operational impact is demonstrated</li>\n</ul>\n<p><strong>How to Apply</strong></p>\n<p>If you are ready to build, scale, and operate at founder-level intensity — we’d love to hear from you.</p>\n<p>Please submit:</p>\n<ul>\n<li>Your updated resume</li>\n</ul>\n<ul>\n<li>A short cover letter explaining why you are a strong operational fit</li>\n</ul>\n<ul>\n<li>A recorded video answering:</li>\n</ul>\n<ul>\n<li>Why did you apply for this role?</li>\n<li>What operational systems have you personally built or scaled?</li>\n<li>What were your day-to-day operational responsibilities?</li>\n<li>Why do you believe you are suited to operate at Sr. Manager/Director level in a high-growth environment?</li>\n</ul>\n<p>Please highlight what you have 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Manager</strong></p>\n<p>We are seeking a hands-on Ops Expert to architect and lead our operational infrastructure as we scale.</p>\n<p>This is not a corporate administrator role. We are specifically looking for a builder - someone who has built or scaled an agency, operated inside high-growth startups, or acted as the operational right hand to a founder.</p>\n<p>You must be comfortable:</p>\n<ul>\n<li>Creating structure from ambiguity</li>\n</ul>\n<ul>\n<li>Driving accountability across functions</li>\n</ul>\n<ul>\n<li>Translating founder vision into executable operational systems</li>\n</ul>\n<ul>\n<li>Operating in fast-paced, high-change environments</li>\n</ul>\n<p>You will work directly with the founders to design and enforce the systems, reporting structures, and performance standards that support aggressive growth while protecting profitability and delivery quality.</p>\n<p><strong>What You’ll Do</strong></p>\n<ul>\n<li>Architect the company’s operating system — workflows, reporting, accountability frameworks</li>\n</ul>\n<ul>\n<li>Translate founder strategy into operational roadmaps</li>\n</ul>\n<ul>\n<li>Streamline and refine internal systems from the ground up</li>\n</ul>\n<ul>\n<li>Identify bottlenecks early and implement decisive solutions</li>\n</ul>\n<ul>\n<li>Drive cross-functional alignment across delivery, talent, client success, and finance coordination</li>\n</ul>\n<ul>\n<li>Establish KPI dashboards and performance tracking across teams</li>\n</ul>\n<ul>\n<li>Protect margins by optimizing service delivery processes</li>\n</ul>\n<ul>\n<li>Lead and inspire a high-performance global team</li>\n</ul>\n<ul>\n<li>Enforce execution standards and operational discipline</li>\n</ul>\n<ul>\n<li>Build scalable systems that support growth without operational drag</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<p><strong>Experience</strong></p>\n<ul>\n<li>3+ years in operations, startup leadership, agency environments, consulting, SaaS, or high-growth businesses</li>\n</ul>\n<ul>\n<li>Proven track record building operational systems from zero (not just maintaining mature ones)</li>\n</ul>\n<ul>\n<li>Demonstrated experience scaling teams and driving measurable operational outcomes</li>\n</ul>\n<ul>\n<li>Former agency owners, startup operators, or founder right-hand leaders strongly preferred</li>\n</ul>\n<p><strong>Operational Expertise</strong></p>\n<ul>\n<li>Deep understanding of service delivery economics and profitability</li>\n</ul>\n<ul>\n<li>Strong commercial acumen</li>\n</ul>\n<ul>\n<li>Experience managing cross-functional global teams</li>\n</ul>\n<ul>\n<li>Comfort with ambiguity and rapid change</li>\n</ul>\n<p><strong>Industry Background</strong></p>\n<p>Experience in one or more of the following:</p>\n<p>Info, Ed-Tech, Consulting, SaaS, AI, Digital Agencies, or Tech-enabled service businesses</p>\n<p><strong>Technical Proficiency (Preferred but not required)</strong></p>\n<p>Familiarity with:</p>\n<p>Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards</p>\n<p><strong>Lean / Systems Thinking</strong></p>\n<p>Knowledge of Lean principles, performance management systems, or structured operational frameworks is a plus.</p>\n<p><strong>Strongly Preferred Background</strong></p>\n<ul>\n<li>Former agency owner or operator</li>\n</ul>\n<ul>\n<li>Extensive startup experience</li>\n</ul>\n<ul>\n<li>Experience acting as second-in-command to a founder</li>\n</ul>\n<ul>\n<li>Proven history of scaling service-based businesses</li>\n</ul>\n<ul>\n<li>Experience building operational infrastructure in remote-first environments</li>\n</ul>\n<p><strong>This Role Is Likely Not a Fit If:</strong></p>\n<ul>\n<li>You prefer structured corporate environments</li>\n</ul>\n<ul>\n<li>You require heavy direction to operate</li>\n</ul>\n<ul>\n<li>You are uncomfortable with ambiguity</li>\n</ul>\n<ul>\n<li>You optimize for stability over growth</li>\n</ul>\n<ul>\n<li>You have primarily inherited mature systems rather than built them</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p><strong>What’s In It For You?</strong></p>\n<ul>\n<li>Competitive compensation (negotiable based on experience and impact)</li>\n</ul>\n<ul>\n<li>Performance-based quarterly bonuses</li>\n</ul>\n<ul>\n<li>Equity / share scheme eligibility after 12 months based on performance</li>\n</ul>\n<ul>\n<li>Direct mentorship and exposure to founders</li>\n</ul>\n<ul>\n<li>Remote flexibility</li>\n</ul>\n<ul>\n<li>Relocation to Dubai may be supported for proven high performers once operational impact is demonstrated</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9fc1391c-d26","directApply":true,"hiringOrganization":{"@type":"Organization","name":"AI Acquisition","sameAs":"https://jobs.workable.com","logo":"https://logos.yubhub.co/view.com.png"},"x-apply-url":"https://jobs.workable.com/view/4LecgQYLMNbrPyt5FEUucT/remote-operations-manager-in-united-kingdom-at-ai-acquisition","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["operations","startup leadership","agency environments","consulting","SaaS","high-growth businesses","service delivery economics","profitability","commercial acumen","cross-functional global teams","ambiguity","rapid change","Lean principles","performance management systems","structured operational frameworks"],"x-skills-preferred":["Zapier","Make.com","Apollo.io","Smartlead/Instantly","Front.com","automation workflows","KPI dashboards"],"datePosted":"2026-03-09T16:51:39.765Z","jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"Operations","industry":"Technology","skills":"operations, startup leadership, agency environments, consulting, SaaS, high-growth businesses, service delivery economics, profitability, commercial acumen, cross-functional global teams, ambiguity, rapid change, Lean principles, performance management systems, structured operational frameworks, Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d37dfd98-33b"},"title":"Operations Manager","description":"<p><strong>Operations Manager at AI Acquisition</strong></p>\n<p>We are seeking a hands-on Ops Expert to architect and lead our operational infrastructure as we scale.</p>\n<p><strong>Why Join Us?</strong></p>\n<p>We are a fast-growing, entrepreneurial company operating inside one of the fastest-growing sectors globally. You’ll work directly with founders and senior leadership in a high-performance environment where your operational decisions materially shape company growth.</p>\n<p><strong>The Role</strong></p>\n<p>We are looking for a builder - someone who has built or scaled an agency, operated inside high-growth startups, or acted as the operational right hand to a founder. You must be comfortable:</p>\n<ul>\n<li>Creating structure from ambiguity</li>\n</ul>\n<ul>\n<li>Driving accountability across functions</li>\n</ul>\n<ul>\n<li>Translating founder vision into executable operational systems</li>\n</ul>\n<ul>\n<li>Operating in fast-paced, high-change environments</li>\n</ul>\n<p>You will work directly with the founders to design and enforce the systems, reporting structures, and performance standards that support aggressive growth while protecting profitability and delivery quality.</p>\n<p><strong>What You’ll Do</strong></p>\n<ul>\n<li>Architect the company’s operating system — workflows, reporting, accountability frameworks</li>\n</ul>\n<ul>\n<li>Translate founder strategy into operational roadmaps</li>\n</ul>\n<ul>\n<li>Streamline and refine internal systems from the ground up</li>\n</ul>\n<ul>\n<li>Identify bottlenecks early and implement decisive solutions</li>\n</ul>\n<ul>\n<li>Drive cross-functional alignment across delivery, talent, client success, and finance coordination</li>\n</ul>\n<ul>\n<li>Establish KPI dashboards and performance tracking across teams</li>\n</ul>\n<ul>\n<li>Protect margins by optimizing service delivery processes</li>\n</ul>\n<ul>\n<li>Lead and inspire a high-performance global team</li>\n</ul>\n<ul>\n<li>Enforce execution standards and operational discipline</li>\n</ul>\n<ul>\n<li>Build scalable systems that support growth without operational drag</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<p><strong>Experience</strong></p>\n<ul>\n<li>3+ years in operations, startup leadership, agency environments, consulting, SaaS, or high-growth businesses</li>\n</ul>\n<ul>\n<li>Proven track record building operational systems from zero (not just maintaining mature ones)</li>\n</ul>\n<ul>\n<li>Demonstrated experience scaling teams and driving measurable operational outcomes</li>\n</ul>\n<ul>\n<li>Former agency owners, startup operators, or founder right-hand leaders strongly preferred</li>\n</ul>\n<p><strong>Operational Expertise</strong></p>\n<ul>\n<li>Deep understanding of service delivery economics and profitability</li>\n</ul>\n<ul>\n<li>Strong commercial acumen</li>\n</ul>\n<ul>\n<li>Experience managing cross-functional global teams</li>\n</ul>\n<ul>\n<li>Comfort with ambiguity and rapid change</li>\n</ul>\n<p><strong>Industry Background</strong></p>\n<p>Experience in one or more of the following:</p>\n<p>Info, Ed-Tech, Consulting, SaaS, AI, Digital Agencies, or Tech-enabled service businesses</p>\n<p><strong>Technical Proficiency (Preferred but not required)</strong></p>\n<p>Familiarity with:</p>\n<p>Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards</p>\n<p><strong>Lean / Systems Thinking</strong></p>\n<p>Knowledge of Lean principles, performance management systems, or structured operational frameworks is a plus.</p>\n<p><strong>Strongly Preferred Background</strong></p>\n<ul>\n<li>Former agency owner or operator</li>\n</ul>\n<ul>\n<li>Extensive startup experience</li>\n</ul>\n<ul>\n<li>Experience acting as second-in-command to a founder</li>\n</ul>\n<ul>\n<li>Proven history of scaling service-based businesses</li>\n</ul>\n<ul>\n<li>Experience building operational infrastructure in remote-first environments</li>\n</ul>\n<p><strong>This Role Is Likely Not a Fit If:</strong></p>\n<ul>\n<li>You prefer structured corporate environments</li>\n</ul>\n<ul>\n<li>You require heavy direction to operate</li>\n</ul>\n<ul>\n<li>You are uncomfortable with ambiguity</li>\n</ul>\n<ul>\n<li>You optimize for stability over growth</li>\n</ul>\n<ul>\n<li>You have primarily inherited mature systems rather than built them</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p><strong>What’s In It For You?</strong></p>\n<ul>\n<li>Competitive compensation (negotiable based on experience and impact)</li>\n</ul>\n<ul>\n<li>Performance-based quarterly bonuses</li>\n</ul>\n<ul>\n<li>Equity / share scheme eligibility after 12 months based on performance</li>\n</ul>\n<ul>\n<li>Direct mentorship and exposure to founders</li>\n</ul>\n<ul>\n<li>Remote flexibility</li>\n</ul>\n<ul>\n<li>Relocation to Dubai may be supported for proven high performers once operational impact is demonstrated</li>\n</ul>\n<p><strong>How to Apply</strong></p>\n<p>If you are ready to build, scale, and operate at founder-level intensity — we’d love to hear from you.</p>\n<p>Please submit:</p>\n<ul>\n<li>Your updated resume</li>\n</ul>\n<ul>\n<li>A short cover letter explaining why you are a strong operational fit</li>\n</ul>\n<ul>\n<li>A recorded video answering:</li>\n</ul>\n<ul>\n<li>Why did you apply for this role?</li>\n<li>What operational systems have you personally built or scaled?</li>\n<li>What were your day-to-day operational responsibilities?</li>\n<li>Why do you believe you are suited to operate at Sr. Manager/Director level in a high-growth environment?</li>\n</ul>\n<p>Please highlight what you have personally built, scaled, or transformed operationally.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d37dfd98-33b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"AI Acquisition","sameAs":"https://jobs.workable.com","logo":"https://logos.yubhub.co/view.com.png"},"x-apply-url":"https://jobs.workable.com/view/kRhHdHXE4etu3fXCDsNAJH/remote-operations-manager-in-poland-at-ai-acquisition","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["operations","startup leadership","agency environments","consulting","SaaS","high-growth businesses","service delivery economics","profitability","commercial acumen","cross-functional global teams","ambiguity","rapid change"],"x-skills-preferred":["Zapier","Make.com","Apollo.io","Smartlead/Instantly","Front.com","automation workflows","KPI dashboards","Lean principles","performance management systems","structured operational frameworks"],"datePosted":"2026-03-09T16:50:11.085Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Poland"}},"jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"Operations","industry":"Technology","skills":"operations, startup leadership, agency environments, consulting, SaaS, high-growth businesses, service delivery economics, profitability, commercial acumen, cross-functional global teams, ambiguity, rapid change, Zapier, Make.com, Apollo.io, Smartlead/Instantly, Front.com, automation workflows, KPI dashboards, Lean principles, performance management systems, structured operational frameworks"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3a6efc4b-131"},"title":"ASIC Security Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>We are seeking a highly skilled ASIC Security Staff Engineer to join our team at Synopsys. As a key member of our Security IP team, you will be responsible for designing and implementing secure ASIC solutions for various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Designing and implementing RTL in Verilog and/or System Verilog for Security Applications.</li>\n<li>Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM.</li>\n<li>Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification.</li>\n<li>Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions.</li>\n<li>Working within an international team setup, contributing to global projects.</li>\n<li>Ensuring adherence to high-quality standards and best practices in digital design and verification processes.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhancing the performance and security of our IP cores and subsystems.</li>\n<li>Contributing to the rapid integration of advanced capabilities into SoCs, meeting unique performance, power, and size requirements.</li>\n<li>Reducing time-to-market for differentiated products with minimized risk.</li>\n<li>Driving innovation in the fields of CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive.</li>\n<li>Collaborating with a diverse team to deliver leading-edge solutions that shape the future of technology.</li>\n<li>Playing a key role in maintaining Synopsys&#39; position as a leader in chip design and software security.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>3+ years Experience in RTL design of hardware IP components.</li>\n<li>Proficiency in ASIC verification using System Verilog, UVM, and or Verilog</li>\n<li>Ability to create detailed specifications for test environments.</li>\n<li>MSc or PhD in Electrical Engineering or Computer Science.</li>\n<li>Strong understanding of IC Design flows and exceptional problem-solving and debugging skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A strong communicator with excellent written and verbal skills.</li>\n<li>A team player who thrives in a collaborative international environment.</li>\n<li>An innovative thinker who is passionate about technology and continuous improvement.</li>\n<li>Detail-oriented and committed to delivering high-quality work.</li>\n<li>Adaptable and able to manage multiple tasks effectively.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be joining the Security IP team in Eindhoven at the High Tech Campus, a dynamic and innovative group dedicated to extending the Security IP business in markets such as CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive. Our team is composed of experts in hardware and software security, working together to develop state-of-the-art IP cores and subsystems. We value collaboration, creativity, and a commitment to excellence.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3a6efc4b-131","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/eindhoven/asic-security-staff-engineer/44408/91940192192","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","Verilog","System Verilog","UVM","Formal verification","IC Design flows","Problem-solving and debugging skills"],"x-skills-preferred":["ASIC verification","Digital hardware Security IP cores and subsystems","Embedded hardware/software IP solutions"],"datePosted":"2026-03-09T11:09:25.644Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eindhoven"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog, System Verilog, UVM, Formal verification, IC Design flows, Problem-solving and debugging skills, ASIC verification, Digital hardware Security IP cores and subsystems, Embedded hardware/software IP solutions"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e4d64b54-9d8"},"title":"Senior Staff R&D Engineer (SoC)","description":"<p><strong>Overview</strong></p>\n<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15159</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/04/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an enthusiastic and detail-oriented SoC RTL Performance Verification Engineer with a passion for developing and deploying verification solutions for System on Chip (SoC) designs. With a strong background in RTL hardware design and verification, you excel in using industry-standard languages like Verilog and SystemVerilog. Your expertise in developing ZeBu emulation-based verification IP (transactor) and solutions makes you a valuable asset to any team. You thrive in dynamic environments, tackling complex problems creatively while adhering to company policies and procedures. Your communication skills are exemplary, allowing you to work effectively with both internal teams and external clients. With a deep understanding of protocols like AMBA AXI/CHI and proficiency in UNIX and scripting, you bring a comprehensive skill set to the table, ready to make an impact in the rapidly evolving field of SoC performance verification.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Developing SoC Performance Validation (PV) flow and components (transactor model and CI/CD automation) on ZeBu emulator.</li>\n</ul>\n<ul>\n<li>Creating emulation-based transactor and solutions using SystemVerilog and C++.</li>\n</ul>\n<ul>\n<li>Providing technical support and guidance to customers during the deployment of the ZeBu emulator.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Ensuring the reliability and performance of customer SoC designs through rigorous validation processes.</li>\n</ul>\n<ul>\n<li>Enhancing the capabilities of the ZeBu emulator transactor to meet evolving industry standards and customer needs.</li>\n</ul>\n<ul>\n<li>Contributing to the development of innovative SoC PV solutions that set Synopsys apart from competitors.</li>\n</ul>\n<ul>\n<li>Supporting customers in achieving their design and performance goals, thereby strengthening Synopsys&#39; market position.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in SoC PV methodologies, leading to more efficient and effective processes.</li>\n</ul>\n<ul>\n<li>Fostering collaboration and knowledge sharing within the team, enhancing overall performance and innovation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or a related field (RTL design/verification) with a minimum of 12+ years of experience.</li>\n</ul>\n<ul>\n<li>A solid understanding of the SoC architecture among HW IPs, AMBA system buses, and LPDDR memory controllers in a mobile AP.</li>\n</ul>\n<ul>\n<li>Proficiency in developing emulation-based transactor models and solutions using SystemVerilog and C++.</li>\n</ul>\n<ul>\n<li>Proficiency with UNIX and scripting.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be part of a dynamic and innovative team focused on developing and deploying cutting-edge verification solutions for SoC designs. The team values collaboration, continuous learning, and a commitment to excellence, working together to drive technological advancements and deliver exceptional results for our customers.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e4d64b54-9d8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/seongnam-si/senior-staff-r-and-d-engineer-soc/44408/91427515184","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design/verification","Verilog","SystemVerilog","ZeBu emulator","UNIX","scripting"],"x-skills-preferred":["AMBA AXI/CHI","LPDDR memory controllers"],"datePosted":"2026-03-09T11:07:14.173Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Seongnam-si"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design/verification, Verilog, SystemVerilog, ZeBu emulator, UNIX, scripting, AMBA AXI/CHI, LPDDR memory controllers"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9a8cc13a-0a3"},"title":"Staff Applications Engineer, Digital Implementation","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15411</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff Applications Engineer, Digital Implementation</li>\n</ul>\n<ul>\n<li>Staff AE – RTL-to-GDS Solutions</li>\n</ul>\n<ul>\n<li>Senior Digital Design Flow Engineer</li>\n</ul>\n<ul>\n<li>Customer Success Engineer – Physical Design</li>\n</ul>\n<ul>\n<li>Staff Field Applications Engineer – EDA</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an experienced engineering professional with a passion for digital design flows and a drive to see customers succeed. You thrive at the intersection of deep technical problem-solving and collaborative partnership, always eager to tackle challenges that span RTL handoff to physical signoff. Your expertise in RTL-to-GDS flows allows you to confidently lead technical engagements, while your curiosity and commitment to learning keep you at the forefront of evolving methodologies and tools.</p>\n<p>You are self-driven, organized, and able to independently manage complex projects, always maintaining a strong sense of ownership over deliverables. You communicate clearly and effectively, whether you are guiding customers through best practices, collaborating with R&amp;D, or translating customer requirements into actionable feature requests. Your analytical skills help you quickly understand diverse customer scenarios, and your adaptability enables you to develop innovative solutions for unique challenges.</p>\n<p>You value teamwork and are motivated by the opportunity to influence both customer success and product evolution. You believe in continuous improvement, for yourself and for the solutions you support. If you are eager to make a tangible impact on the next generation of digital design, we invite you to join us.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Serve as the primary technical advisor for customers implementing Synopsys’ RTL-to-GDS (R2G) solution, including synthesis, physical implementation, and signoff flows.</li>\n</ul>\n<ul>\n<li>Lead customer onboarding, technical evaluations, benchmarking, and full production deployments across advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Analyze complex customer challenges and deliver tailored solutions using deep expertise in digital implementation flows.</li>\n</ul>\n<ul>\n<li>Develop and optimize RTL-to-GDS methodologies, including floorplanning, placement, clock tree synthesis, routing, and signoff correlation.</li>\n</ul>\n<ul>\n<li>Collaborate with global Applications Engineering, R&amp;D, and Product Management teams to enhance methodologies and influence tool development.</li>\n</ul>\n<ul>\n<li>Provide technical guidance and best practices to customers while ensuring successful project delivery and adoption of Synopsys tools.</li>\n</ul>\n<ul>\n<li>Troubleshoot and triage tool issues, provide reproducible testcases, and advocate for customer-driven enhancements.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive successful adoption and expansion of Synopsys’ digital implementation toolchain across key customer accounts.</li>\n</ul>\n<ul>\n<li>Enable customers to achieve optimal PPA (Power, Performance, Area) and signoff closure on complex projects.</li>\n</ul>\n<ul>\n<li>Serve as the voice of the customer, directly influencing tool enhancements and product roadmap evolution.</li>\n</ul>\n<ul>\n<li>Accelerate customer productivity and innovation by delivering robust methodologies and automation solutions.</li>\n</ul>\n<ul>\n<li>Foster long-term, trusted relationships with customers, contributing to Synopsys’ industry leadership and growth.</li>\n</ul>\n<ul>\n<li>Enhance cross-functional collaboration within Synopsys, driving continuous improvement in product quality and support.</li>\n</ul>\n<ul>\n<li>Champion best practices and knowledge sharing within the Applications Engineering community.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Proven expertise in RTL-to-GDS flows, including digital synthesis (Design Compiler/Fusion Compiler), physical implementation (ICC2/Fusion Compiler), and static timing analysis (PrimeTime).</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced node design, floorplanning, PPA optimization, and signoff-driven closure.</li>\n</ul>\n<ul>\n<li>Strong proficiency in scripting languages (Tcl, Python, Perl) for flow automation and customization.</li>\n</ul>\n<ul>\n<li>Ability to independently own technical deliverables, lead customer evaluations, and drive production deployments.</li>\n</ul>\n<ul>\n<li>Deep understanding of digital design methodologies, process technology challenges, and EDA tool ecosystems.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Analytical and methodical, able to evaluate diverse customer scenarios and devise effective solutions.</li>\n</ul>\n<ul>\n<li>Exceptional communicator, comfortable engaging with both internal teams and external partners.</li>\n</ul>\n<ul>\n<li>Self-motivated and accountable, thriving with moderate supervision and a high degree of autonomy.</li>\n</ul>\n<ul>\n<li>Collaborative team player, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Customer-focused, energetic, and adaptable to fast-paced, evolving environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic, globally distributed Applications Engineering team at Synopsys, dedicated to driving customer success in digital implementation. Our team works closely with R&amp;D, Product Management, and field engineers to deliver innovative solutions, optimize design flows, and influence product direction. We foster a culture of collaboration, continuous learning, and knowledge sharing, empowering each other to solve complex challenges and achieve excellence for our customers.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine **around the office*</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9a8cc13a-0a3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/penang/staff-applications-engineer-digital-implementation/44408/92092150640","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDS flows","digital synthesis","physical implementation","static timing analysis","advanced node design","floorplanning","PPA optimization","signoff-driven closure","scripting languages","Tcl","Python","Perl","EDA tool ecosystems"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:06:20.254Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Penang, Malaysia"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDS flows, digital synthesis, physical implementation, static timing analysis, advanced node design, floorplanning, PPA optimization, signoff-driven closure, scripting languages, Tcl, Python, Perl, EDA tool ecosystems"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4b33752-a69"},"title":"Application Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.</p>\n<p>You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.</p>\n<p>You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.</p>\n<p>You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.</p>\n<p>The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.</p>\n<p>You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&amp;D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys&#39; reputation as a trusted partner and thought leader in the semiconductor industry.</p>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.</li>\n<li>Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).</li>\n<li>Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place &amp; Route, and timing analysis.</li>\n<li>Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.</li>\n<li>Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.</li>\n<li>Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.</li>\n<li>Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent communicator able to build trust and rapport with diverse stakeholders.</li>\n<li>Analytical thinker with strong troubleshooting and debugging skills.</li>\n<li>Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.</li>\n<li>Highly collaborative team player who thrives in fast-paced, multicultural environments.</li>\n<li>Self-motivated, innovative, and passionate about continuous learning and process improvement.</li>\n<li>Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, expert team within the Silicon Design &amp; Verification business at Synopsys, based in Hyderabad. The team is dedicated to driving customer success in high-impact projects, deploying advanced implementation flows, and shaping the future of silicon design. Collaboration, technical excellence, and a commitment to innovation are at the core of our culture. You’ll work closely with customers, R&amp;D, and field teams to deliver transformative solutions and advance industry-leading technologies.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4b33752-a69","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-staff-engineer/44408/92113189648","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Implementation Methodologies","Physical Design","Synopsys tools","RTL to GDS flows","Synthesis","Place & Route","Timing analysis","Scripting (TCL, Python, Unix, Perl)","Automation","Tool integration","Debugging"],"x-skills-preferred":["STA","Low Power Flows","Design Planning","Customer-facing roles"],"datePosted":"2026-03-09T11:05:14.988Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Implementation Methodologies, Physical Design, Synopsys tools, RTL to GDS flows, Synthesis, Place & Route, Timing analysis, Scripting (TCL, Python, Unix, Perl), Automation, Tool integration, Debugging, STA, Low Power Flows, Design Planning, Customer-facing roles"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_798ace47-ff9"},"title":"Staff Design Verification Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Senior Digital Verification Engineer</strong></p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Developing functional verification environments (test benches) for complex digital design blocks.</li>\n<li>Creating comprehensive test plans and test cases to ensure thorough coverage and robust design validation.</li>\n<li>Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).</li>\n<li>Performing simulations, generating random and focused stimulus, and conducting coverage analysis to verify functionality.</li>\n<li>Building architecture and micro-architecture knowledge of digital blocks under test to drive effective verification strategies.</li>\n<li>Collaborating with cross-functional teams to share insights and resolve issues throughout the pre-silicon verification process.</li>\n<li>Utilizing industry-standard verification tools and methodologies to enhance efficiency and quality.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Ensuring the reliability and performance of high-speed PHY IPs through rigorous pre-silicon functional verification.</li>\n<li>Accelerating product time-to-market by identifying and resolving design issues early in the development cycle.</li>\n<li>Reducing risk for customers by delivering thoroughly verified and differentiated silicon IP solutions.</li>\n<li>Supporting the development of next-generation products that power innovations in AI, 5G, IoT, and more.</li>\n<li>Contributing technical expertise to the team, fostering a culture of continuous improvement and learning.</li>\n<li>Promoting collaboration and knowledge sharing across engineering teams to achieve collective goals.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.</li>\n<li>Background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.</li>\n<li>Proficiency in Verilog, System Verilog, UVM, and netlist simulations.</li>\n<li>Excellent diagnostic and problem-solving skills for debugging and optimizing verification flows.</li>\n<li>Experience with industry-standard development and verification tools and methodologies.</li>\n<li>Familiarity with scripting languages such as Perl, TCL, and Shell scripting (preferred).</li>\n<li>Experience with formal verification, System Verilog Assertions, and code/functional coverage analysis (preferred).</li>\n<li>Knowledge of high-speed interface protocols such as DDR and LPDDR (preferred).</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Analytical thinker with a strong eagerness to learn and grow.</li>\n<li>Dynamic personality, energizing and motivating team members.</li>\n<li>Strong communicator, able to collaborate effectively in diverse environments.</li>\n<li>Self-motivated leader, capable of driving verification activities independently and as part of a team.</li>\n<li>Detail-oriented, ensuring thorough validation and quality in all deliverables.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_798ace47-ff9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/staff-design-verification-engineer/44408/91940192160","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","System Verilog","UVM","netlist simulations","Perl","TCL","Shell scripting","formal verification","System Verilog Assertions","code/functional coverage analysis","high-speed interface protocols"],"x-skills-preferred":["RTL","digital design","verification","architecture","scripting languages","high-speed interface protocols"],"datePosted":"2026-03-09T11:04:17.561Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, System Verilog, UVM, netlist simulations, Perl, TCL, Shell scripting, formal verification, System Verilog Assertions, code/functional coverage analysis, high-speed interface protocols, RTL, digital design, verification, architecture, scripting languages, high-speed interface protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4ed1875c-bd2"},"title":"Physical Design Lead (With STA & Timing Constraints Expertise)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</li>\n<li>Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.</li>\n<li>Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.</li>\n<li>Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power &amp; IR drop signoff to debug and resolve critical implementation bottlenecks.</li>\n<li>Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.</li>\n<li>Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock &amp; reset architecture improvements for enabling high speed timing closure, PPA improvements.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4ed1875c-bd2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/physical-design-lead-with-sta-and-timing-constraints-expertise-13350/44408/88575081136","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$209000-$313000","x-skills-required":["Physical Design","STA","Timing Constraints","RTL-GDSII","Synopsys tools","Scripting","Software skills"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:03:38.501Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, STA, Timing Constraints, RTL-GDSII, Synopsys tools, Scripting, Software skills","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":209000,"maxValue":313000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_48da4c00-386"},"title":"Design Architect (PCIe/CXL Expert)","description":"<p>You are a visionary and highly experienced logic design expert with a passion for building next-generation hardware solutions. With a strong foundation in PCI Express (PCIe) and/or Compute Express Link (CXL) protocols, you thrive in challenging technical environments, pushing the boundaries of what’s possible in high-speed, complex SoC-class platforms. Your background combines deep hands-on expertise in FPGA architecture, RTL design, and hardware validation, making you a go-to leader for mission-critical projects. You excel at architecting robust, production-quality subsystems and are adept at navigating the intricacies of hardware/software co-design and debugging.</p>\n<p>You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.</li>\n<li>Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.</li>\n<li>Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.</li>\n<li>Collaborating with R&amp;D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.</li>\n<li>Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.</li>\n<li>Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.</li>\n<li>Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.</li>\n<li>Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.</li>\n<li>Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.</li>\n<li>Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.</li>\n<li>12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.</li>\n<li>Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.</li>\n<li>7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.</li>\n<li>Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).</li>\n<li>Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.</li>\n<li>Experience in Unix/Linux development environments.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative team player with excellent communication skills and a global mindset.</li>\n<li>Proactive problem solver who thrives in dynamic, fast-paced environments.</li>\n<li>Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.</li>\n<li>Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.</li>\n<li>Adaptable and eager to stay updated with the latest industry trends and technologies.</li>\n<li>Customer-focused, with a dedication to supporting and enabling client success.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&amp;D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_48da4c00-386","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/design-architect-pcie-cxl-expert/44408/92113189568","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["PCIe","CXL","FPGA","RTL design","hardware validation","Unix/Linux development environments","Xilinx FPGA experience","transceiver/SERDES integration","FPGA prototyping flows","SystemVerilog/Verilog","hardware development cycle","simulation","synthesis","timing analysis"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:02:24.768Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"PCIe, CXL, FPGA, RTL design, hardware validation, Unix/Linux development environments, Xilinx FPGA experience, transceiver/SERDES integration, FPGA prototyping flows, SystemVerilog/Verilog, hardware development cycle, simulation, synthesis, timing analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_82b664ed-78c"},"title":"Staff Application Engineer (Backend)","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>16005</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>03/05/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.</li>\n</ul>\n<ul>\n<li>Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.</li>\n</ul>\n<ul>\n<li>Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.</li>\n</ul>\n<ul>\n<li>Collaborating cross-functionally with customers, R&amp;D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.</li>\n</ul>\n<ul>\n<li>Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.</li>\n</ul>\n<ul>\n<li>Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.</li>\n</ul>\n<ul>\n<li>Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&amp;D on new feature development.</li>\n</ul>\n<ul>\n<li>Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.</li>\n</ul>\n<ul>\n<li>Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.</li>\n</ul>\n<ul>\n<li>Elevate the technical capabilities of the application engineering team through mentorship and cross-training.</li>\n</ul>\n<ul>\n<li>Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.</li>\n</ul>\n<ul>\n<li>Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&amp;R tools (Fusion Compiler, ICC2, or similar).</li>\n</ul>\n<ul>\n<li>Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.</li>\n</ul>\n<ul>\n<li>Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.</li>\n</ul>\n<ul>\n<li>Outstanding verbal and written communication, presentation, and customer interaction skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.</li>\n</ul>\n<ul>\n<li>Analytical thinker with a problem-solving mindset and a passion for continuous improvement.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in the face of evolving customer requirements and technology landscapes.</li>\n</ul>\n<ul>\n<li>Strong organizational skills, able to manage multiple projects and priorities with poise.</li>\n</ul>\n<ul>\n<li>Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&amp;D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_82b664ed-78c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-application-engineer-backend/44408/92463617216","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDSII flows","industry-leading EDA tools","physical synthesis","timing closure","clock tree synthesis (CTS)","routing at advanced technology nodes","Tcl and Python scripting","backend P&R tools","Fusion Compiler","ICC2"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:22:03.259Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDSII flows, industry-leading EDA tools, physical synthesis, timing closure, clock tree synthesis (CTS), routing at advanced technology nodes, Tcl and Python scripting, backend P&R tools, Fusion Compiler, ICC2"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_517e3008-238"},"title":"Physical Design Engineer","description":"<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$266K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.</p>\n<p>You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Develop, build and own tools, flows and methodologies for physical implementation</li>\n<li>Own physical implementation of floorplan blocks from floorplanning to final signoff</li>\n<li>Collaborate with RTL designers to drive optimal block implementation solutions</li>\n<li>Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners</li>\n</ul>\n<p><strong>Qualifications:</strong></p>\n<ul>\n<li>BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development</li>\n<li>Demonstrated success in taping out complex silicon designs</li>\n<li>Hands-on experience with block physical implementation and PPA convergence</li>\n<li>Strong coding experience with python, bazel, TCL</li>\n<li>Strong experience building physical design tools, flows and methodologies</li>\n<li>Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.</li>\n<li>Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation</li>\n</ul>\n<p><strong>Bonus:</strong></p>\n<ul>\n<li>Experience with AI or HPC-focused chips</li>\n<li>Experience with optimizing PPA for high performance compute cores</li>\n<li>Hands-on experience with top-level design methodologies</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_517e3008-238","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/5a265d2b-683f-4cea-9b69-8e137e704ab3","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$266K – $445K","x-skills-required":["physical design","methodology development","python","bazel","TCL","EDA vendors","ASIC partners","microarchitecture","RTL design","physical design","circuit design","physical verification","timing closure"],"x-skills-preferred":["AI or HPC-focused chips","optimizing PPA for high performance compute cores","top-level design methodologies"],"datePosted":"2026-03-06T18:41:49.725Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, methodology development, python, bazel, TCL, EDA vendors, ASIC partners, microarchitecture, RTL design, physical design, circuit design, physical verification, timing closure, AI or HPC-focused chips, optimizing PPA for high performance compute cores, top-level design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":266000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_568dcff2-ed1"},"title":"RTL & Co-design Engineer (junior)","description":"<p><strong>RTL &amp; Co-design Engineer (junior)</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems</li>\n</ul>\n<ul>\n<li>Contribute to architectural studies including performance modeling and feasibility analysis.</li>\n</ul>\n<ul>\n<li>Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.</li>\n</ul>\n<ul>\n<li>Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.</li>\n</ul>\n<ul>\n<li>Build and review performance and functional models to validate design intent.</li>\n</ul>\n<ul>\n<li>Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.</li>\n</ul>\n<p><strong><strong>You Might Thrive In This Role If You Have:</strong></strong></p>\n<ul>\n<li>Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.</li>\n</ul>\n<ul>\n<li>Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.</li>\n</ul>\n<ul>\n<li>Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.</li>\n</ul>\n<ul>\n<li>Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.</li>\n</ul>\n<ul>\n<li>Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.</li>\n</ul>\n<ul>\n<li>Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.</li>\n</ul>\n<ul>\n<li>Passion for building industry-leading massive-scale hardware systems.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_568dcff2-ed1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/77b815de-b7c5-4b87-8582-e8c752aea849","x-work-arrangement":"hybrid","x-experience-level":"junior","x-job-type":"full-time","x-salary-range":"$225K – $445K • Offers Equity","x-skills-required":["RTL","Verilog","SystemVerilog","Computer Architecture","AI/ML Hardware–Software Co-design","Workload Analysis","Dataflow Mapping","Accelerator Algorithm Optimization","Hardware Design Models","Architectural Simulators","Industry-standard Design Tools","Lint","CDC/RDC","Synthesis","STA","Methodologies"],"x-skills-preferred":[],"datePosted":"2026-03-06T18:39:06.360Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL, Verilog, SystemVerilog, Computer Architecture, AI/ML Hardware–Software Co-design, Workload Analysis, Dataflow Mapping, Accelerator Algorithm Optimization, Hardware Design Models, Architectural Simulators, Industry-standard Design Tools, Lint, CDC/RDC, Synthesis, STA, Methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":225000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e8eef588-4b1"},"title":"Technical Deployment Lead, Semiconductors","description":"<p><strong>Technical Deployment Lead, Semiconductors</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Location Type</strong></p>\n<p>Hybrid</p>\n<p><strong>Department</strong></p>\n<p>Model Deployment for Business</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$198K – $335K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p><strong>About the team</strong></p>\n<p>OpenAI’s Forward Deployed Engineering (FDE) team turns research breakthroughs into production-grade systems. We embed deeply with customers to solve high-leverage problems and act as the delivery engine for our most complex large-scale engagements. We move quickly from prototype to production and surface reusable patterns that shape our platform. We operate at the intersection of deployment and development – working closely with OpenAI Research, Product and Partnerships.</p>\n<p><strong>About the Role</strong></p>\n<p>As a Technical Deployment Lead (TDL), you will define how OpenAI delivers complex systems to Semiconductor customers. You will own how solutions are scoped, built, shipped, and adopted across high-value engineering workflows such as RTL design, verification, and physical implementation. You’ll translate business outcomes into a technical plan, run day-to-day execution across FDEs, Researchers, and Customer Engineers, and partner with customer teams to ensure delivery supports their goals.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li><strong>Own the technical delivery plan</strong> for multiple interdependent work streams, translating customer objectives into a roadmap with milestones, dependencies, and acceptance criteria.</li>\n</ul>\n<ul>\n<li><strong>Run day-to-day engineering execution by</strong> tracking and driving delivery across OpenAI FDE and customer teams. Keep progress unblocked and sequenced. Make real-time trade-offs on scope and priority to protect the critical path.</li>\n</ul>\n<ul>\n<li><strong>Embed with Semiconductor customer teams to land production deployments and drive adoption.</strong> Map workflows, shape tools/integrations, and translate requirements into a delivery plan.</li>\n</ul>\n<ul>\n<li><strong>Shape production deployments</strong> that integrate with customer infrastructure, data systems, and engineering toolchains, including export-controlled environments.</li>\n</ul>\n<ul>\n<li><strong>Partner with Product and Research</strong> so platform components and research work streams land in time to support deployment goals.</li>\n</ul>\n<ul>\n<li><strong>Codify solution patterns and evals.</strong> Extract reusable patterns and package field signals to improve product and models.</li>\n</ul>\n<ul>\n<li><strong>Own value cases and ROI.</strong> Set impact hypotheses, baselines, and KPIs; run pre-/post-deployment measurement and report to exec sponsors.</li>\n</ul>\n<ul>\n<li>**Help define how OpenAI engages Semiconductor customers</li>\n</ul>\n<p><strong>You’ll thrive in this role if you:</strong></p>\n<ul>\n<li>Bring 7+ years of customer‑facing technical delivery leadership.</li>\n</ul>\n<ul>\n<li>Have deep expertise in Semiconductor workflows, including RTL design, verification, EDA tooling, and physical implementation</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e8eef588-4b1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/ec9950cb-ccb5-4d2b-b49d-0f6a80b03460","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$198K – $335K","x-skills-required":["Technical delivery leadership","Semiconductor workflows","RTL design","Verification","EDA tooling","Physical implementation","Customer-facing technical delivery"],"x-skills-preferred":[],"datePosted":"2026-03-06T18:35:39.407Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Technical delivery leadership, Semiconductor workflows, RTL design, Verification, EDA tooling, Physical implementation, Customer-facing technical delivery","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":198000,"maxValue":335000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c47b3425-297"},"title":"Reliability/DFX Engineer","description":"<p><strong>Reliability/DFX Engineer</strong></p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled cross-stack engineer with deep expertise in making ML systems reliable at scale. This hands-on individual contributor will sit within our hardware team and work closely with chip design, platform design, hardware health, and the broader industry ecosystem to architect, implement, and deploy reliable next-generation AI accelerator systems.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Oversee DFX architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to enhance reliability and fault tolerance. DFX includes design for testability, reliability, availability, and serviceability of high-performance AI hardware.</li>\n</ul>\n<ul>\n<li>Build system-level reliability models grounded in empirical data to guide organization-wide DFX and reliability strategy. This requires a detailed understanding of chip and system architecture, design, implementation, and component-level reliability.</li>\n</ul>\n<ul>\n<li>Collaborate with chip and platform architecture/design teams to explore and implement DFX features, including the specification and implementation of digital/mixed-signal IP, firmware/system software, and DFX methodology (in partnership with engineering teams).</li>\n</ul>\n<ul>\n<li>Partner with hardware health and platform design teams to continuously improve reliability and fault tolerance in NPI and HVM. This includes optimizing operating conditions, designing experiments, and performing data analysis to drive continuous, data-driven improvements across the stack.</li>\n</ul>\n<ul>\n<li>Serve as the DFX/reliability champion and evangelist to align the broader industry ecosystem with OpenAI’s requirements and roadmap.</li>\n</ul>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>BS with 15+ years, MS with 10+ years, or PhD with 3+ years of relevant industry experience focused on reliability across the chip/platform stack.</li>\n</ul>\n<ul>\n<li>Hands-on experience with RTL design and DFT is required; physical implementation and/or silicon ATE experience is preferred.</li>\n</ul>\n<ul>\n<li>Detailed understanding of ML chip and platform architecture and ML workload characteristics is required.</li>\n</ul>\n<ul>\n<li>Strong fundamentals in reliability modeling, with hands-on skills in empirical data analysis.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c47b3425-297","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/b2c5f3d7-5dfd-45f6-a4fa-fa372f5875a5","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$225K – $445K","x-skills-required":["RTL design","DFT","physical implementation","silicon ATE","ML chip and platform architecture","ML workload characteristics","reliability modeling","empirical data analysis"],"x-skills-preferred":["digital/mixed-signal IP","firmware/system software","DFX methodology"],"datePosted":"2026-03-06T18:29:16.196Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, DFT, physical implementation, silicon ATE, ML chip and platform architecture, ML workload characteristics, reliability modeling, empirical data analysis, digital/mixed-signal IP, firmware/system software, DFX methodology","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":225000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d094148d-0e0"},"title":"RTL & Codesign Engineer","description":"<p><strong>Job Posting</strong></p>\n<p><strong>RTL &amp; Codesign Engineer</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems</li>\n</ul>\n<ul>\n<li>Contribute to architectural studies including performance modeling and feasibility analysis.</li>\n</ul>\n<ul>\n<li>Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.</li>\n</ul>\n<ul>\n<li>Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.</li>\n</ul>\n<ul>\n<li>Build and review performance and functional models to validate design intent.</li>\n</ul>\n<ul>\n<li>Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.</li>\n</ul>\n<p><strong><strong>You Might Thrive In This Role If You Have:</strong></strong></p>\n<ul>\n<li>Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.</li>\n</ul>\n<ul>\n<li>Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.</li>\n</ul>\n<ul>\n<li>Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.</li>\n</ul>\n<ul>\n<li>Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.</li>\n</ul>\n<ul>\n<li>Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.</li>\n</ul>\n<ul>\n<li>Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.</li>\n</ul>\n<ul>\n<li>Passion for building industry-leading massive-scale hardware systems.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d094148d-0e0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/31b998a9-f62a-439e-89e4-b51aea6311f7","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$225K – $445K • Offers Equity","x-skills-required":["RTL","Verilog/SystemVerilog","Computer Architecture","AI/ML Hardware–Software Co-design","Workload Analysis","Dataflow Mapping","Accelerator Algorithm Optimization","Industry-standard Design Tools","Lint","CDC/RDC","Synthesis","STA"],"x-skills-preferred":["Hardware Design Models","Architectural Simulators","AI/ML or High-Performance Compute Systems","Cross-functional Collaboration","Problem-solving Skills","Abstraction Layers"],"datePosted":"2026-03-06T18:28:47.631Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL, Verilog/SystemVerilog, Computer Architecture, AI/ML Hardware–Software Co-design, Workload Analysis, Dataflow Mapping, Accelerator Algorithm Optimization, Industry-standard Design Tools, Lint, CDC/RDC, Synthesis, STA, Hardware Design Models, Architectural Simulators, AI/ML or High-Performance Compute Systems, Cross-functional Collaboration, Problem-solving Skills, Abstraction Layers","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":225000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_46bb9922-091"},"title":"ML Research Engineer - Hardware Codesign","description":"<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$185K – $455K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re seeking a Research-Hardware Codesign Engineer to operate at the boundary between model research and silicon/system architecture. You’ll help shape the numerics, architecture, and technology bets of future OpenAI silicon in collaboration with both Research and Hardware.</p>\n<p>Your work will include debugging gaps between rooflines and reality, writing quantization kernels, derisking numerics via model evals, quantifying system architecture tradeoffs, and implementing novel numeric RTL. This is a hands-on role for people who go looking for hard problems, get to ground truth, and drive it to production. Strong prioritization and clear, honest communication are essential.</p>\n<p>Location: San Francisco, CA (Hybrid: 3 days/week onsite)</p>\n<p>Relocation assistance available.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Build on our roofline simulator to track evolving workloads, and deliver analyses that quantify the impact of system architecture decisions and support technology pathfinding.</li>\n</ul>\n<ul>\n<li>Debug gaps between performance simulation and real measurements; clearly communicate root cause, bottlenecks, and invalid assumptions.</li>\n</ul>\n<ul>\n<li>Write emulation kernels for low-precision numerics and lossy compression schemes, and get Research the information they need to trade efficiency with model quality.</li>\n</ul>\n<ul>\n<li>Prototype numerics modules by pushing RTL through synthesis; hand off novel numerics cleanly, or occasionally own an RTL module end-to-end.</li>\n</ul>\n<ul>\n<li>Proactively pull in new ML workloads, prototype them with rooflines and/or functional simulation, and drive initial evaluation of new opportunities or risks.</li>\n</ul>\n<ul>\n<li>Understand the whole picture from ML science to hardware optimization, and slice this end-to-end objective into near-term deliverables.</li>\n</ul>\n<ul>\n<li>Build ad-hoc collaborations across teams with very different goals and areas of expertise, and keep progress unblocked.</li>\n</ul>\n<ul>\n<li>Communicate design tradeoffs clearly with explicit assumptions and confidence levels; produce a trail of evidence that enables confident execution.</li>\n</ul>\n<p><strong><strong>You Will Thrive in this Role if:</strong></strong></p>\n<ul>\n<li>An exceptional track record of high-quality technical output, and a bias for shipping a prototype now and iterating later in the absence of clear requirements.</li>\n</ul>\n<ul>\n<li>Strong Python, and C++ or Rust, with a cautious attitude toward correctness and an intuition for clean extensibility.</li>\n</ul>\n<ul>\n<li>Experience writing Triton, CUDA, or similar, and an understanding of the resulting mapping of tensor ops to functional units.</li>\n</ul>\n<ul>\n<li>Working knowledge of PyTorch or JAX; experience in large ML codebases is a plus.</li>\n</ul>\n<ul>\n<li>Practical understanding of floating point numerics, the ML tradeoffs of reduced precision, and the current state of the art in model quantization.</li>\n</ul>\n<ul>\n<li>Deep understanding of transformer models, and strong intuition for transformer rooflines and the tradeoffs of sharded training and inference in large-scale ML systems.</li>\n</ul>\n<ul>\n<li>Experience writing RTL (especially for floating point logic) and understanding of PPA tradeoffs is a plus.</li>\n</ul>\n<ul>\n<li>Strong cross-functional communication (e.g. across ML researchers and hardware engineers); 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The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong></p>\n<p>You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems.</p>\n<p><strong>In this role you will:</strong></p>\n<ul>\n<li>Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.</li>\n</ul>\n<ul>\n<li>Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.</li>\n</ul>\n<ul>\n<li>Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.</li>\n</ul>\n<ul>\n<li>Work closely with designers and verification engineers to turn real pain points into durable tools.</li>\n</ul>\n<ul>\n<li>Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.</li>\n</ul>\n<ul>\n<li>Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts.</li>\n</ul>\n<ul>\n<li>Help enable PPA optimization loops by building analysis and automation around area, timing, and power tradeoffs, and by improving tooling that impacts those outcomes.</li>\n</ul>\n<p><strong>You might thrive in this role if:</strong></p>\n<ul>\n<li>Demonstrated ability to build and maintain software (projects, internships, research, open source, or equivalent experience).</li>\n</ul>\n<ul>\n<li>Strong CS fundamentals: data structures, algorithms, debugging, and software design.</li>\n</ul>\n<ul>\n<li>Proficiency in at least one of Rust, C++, or Python (and willingness to learn the rest).</li>\n</ul>\n<ul>\n<li>Familiarity with digital design concepts and the ability to read RTL (Verilog/SystemVerilog) or equivalent hardware descriptions.</li>\n</ul>\n<ul>\n<li>Familiarity with compiler or IR-based ideas (representations, passes, transformations, lowering), through coursework or projects.</li>\n</ul>\n<ul>\n<li>Comfort operating in ambiguity and iterating quickly with users of your tools.</li>\n</ul>\n<p><strong>Nice to have skills:</strong></p>\n<ul>\n<li>Exposure to compiler and hardware toolchains such as XLS/DSLX, LLVM, Chisel/FIRRTL, CIRCT/MLIR, other novel hardware languages (e.g. HardCaml, SpinalHDL, Spade, PyMTL, Clash, BlueSpec, PyRope)</li>\n</ul>\n<ul>\n<li>Experience with Verilog tooling ecosystems (Yosys/RTLIL, Verilator, Slang) or writing tooling around them.</li>\n</ul>\n<ul>\n<li>Experience with build and test infrastructure (Bazel, CI systems, fuzzing, performance testing).</li>\n</ul>\n<ul>\n<li>Prior work touching synthesis, place and route, static timing analysis, or other PPA-related workflows.</li>\n</ul>\n<p><strong>To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.</strong></p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. 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The successful candidate will be responsible for providing technical guidance and hands-on support to customers integrating Synopsys Interface IP into their ASIC SoC/systems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems</li>\n<li>Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s and/or masters with a minimum 10+yrs of Industry experience or equivalent</li>\n<li>At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)</li>\n<li>Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure</li>\n<li>Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2e9367c2-7d7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/herzliya/serdes-ip-s-applications-engineering-sr-staff-engineer/44408/92304383936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP design","ASIC/SoC integration","customer-facing engineering roles","ASIC design flows","simulation/verification","RTL synthesis","floorplanning","physical design","timing closure","High Speed SerDes IPs","PCIe","ETH","USB"],"x-skills-preferred":[],"datePosted":"2026-03-06T07:38:03.021Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Herzliya, Tel Aviv, Israel"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP design, ASIC/SoC integration, customer-facing engineering roles, ASIC design flows, simulation/verification, RTL synthesis, floorplanning, physical design, timing closure, High Speed SerDes IPs, PCIe, ETH, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_07d0d6b0-9ac"},"title":"RTL Design & Verification Engineer (R&D Engineering, Sr Engineer)","description":"<p>We are seeking a passionate, detail-oriented engineer with an insatiable curiosity for technology and its impact on the world. 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As a Principal SerDes Systems Engineer, you will be responsible for developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.</li>\n<li>Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.</li>\n<li>Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.</li>\n<li>Correlating simulated performance with silicon measurements to ensure accuracy and reliability.</li>\n<li>Providing expert assistance to customers for system-level performance issues and troubleshooting.</li>\n<li>Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development.</li>\n<li>Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>M.Sc. or Ph.D. in Electrical or Computer Engineering.</li>\n<li>Strong experience modeling circuits and systems in MATLAB/Simulink.</li>\n<li>Expertise in designing high-speed analog CMOS circuits.</li>\n<li>Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.</li>\n<li>Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.</li>\n<li>Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).</li>\n<li>Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.</li>\n<li>Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_600601e3-040","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/principal-serdes-systems-engineer/44408/92341044560","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["M.Sc. or Ph.D. in Electrical or Computer Engineering","Strong experience modeling circuits and systems in MATLAB/Simulink","Expertise in designing high-speed analog CMOS circuits"],"x-skills-preferred":["Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering","Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links","Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR)"],"datePosted":"2026-03-06T07:20:35.625Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga, Ontario, Canada"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"M.Sc. or Ph.D. in Electrical or Computer Engineering, Strong experience modeling circuits and systems in MATLAB/Simulink, Expertise in designing high-speed analog CMOS circuits, Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering, Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links, Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_de06399d-688"},"title":"R&D Engineering, Sr Staff Engineer (RTL Design Engineer - FPGA)","description":"<p>Opening. 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interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.</li>\n<li>Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.</li>\n<li>Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.</li>\n<li>Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.</li>\n<li>Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.</li>\n</ul>\n<p><strong>Why you&#39;ll love this role</strong></p>\n<ul>\n<li>Opportunity to work on cutting-edge projects and technologies.</li>\n<li>Collaborative and dynamic work environment.</li>\n<li>Professional growth and development opportunities.</li>\n<li>Recognition and rewards for outstanding performance.</li>\n<li>Comprehensive benefits and compensation package.</li>\n</ul>\n<p><strong>What you&#39;ll need to succeed</strong></p>\n<ul>\n<li>Strong technical skills and knowledge in digital design, verification, and prototyping.</li>\n<li>Excellent problem-solving and debugging skills.</li>\n<li>Strong communication and collaboration skills.</li>\n<li>Ability to work independently and as part of a team.</li>\n<li>Adaptability and flexibility in a fast-paced environment.</li>\n</ul>\n<p><strong>How to apply</strong></p>\n<ul>\n<li>If you&#39;re ready to make a meaningful impact and help shape the next generation of prototyping systems, Synopsys is the place for you.</li>\n<li>Apply now to join our team of talented engineers and contribute to the development of industry-leading prototyping solutions.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>Time away, including company holidays, ETO, and FTO programs.</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.</li>\n<li>ESPP, with a 15% discount on Synopsys common stock.</li>\n<li>Retirement plans, varying by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p><strong>How we hire</strong></p>\n<ul>\n<li>We&#39;re proud to be an equal opportunities employer and welcome applications from diverse candidates.</li>\n<li>Our hiring process typically involves a phone screen, followed by an interview with the hiring team.</li>\n<li>We&#39;re committed to providing a supportive and inclusive work environment, where everyone has the opportunity to grow and succeed.</li>\n</ul>\n<p><strong>Join our team</strong></p>\n<ul>\n<li>If you&#39;re passionate about innovation and technology, and want to be part of a dynamic and collaborative team, apply now to join Synopsys.</li>\n<li>We can&#39;t wait to hear from you!</li>\n</ul>\n<p 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We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n</ul>\n<ul>\n<li>Time Away</li>\n</ul>\n<ul>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n</ul>\n<ul>\n<li>Family Support</li>\n</ul>\n<ul>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n</ul>\n<ul>\n<li>ESPP</li>\n</ul>\n<ul>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n</ul>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<ul>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n</ul>\n<ul>\n<li>Compensation</li>\n</ul>\n<ul>\n<li>Competitive salaries.</li>\n</ul>\n<ul>\n<li>Awards</li>\n</ul>\n<ul>\n<li>We&#39;re proud to receive several recognitions.</li>\n</ul>\n<ul>\n<li>Explore the Possibilities with Synopsys</li>\n</ul>\n<ul>\n<li>Search Synopsys Careers</li>\n</ul>\n<ul>\n<li>Join our Talent Community</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2a30b6e4-ca4"},"title":"ASIC Verification, Principal Engineer","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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