{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/rtl-synthesis"},"x-facet":{"type":"skill","slug":"rtl-synthesis","display":"Rtl Synthesis","count":2},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2e9367c2-7d7"},"title":"SerDes IP's Applications Engineering, Sr Staff Engineer","description":"<p>We are seeking a highly motivated and experienced Sr Staff Engineer to join our SerDes IP&#39;s Applications Engineering team. The successful candidate will be responsible for providing technical guidance and hands-on support to customers integrating Synopsys Interface IP into their ASIC SoC/systems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems</li>\n<li>Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s and/or masters with a minimum 10+yrs of Industry experience or equivalent</li>\n<li>At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)</li>\n<li>Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure</li>\n<li>Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2e9367c2-7d7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/herzliya/serdes-ip-s-applications-engineering-sr-staff-engineer/44408/92304383936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP design","ASIC/SoC integration","customer-facing engineering roles","ASIC design flows","simulation/verification","RTL synthesis","floorplanning","physical design","timing closure","High Speed SerDes IPs","PCIe","ETH","USB"],"x-skills-preferred":[],"datePosted":"2026-03-06T07:38:03.021Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Herzliya, Tel Aviv, Israel"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP design, ASIC/SoC integration, customer-facing engineering roles, ASIC design flows, simulation/verification, RTL synthesis, floorplanning, physical design, timing closure, High Speed SerDes IPs, PCIe, ETH, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cb550b3a-5d9"},"title":"Technical Support Engineer","description":"<p>We Are:</p>\n<p>You are a passionate technologist with a strong drive to solve complex challenges and deliver exceptional customer experiences. You thrive in fast-paced, collaborative environments and possess a deep understanding of semiconductor design flows, EDA tools, and system integration.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Provides technical support to company customers and field engineers who encounter problems.</p>\n<p>Support process includes diagnosing, troubleshooting, providing workarounds for product bugs, and providing solutions for a wide range of complex issues covering usage, methodology, product defects, interoperability, licensing, and installation.</p>\n<p><strong>What you need</strong></p>\n<p>Need 13+ year working experience on HW development area or verification domain prototyping/emulation methodologies and technologies, who have demonstrated experience in the complete design validation cycle, driven to help customers achieve their SW validation goals.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cb550b3a-5d9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/seongnam-si/applications-engineering-director/44408/87851314464","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["EDA verification flow","Simulation","RTL synthesis","FPGA implementation","HW bring-up","scripting language","Unix/Linux development environment"],"x-skills-preferred":["communication skills","problem-solving skills"],"datePosted":"2025-12-22T11:58:33.559Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brackley"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"EDA verification flow, Simulation, RTL synthesis, FPGA implementation, HW bring-up, scripting language, Unix/Linux development environment, communication skills, problem-solving skills"}]}