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Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.</p>\n<p>What You’ll Be Doing:</p>\n<p>Defining and developing ASIC RTL design and verification at both chip and block levels.\nCreating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols.\nCollaborating with cross-functional teams to ensure seamless integration and functionality of designs.\nUtilizing advanced design and verification methodologies and tools to achieve high-quality results.\nMentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.\nCommunicating with internal and external stakeholders to align on project goals and deliverables.</p>\n<p>The Impact You Will Have:</p>\n<p>Enhancing the reliability and performance of Synopsys’ digital design processes.\nDriving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.\nImproving time-to-market for high-performance silicon chips through efficient methodologies.\nBuilding and nurturing a highly skilled development team, elevating overall project quality.\nInfluencing strategic decisions that shape the future of Synopsys’ capabilities.\nEnsuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</p>\n<p>What You’ll Need:</p>\n<p>Extensive experience in ASIC RTL design.\nIn-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.\nProficiency in advanced digital design tools and methodologies.\nStrong problem-solving skills and the ability to work independently.\nExcellent communication skills for effective collaboration with diverse teams.</p>\n<p>Who You Are:</p>\n<p>A visionary leader with a strategic mindset.\nA mentor who fosters talent and encourages innovation.\nA proactive problem solver who thrives in complex environments.\nAn effective communicator with the ability to convey technical concepts to a broad audience.\nA team player who values collaboration and diversity.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. 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Our team collaborates closely with various departments, including analog design, physical design, and applications engineering, to ensure the seamless integration of all design components. We are committed to continuous learning and improvement, fostering a culture of innovation and excellence.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.</p>\n<p>With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.</p>\n<p>Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.</p>\n<p>You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.</li>\n</ul>\n<ul>\n<li>Define synthesis constraints and resolve STA and gate-level simulation issues.</li>\n</ul>\n<ul>\n<li>Collaborate with verification, controller, and lab teams for design and debugging.</li>\n</ul>\n<ul>\n<li>Support RTL to GDS flow during logic implementation.</li>\n</ul>\n<ul>\n<li>Lead projects and train junior engineers.</li>\n</ul>\n<ul>\n<li>Work with customers to resolve technical RTL issues.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver robust RTL designs for advanced silicon solutions.</li>\n</ul>\n<ul>\n<li>Drive successful project completion and tape-outs.</li>\n</ul>\n<ul>\n<li>Enhance design quality and verification efficiency.</li>\n</ul>\n<ul>\n<li>Support customer success and strengthen Synopsys’ reputation.</li>\n</ul>\n<ul>\n<li>Mentor and grow engineering talent within the team.</li>\n</ul>\n<ul>\n<li>Contribute to digital flow improvements and innovation.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering or Telecommunications.</li>\n</ul>\n<ul>\n<li>5+ years of RTL design experience for ASIC or PHY IP.</li>\n</ul>\n<ul>\n<li>Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, 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domain crossing, APB, JTAG protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_05702639-4e7"},"title":"ASIC Digital IP Design/Verification, Architect","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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Enable strategic customers to meet critical industry requirements such as design security, automotive safety, and verification signoff.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e4bdd5cd-618","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/senior-manager-formal-verification-applications-engineering/44408/93365523248","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","Verification methodologies","Assertion-based verification","Unix/Linux automation shell scripting","Programming languages such as Tcl, Perl, and Python","Formal property verification testbench development","Floating point arithmetic operations","C/C++","IEEE math libraries","Security architecture","Automotive safety (FuSa)","Verification signoff with formal"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:43.796Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verification methodologies, Assertion-based verification, Unix/Linux automation shell scripting, Programming languages such as Tcl, Perl, and Python, Formal property verification testbench development, Floating point arithmetic operations, C/C++, IEEE math libraries, Security architecture, Automotive safety (FuSa), Verification signoff with formal"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6d8de738-1a7"},"title":"Staff Hardware Engineer","description":"<p>We are seeking a skilled Staff Hardware Engineer to join our team in Cairo. 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You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.</p>\n<p>Requirements include:</p>\n<ul>\n<li>BS/MS in Computer Science, Electrical Engineering, or a related field.</li>\n<li>5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.</li>\n<li>Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.</li>\n<li>Expertise in using industry-standard EDA tools and methodologies for design and verification.</li>\n<li>Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.</li>\n<li>Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.</li>\n<li>Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).</li>\n<li>Strong logical thinking and problem-solving abilities, with a keen attention to detail.</li>\n</ul>\n<p>Benefits include:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6d8de738-1a7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/cairo/staff-hardware-engineer/44408/93286401152","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","Xilinx UltraScale, UltraScale+, and Versal FPGAs","Hardware Description Languages (VERILOG, VHDL, SystemVerilog)","Industry-standard EDA tools and methodologies","FPGA flows and tools (Vivado)","Unix/Linux environments","Scripting languages (Shell, Perl, Python, TCL)","HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:26.758Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Cairo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, Xilinx UltraScale, UltraScale+, and Versal FPGAs, Hardware Description Languages (VERILOG, VHDL, SystemVerilog), Industry-standard EDA tools and methodologies, FPGA flows and tools (Vivado), Unix/Linux environments, Scripting languages (Shell, Perl, Python, TCL), HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_02d8b8e9-445"},"title":"IP Design Technical Lead/ Staff ASIC RTL Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.</p>\n<p><strong>Responsibilities</strong></p>\n<p>Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</p>\n<p>Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.</p>\n<p>Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.</p>\n<p>Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.</p>\n<p>Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&amp;R-aware synthesis using tools such as Fusion Compiler.</p>\n<p>Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.</p>\n<p>Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.</p>\n<p>4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.</p>\n<p>Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.</p>\n<p>Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.</p>\n<p>Familiarity with high-speed design (&gt;600MHz), P&amp;R-aware synthesis, and EDA tools such as Fusion Compiler.</p>\n<p>Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.</p>\n<p>Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).</p>\n<p>Exposure to quality processes in IP design and verification is an advantage.</p>\n<p>Prior experience as a technical lead or mentor is highly desirable.</p>\n<p><strong>Who We Are Looking For</strong></p>\n<p>Innovative thinker with a solutions-oriented mindset and a passion for technology.</p>\n<p>Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.</p>\n<p>Natural leader with mentoring abilities, fostering inclusion and diversity within the team.</p>\n<p>Detail-oriented professional with strong analytical and problem-solving skills.</p>\n<p>Self-motivated, adaptable, and eager to drive technical excellence and process improvements.</p>\n<p>Committed to continuous learning and staying ahead of industry trends.</p>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_02d8b8e9-445","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-asic-rtl-design-engineer/44408/92577687840","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","Verilog/SystemVerilog","Simulation tools","Design flows","Linting","Static timing analysis","Formal checking","P&R-aware synthesis","Fusion Compiler","Version control systems","Scripting languages","Industry protocols","Ethernet","DDR","PCIe","USB","MIPI-UFS/Unipro","SD-MMC","AMBA"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:10:55.005Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, Verilog/SystemVerilog, Simulation tools, Design flows, Linting, Static timing analysis, Formal checking, P&R-aware synthesis, Fusion Compiler, Version control systems, Scripting languages, Industry protocols, Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_40a899dc-af8"},"title":"Senior/Staff ASIC Design Verification Engineer","description":"<p>Our organisation is seeking a skilled Senior/Staff ASIC Design Verification Engineer to join our team in Ho Chi Minh City, Vietnam. As a key member of our engineering team, you will be responsible for designing and developing cutting-edge semiconductor solutions. Your expertise in ASIC RTL design flow, RTL and GLS verification, and high-speed interface protocols will be essential in advancing our technology and enabling innovations in various industries.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.</li>\n<li>Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.</li>\n<li>Define, develop, and execute functional verification plans and test strategies.</li>\n<li>Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.</li>\n<li>Generate VCD files and perform power analysis/reporting using PrimeTime PX.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum of 2 years of experience in ASIC RTL design flow.</li>\n<li>Proficiency in RTL and GLS verification, with strong debugging capabilities.</li>\n<li>Excellent teamwork and communication skills, with professional proficiency in English.</li>\n<li>Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_40a899dc-af8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/senior-staff-asic-design-verification-engineer/44408/92568976592","x-work-arrangement":"onsite","x-experience-level":"senior/staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC RTL design flow","RTL and GLS verification","High-speed interface protocols","UVM-based methodologies","PrimeTime PX"],"x-skills-preferred":["High-speed interface protocols"],"datePosted":"2026-03-10T12:09:27.363Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design flow, RTL and GLS verification, High-speed interface protocols, UVM-based methodologies, PrimeTime PX, High-speed interface protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4b712e08-c1e"},"title":"Staff Engineer (Machine Learning)","description":"<p><strong>Job Description</strong></p>\n<p>At Synopsys, we&#39;re seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design &amp; Verification business. As a key member of this highly innovative team, you&#39;ll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.</li>\n<li>Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.</li>\n<li>Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.</li>\n<li>Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).</li>\n<li>Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.</li>\n<li>Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys&#39; product lines.</li>\n</ul>\n<p><strong>Impact:</strong></p>\n<ul>\n<li>Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.</li>\n<li>Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.</li>\n<li>Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys&#39; tools, driving industry-leading outcomes.</li>\n<li>Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.</li>\n<li>Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.</li>\n<li>Strengthen Synopsys&#39; position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelor&#39;s, Master&#39;s, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.</li>\n<li>5+ years of experience in chip design, EDA, or related fields.</li>\n<li>Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).</li>\n<li>Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.</li>\n<li>Solid understanding of Unix/Linux environments and design flow automation.</li>\n<li>Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.</li>\n<li>Familiarity with low power design techniques, computer architecture, and machine learning principles.</li>\n</ul>\n<p><strong>Who We&#39;re Looking For:</strong></p>\n<ul>\n<li>A creative problem solver who approaches challenges with curiosity and resilience.</li>\n<li>An effective communicator who collaborates well with multidisciplinary teams.</li>\n<li>Detail-oriented with a passion for quality and continuous improvement.</li>\n<li>Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.</li>\n<li>Committed to learning, growth, and sharing knowledge with others.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of:</strong></p>\n<p>You&#39;ll join the Machine Learning Center of Excellence (ML CoE) within Synopsys&#39; Silicon Design &amp; Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you&#39;ll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4b712e08-c1e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/staff-engineer-machine-learning/44408/92577691360","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["machine learning","chip design","EDA","Perl","Python","Tcl","shell scripting","Unix/Linux environments","design flow automation","RTL design","synthesis","place and route","verification","ATPG","custom-circuit design","signoff flows","low power design techniques","computer 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and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.</p>\n<p>As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.</p>\n<p>You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.</p>\n<p>You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.</p>\n<p>You will develop and implement advanced test plans and test environments at both unit and system levels.</p>\n<p>You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.</p>\n<p>You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.</p>\n<p>You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.</p>\n<p>This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.</p>\n<p>You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.</p>\n<p>You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.</p>\n<p>You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.</p>\n<p>You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.</p>\n<p>You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.</p>\n<p>You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.</p>\n<p>You will join the DesignWare IP Verification R&amp;D team, a group of talented and passionate engineers committed to advancing Synopsys&#39; leadership in semiconductor IP.</p>\n<p>The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.</p>\n<p>Collaboration, innovation, and a drive for excellence define our culture.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2a58c59b-da1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-design-verification-sr-staff-engineer-ddr/44408/89681053968","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC verification","System Verilog/UVM","HVL","Serial interface protocols","IP core development","Verification methodologies","Test plans and test environments","Functional coverage and code coverage metrics","Regressions and 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at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/09/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.</p>\n<p>You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>\n<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>\n<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>\n</ul>\n<ul>\n<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>\n</ul>\n<ul>\n<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>\n</ul>\n<ul>\n<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>\n</ul>\n<ul>\n<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>\n</ul>\n<ul>\n<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>\n</ul>\n<ul>\n<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>\n</ul>\n<ul>\n<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>\n</ul>\n<ul>\n<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>\n</ul>\n<ul>\n<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>\n</ul>\n<ul>\n<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>\n</ul>\n<ul>\n<li>Past experience of leading IP deign projects, team.</li>\n</ul>\n<ul>\n<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>\n</ul>\n<ul>\n<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>\n</ul>\n<ul>\n<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>\n</ul>\n<ul>\n<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>\n</ul>\n<ul>\n<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>\n<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>\n<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.</p>\n<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>\n<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b5f1283c-76e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","System architecture","ASIC solutions","High-performance protocols","DDR PHY","PCIe","USB","HBM","Verilog","SystemVerilog","Simulation tools","Design flows","Lint","CDC","Synthesis","Static timing analysis","Formal verification","Control path-oriented designs","Asynchronous FIFOs","DMA","SPRAM/DPRAM interfaces","Scripting languages","Perl","Shell"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:04:48.404Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, System architecture, ASIC solutions, High-performance protocols, DDR PHY, PCIe, USB, HBM, Verilog, SystemVerilog, Simulation tools, Design flows, Lint, CDC, Synthesis, Static timing analysis, Formal verification, Control path-oriented designs, Asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces, Scripting languages, Perl, Shell"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3a6efc4b-131"},"title":"ASIC Security Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>We are seeking a highly skilled ASIC Security Staff Engineer to join our team at Synopsys. As a key member of our Security IP team, you will be responsible for designing and implementing secure ASIC solutions for various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Designing and implementing RTL in Verilog and/or System Verilog for Security Applications.</li>\n<li>Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM.</li>\n<li>Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification.</li>\n<li>Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions.</li>\n<li>Working within an international team setup, contributing to global projects.</li>\n<li>Ensuring adherence to high-quality standards and best practices in digital design and verification processes.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhancing the performance and security of our IP cores and subsystems.</li>\n<li>Contributing to the rapid integration of advanced capabilities into SoCs, meeting unique performance, power, and size requirements.</li>\n<li>Reducing time-to-market for differentiated products with minimized risk.</li>\n<li>Driving innovation in the fields of CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive.</li>\n<li>Collaborating with a diverse team to deliver leading-edge solutions that shape the future of technology.</li>\n<li>Playing a key role in maintaining Synopsys&#39; position as a leader in chip design and software security.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>3+ years Experience in RTL design of hardware IP components.</li>\n<li>Proficiency in ASIC verification using System Verilog, UVM, and or Verilog</li>\n<li>Ability to create detailed specifications for test environments.</li>\n<li>MSc or PhD in Electrical Engineering or Computer Science.</li>\n<li>Strong understanding of IC Design flows and exceptional problem-solving and debugging skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A strong communicator with excellent written and verbal skills.</li>\n<li>A team player who thrives in a collaborative international environment.</li>\n<li>An innovative thinker who is passionate about technology and continuous improvement.</li>\n<li>Detail-oriented and committed to delivering high-quality work.</li>\n<li>Adaptable and able to manage multiple tasks effectively.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be joining the Security IP team in Eindhoven at the High Tech Campus, a dynamic and innovative group dedicated to extending the Security IP business in markets such as CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive. Our team is composed of experts in hardware and software security, working together to develop state-of-the-art IP cores and subsystems. We value collaboration, creativity, and a commitment to excellence.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3a6efc4b-131","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/eindhoven/asic-security-staff-engineer/44408/91940192192","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","Verilog","System Verilog","UVM","Formal verification","IC Design flows","Problem-solving and debugging skills"],"x-skills-preferred":["ASIC verification","Digital hardware Security IP cores and subsystems","Embedded hardware/software IP solutions"],"datePosted":"2026-03-09T11:09:25.644Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eindhoven"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog, System Verilog, UVM, Formal verification, IC Design flows, Problem-solving and debugging skills, ASIC verification, Digital hardware Security IP cores and subsystems, Embedded hardware/software IP solutions"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e4d64b54-9d8"},"title":"Senior Staff R&D Engineer (SoC)","description":"<p><strong>Overview</strong></p>\n<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15159</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/04/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an enthusiastic and detail-oriented SoC RTL Performance Verification Engineer with a passion for developing and deploying verification solutions for System on Chip (SoC) designs. With a strong background in RTL hardware design and verification, you excel in using industry-standard languages like Verilog and SystemVerilog. Your expertise in developing ZeBu emulation-based verification IP (transactor) and solutions makes you a valuable asset to any team. You thrive in dynamic environments, tackling complex problems creatively while adhering to company policies and procedures. Your communication skills are exemplary, allowing you to work effectively with both internal teams and external clients. With a deep understanding of protocols like AMBA AXI/CHI and proficiency in UNIX and scripting, you bring a comprehensive skill set to the table, ready to make an impact in the rapidly evolving field of SoC performance verification.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Developing SoC Performance Validation (PV) flow and components (transactor model and CI/CD automation) on ZeBu emulator.</li>\n</ul>\n<ul>\n<li>Creating emulation-based transactor and solutions using SystemVerilog and C++.</li>\n</ul>\n<ul>\n<li>Providing technical support and guidance to customers during the deployment of the ZeBu emulator.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Ensuring the reliability and performance of customer SoC designs through rigorous validation processes.</li>\n</ul>\n<ul>\n<li>Enhancing the capabilities of the ZeBu emulator transactor to meet evolving industry standards and customer needs.</li>\n</ul>\n<ul>\n<li>Contributing to the development of innovative SoC PV solutions that set Synopsys apart from competitors.</li>\n</ul>\n<ul>\n<li>Supporting customers in achieving their design and performance goals, thereby strengthening Synopsys&#39; market position.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in SoC PV methodologies, leading to more efficient and effective processes.</li>\n</ul>\n<ul>\n<li>Fostering collaboration and knowledge sharing within the team, enhancing overall performance and innovation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or a related field (RTL design/verification) with a minimum of 12+ years of experience.</li>\n</ul>\n<ul>\n<li>A solid understanding of the SoC architecture among HW IPs, AMBA system buses, and LPDDR memory controllers in a mobile AP.</li>\n</ul>\n<ul>\n<li>Proficiency in developing emulation-based transactor models and solutions using SystemVerilog and C++.</li>\n</ul>\n<ul>\n<li>Proficiency with UNIX and scripting.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be part of a dynamic and innovative team focused on developing and deploying cutting-edge verification solutions for SoC designs. The team values collaboration, continuous learning, and a commitment to excellence, working together to drive technological advancements and deliver exceptional results for our customers.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e4d64b54-9d8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/seongnam-si/senior-staff-r-and-d-engineer-soc/44408/91427515184","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design/verification","Verilog","SystemVerilog","ZeBu emulator","UNIX","scripting"],"x-skills-preferred":["AMBA AXI/CHI","LPDDR memory controllers"],"datePosted":"2026-03-09T11:07:14.173Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Seongnam-si"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design/verification, Verilog, SystemVerilog, ZeBu emulator, UNIX, scripting, AMBA AXI/CHI, LPDDR memory controllers"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_48da4c00-386"},"title":"Design Architect (PCIe/CXL Expert)","description":"<p>You are a visionary and highly experienced logic design expert with a passion for building next-generation hardware solutions. With a strong foundation in PCI Express (PCIe) and/or Compute Express Link (CXL) protocols, you thrive in challenging technical environments, pushing the boundaries of what’s possible in high-speed, complex SoC-class platforms. Your background combines deep hands-on expertise in FPGA architecture, RTL design, and hardware validation, making you a go-to leader for mission-critical projects. You excel at architecting robust, production-quality subsystems and are adept at navigating the intricacies of hardware/software co-design and debugging.</p>\n<p>You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.</li>\n<li>Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.</li>\n<li>Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.</li>\n<li>Collaborating with R&amp;D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.</li>\n<li>Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.</li>\n<li>Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.</li>\n<li>Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.</li>\n<li>Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.</li>\n<li>Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.</li>\n<li>Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.</li>\n<li>12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.</li>\n<li>Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.</li>\n<li>7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.</li>\n<li>Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).</li>\n<li>Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.</li>\n<li>Experience in Unix/Linux development environments.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative team player with excellent communication skills and a global mindset.</li>\n<li>Proactive problem solver who thrives in dynamic, fast-paced environments.</li>\n<li>Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.</li>\n<li>Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.</li>\n<li>Adaptable and eager to stay updated with the latest industry trends and technologies.</li>\n<li>Customer-focused, with a dedication to supporting and enabling client success.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&amp;D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_48da4c00-386","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/design-architect-pcie-cxl-expert/44408/92113189568","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["PCIe","CXL","FPGA","RTL design","hardware validation","Unix/Linux development environments","Xilinx FPGA experience","transceiver/SERDES integration","FPGA prototyping flows","SystemVerilog/Verilog","hardware development cycle","simulation","synthesis","timing analysis"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:02:24.768Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"PCIe, CXL, FPGA, RTL design, hardware validation, Unix/Linux development environments, Xilinx FPGA experience, transceiver/SERDES integration, FPGA prototyping flows, SystemVerilog/Verilog, hardware development cycle, simulation, synthesis, timing analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_517e3008-238"},"title":"Physical Design Engineer","description":"<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$266K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.</p>\n<p>You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Develop, build and own tools, flows and methodologies for physical implementation</li>\n<li>Own physical implementation of floorplan blocks from floorplanning to final signoff</li>\n<li>Collaborate with RTL designers to drive optimal block implementation solutions</li>\n<li>Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners</li>\n</ul>\n<p><strong>Qualifications:</strong></p>\n<ul>\n<li>BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development</li>\n<li>Demonstrated success in taping out complex silicon designs</li>\n<li>Hands-on experience with block physical implementation and PPA convergence</li>\n<li>Strong coding experience with python, bazel, TCL</li>\n<li>Strong experience building physical design tools, flows and methodologies</li>\n<li>Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.</li>\n<li>Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation</li>\n</ul>\n<p><strong>Bonus:</strong></p>\n<ul>\n<li>Experience with AI or HPC-focused chips</li>\n<li>Experience with optimizing PPA for high performance compute cores</li>\n<li>Hands-on experience with top-level design methodologies</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_517e3008-238","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/5a265d2b-683f-4cea-9b69-8e137e704ab3","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$266K – $445K","x-skills-required":["physical design","methodology development","python","bazel","TCL","EDA vendors","ASIC partners","microarchitecture","RTL design","physical design","circuit design","physical verification","timing closure"],"x-skills-preferred":["AI or HPC-focused chips","optimizing PPA for high performance compute cores","top-level design methodologies"],"datePosted":"2026-03-06T18:41:49.725Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, methodology development, python, bazel, TCL, EDA vendors, ASIC partners, microarchitecture, RTL design, physical design, circuit design, physical verification, timing closure, AI or HPC-focused chips, optimizing PPA for high performance compute cores, top-level design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":266000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e8eef588-4b1"},"title":"Technical Deployment Lead, Semiconductors","description":"<p><strong>Technical Deployment Lead, Semiconductors</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Location Type</strong></p>\n<p>Hybrid</p>\n<p><strong>Department</strong></p>\n<p>Model Deployment for Business</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$198K – $335K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p><strong>About the team</strong></p>\n<p>OpenAI’s Forward Deployed Engineering (FDE) team turns research breakthroughs into production-grade systems. We embed deeply with customers to solve high-leverage problems and act as the delivery engine for our most complex large-scale engagements. We move quickly from prototype to production and surface reusable patterns that shape our platform. We operate at the intersection of deployment and development – working closely with OpenAI Research, Product and Partnerships.</p>\n<p><strong>About the Role</strong></p>\n<p>As a Technical Deployment Lead (TDL), you will define how OpenAI delivers complex systems to Semiconductor customers. You will own how solutions are scoped, built, shipped, and adopted across high-value engineering workflows such as RTL design, verification, and physical implementation. You’ll translate business outcomes into a technical plan, run day-to-day execution across FDEs, Researchers, and Customer Engineers, and partner with customer teams to ensure delivery supports their goals.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li><strong>Own the technical delivery plan</strong> for multiple interdependent work streams, translating customer objectives into a roadmap with milestones, dependencies, and acceptance criteria.</li>\n</ul>\n<ul>\n<li><strong>Run day-to-day engineering execution by</strong> tracking and driving delivery across OpenAI FDE and customer teams. Keep progress unblocked and sequenced. Make real-time trade-offs on scope and priority to protect the critical path.</li>\n</ul>\n<ul>\n<li><strong>Embed with Semiconductor customer teams to land production deployments and drive adoption.</strong> Map workflows, shape tools/integrations, and translate requirements into a delivery plan.</li>\n</ul>\n<ul>\n<li><strong>Shape production deployments</strong> that integrate with customer infrastructure, data systems, and engineering toolchains, including export-controlled environments.</li>\n</ul>\n<ul>\n<li><strong>Partner with Product and Research</strong> so platform components and research work streams land in time to support deployment goals.</li>\n</ul>\n<ul>\n<li><strong>Codify solution patterns and evals.</strong> Extract reusable patterns and package field signals to improve product and models.</li>\n</ul>\n<ul>\n<li><strong>Own value cases and ROI.</strong> Set impact hypotheses, baselines, and KPIs; run pre-/post-deployment measurement and report to exec sponsors.</li>\n</ul>\n<ul>\n<li>**Help define how OpenAI engages Semiconductor customers</li>\n</ul>\n<p><strong>You’ll thrive in this role if you:</strong></p>\n<ul>\n<li>Bring 7+ years of customer‑facing technical delivery leadership.</li>\n</ul>\n<ul>\n<li>Have deep expertise in Semiconductor workflows, including RTL design, verification, EDA tooling, and physical implementation</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e8eef588-4b1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/ec9950cb-ccb5-4d2b-b49d-0f6a80b03460","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$198K – $335K","x-skills-required":["Technical delivery leadership","Semiconductor workflows","RTL design","Verification","EDA tooling","Physical implementation","Customer-facing technical delivery"],"x-skills-preferred":[],"datePosted":"2026-03-06T18:35:39.407Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Technical delivery leadership, Semiconductor workflows, RTL design, Verification, EDA tooling, Physical implementation, Customer-facing technical delivery","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":198000,"maxValue":335000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c47b3425-297"},"title":"Reliability/DFX Engineer","description":"<p><strong>Reliability/DFX Engineer</strong></p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled cross-stack engineer with deep expertise in making ML systems reliable at scale. This hands-on individual contributor will sit within our hardware team and work closely with chip design, platform design, hardware health, and the broader industry ecosystem to architect, implement, and deploy reliable next-generation AI accelerator systems.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Oversee DFX architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to enhance reliability and fault tolerance. DFX includes design for testability, reliability, availability, and serviceability of high-performance AI hardware.</li>\n</ul>\n<ul>\n<li>Build system-level reliability models grounded in empirical data to guide organization-wide DFX and reliability strategy. This requires a detailed understanding of chip and system architecture, design, implementation, and component-level reliability.</li>\n</ul>\n<ul>\n<li>Collaborate with chip and platform architecture/design teams to explore and implement DFX features, including the specification and implementation of digital/mixed-signal IP, firmware/system software, and DFX methodology (in partnership with engineering teams).</li>\n</ul>\n<ul>\n<li>Partner with hardware health and platform design teams to continuously improve reliability and fault tolerance in NPI and HVM. This includes optimizing operating conditions, designing experiments, and performing data analysis to drive continuous, data-driven improvements across the stack.</li>\n</ul>\n<ul>\n<li>Serve as the DFX/reliability champion and evangelist to align the broader industry ecosystem with OpenAI’s requirements and roadmap.</li>\n</ul>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>BS with 15+ years, MS with 10+ years, or PhD with 3+ years of relevant industry experience focused on reliability across the chip/platform stack.</li>\n</ul>\n<ul>\n<li>Hands-on experience with RTL design and DFT is required; physical implementation and/or silicon ATE experience is preferred.</li>\n</ul>\n<ul>\n<li>Detailed understanding of ML chip and platform architecture and ML workload characteristics is required.</li>\n</ul>\n<ul>\n<li>Strong fundamentals in reliability modeling, with hands-on skills in empirical data analysis.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. 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As a key member of our team, you will be responsible for architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</li>\n<li>Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.</li>\n<li>Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.</li>\n<li>Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.</li>\n<li>4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.</li>\n<li>Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.</li>\n<li>Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9b235f6e-c09","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/ip-design-technical-lead-staff-asic-rtl-design-engineer/44408/90581151808","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","Verilog/SystemVerilog","simulation tools","design flows"],"x-skills-preferred":["data path and control path design","Reed Solomon FEC","BCH codes","CRC architectures","MAC SEC engines"],"datePosted":"2026-03-06T07:24:37.286Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog/SystemVerilog, simulation tools, design flows, data path and control path design, Reed Solomon FEC, BCH codes, CRC architectures, MAC SEC engines"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c160f208-ea8"},"title":"Principal Engineer, ASIC Digital Design","description":"<p>We are seeking a Principal Engineer, ASIC Digital Design to join our team in Munich, Germany. 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