{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/rtl-design-and-verification"},"x-facet":{"type":"skill","slug":"rtl-design-and-verification","display":"Rtl Design And Verification","count":7},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_66c5c8aa-9e8"},"title":"Solutions Engineering, Sr Staff Engineer (DFT ,Verification, product Engineer)","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li><p>Working closely with a world-class R&amp;D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.</p>\n</li>\n<li><p>Working closely with customers, you will bring detailed requirements into the factory to enable R&amp;D for strong, robust, and successful product development.</p>\n</li>\n<li><p>Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.</p>\n</li>\n<li><p>Driving the deployment and smooth execution of SLM solutions into customers’ projects.</p>\n</li>\n<li><p>Enabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.</p>\n</li>\n</ul>\n<p>The impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_66c5c8aa-9e8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/solutions-engineering-sr-staff-engineer-dft-verification-product-engineer/44408/92871142528","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design and verification","D2D and PHY protocols","UCIe and HBM","JTAG IEEE 1149.1","IEEE 1687/1500","BIST/DFT mechanisms","3D-IC/2.5D-IC solutions","IEEE 1838 and UCIe standards","PCIe & USB protocol knowledge","Debugging abilities","Flow automation","Synthesis","Lint, CDC, RDC"],"x-skills-preferred":["GenAI and Agentic AI workflows","Architecture/micro-architecture experience","Understanding of GenAI and Agentic AI workflows"],"datePosted":"2026-04-05T13:21:31.895Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, D2D and PHY protocols, UCIe and HBM, JTAG IEEE 1149.1, IEEE 1687/1500, BIST/DFT mechanisms, 3D-IC/2.5D-IC solutions, IEEE 1838 and UCIe standards, PCIe & USB protocol knowledge, Debugging abilities, Flow automation, Synthesis, Lint, CDC, RDC, GenAI and Agentic AI workflows, Architecture/micro-architecture experience, Understanding of GenAI and Agentic AI workflows"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8409e0bb-24a"},"title":"RTL Design & Verification Staff Engineer","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>We are looking for a passionate, detail-oriented engineer with an insatiable curiosity for technology and its impact on the world. You will thrive in collaborative environments, bringing together diverse perspectives to solve complex challenges. With a strong foundation in RTL design and verification, you will approach every project with a sense of ownership and a commitment to excellence.</p>\n<p>As an effective communicator, you will clearly articulate technical concepts to both internal teams and external customers, fostering strong partnerships and driving innovation. You will be adaptable, self-motivated, and resilient in the face of challenges, always seeking opportunities to learn and grow.</p>\n<p>Your responsibilities will include designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance. You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.</p>\n<p>You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies. You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.</p>\n<p>You will participate in code reviews and technical discussions to drive innovation and continuous improvement.</p>\n<p>The impact you will have includes accelerating the development of industry-leading SLM IPs that power the world&#39;s top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions. You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy.</p>\n<p>You will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will have 5+ years of hands-on experience in RTL design and verification. You will be proficient in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.</p>\n<p>You will be an analytical and critical thinker with a detail-oriented approach. You will be an effective communicator, comfortable collaborating across teams and with customers. You will be self-motivated and proactive in seeking solutions and driving projects forward.</p>\n<p>You will join a talented and diverse engineering team focused on developing and verifying cutting-edge Silicon Lifecycle Management IPs for next-generation chip solutions.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8409e0bb-24a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/rtl-design-and-verification-staff-engineer/44408/93169652816","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","EDA tools","Verilog","System Verilog","TCL scripting","Formal Verification methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:54.841Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, EDA tools, Verilog, System Verilog, TCL scripting, Formal Verification methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e40da191-421"},"title":"Staff ASIC Digital Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff ASIC Digital Design Engineer, you will be part of our R&amp;D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.</p>\n<p>Key responsibilities include:</p>\n<p>Creating and debugging test benches and test cases\nRunning RTL and gate-level simulations\nSupporting application engineers and customers on HBM/DDR PHY topics\nContributing to technical documentation\nDriving product improvements based on customer feedback</p>\n<p>The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:</p>\n<p>ASIC RTL design and verification experience\nVerilog, PERL, TCL, Python skills\nStatic timing analysis and synthesis knowledge\nSimulation and debugging abilities\nHBM/DDR protocol experience is an asset</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e40da191-421","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/kanata/staff-asic-digital-design-engineer-15996/44408/93015824864","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC RTL design and verification experience","Verilog, PERL, TCL, Python skills","Static timing analysis and synthesis knowledge","Simulation and debugging abilities","HBM/DDR protocol experience"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:45.947Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Kanata"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design and verification experience, Verilog, PERL, TCL, Python skills, Static timing analysis and synthesis knowledge, Simulation and debugging abilities, HBM/DDR protocol experience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_05702639-4e7"},"title":"ASIC Digital IP Design/Verification, Architect","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Verification Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of HBM or PCIe/CXL and its applications. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Defining and developing ASIC RTL design and verification at both chip and block levels.</li>\n<li>Creating and executing verification plans for complex digital designs, particularly focusing on HBM or PCIe/CXL.</li>\n<li>Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.</li>\n<li>Utilizing advanced verification methodologies and tools to achieve high-quality verification results.</li>\n<li>Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.</li>\n<li>Communicating with internal and external stakeholders to align on project goals and deliverables.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enhancing the reliability and performance of Synopsys&#39; digital verification processes.</li>\n<li>Driving innovations in HBM or PCIe/CXL technology, contributing to the development of cutting-edge semiconductor solutions.</li>\n<li>Improving time-to-market for high-performance silicon chips through efficient verification methodologies.</li>\n<li>Building and nurturing a highly skilled verification team, elevating overall project quality.</li>\n<li>Influencing strategic decisions that shape the future of Synopsys&#39; verification capabilities.</li>\n<li>Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC RTL design and verification.</li>\n<li>In-depth knowledge of HBM or PCIe protocols and their applications.</li>\n<li>Proficiency in advanced verification tools and methodologies.</li>\n<li>Strong problem-solving skills and the ability to work independently.</li>\n<li>Excellent communication skills for effective collaboration with diverse teams.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>A team member who encourages innovation.</li>\n<li>A proactive problem solver who thrives in complex environments.</li>\n<li>An effective communicator with the ability to convey technical concepts to a broad audience.</li>\n<li>A team player who values collaboration and diversity.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; verification technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Health &amp; Wellness: Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>Time Away: In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Retirement Plans: Save for your future with our retirement plans that vary by region and country.</li>\n<li>Compensation: Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_05702639-4e7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/reading/asic-digital-ip-design-verification-architect/44408/91458064928","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design and verification","HBM or PCIe protocols and their applications","Advanced verification tools and methodologies","Strong problem-solving skills","Excellent communication skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:07.811Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Reading"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design and verification, HBM or PCIe protocols and their applications, Advanced verification tools and methodologies, Strong problem-solving skills, Excellent communication skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6d8de738-1a7"},"title":"Staff Hardware Engineer","description":"<p>We are seeking a skilled Staff Hardware Engineer to join our team in Cairo. As a Staff Hardware Engineer, you will be responsible for defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development. You will develop and optimize RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability. You will also drive the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.</li>\n<li>Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</li>\n<li>Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.</li>\n<li>Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.</li>\n</ul>\n<p>As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.</p>\n<p>Requirements include:</p>\n<ul>\n<li>BS/MS in Computer Science, Electrical Engineering, or a related field.</li>\n<li>5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.</li>\n<li>Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.</li>\n<li>Expertise in using industry-standard EDA tools and methodologies for design and verification.</li>\n<li>Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.</li>\n<li>Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.</li>\n<li>Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).</li>\n<li>Strong logical thinking and problem-solving abilities, with a keen attention to detail.</li>\n</ul>\n<p>Benefits include:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6d8de738-1a7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/cairo/staff-hardware-engineer/44408/93286401152","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","Xilinx UltraScale, UltraScale+, and Versal FPGAs","Hardware Description Languages (VERILOG, VHDL, SystemVerilog)","Industry-standard EDA tools and methodologies","FPGA flows and tools (Vivado)","Unix/Linux environments","Scripting languages (Shell, Perl, Python, TCL)","HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:26.758Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Cairo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, Xilinx UltraScale, UltraScale+, and Versal FPGAs, Hardware Description Languages (VERILOG, VHDL, SystemVerilog), Industry-standard EDA tools and methodologies, FPGA flows and tools (Vivado), Unix/Linux environments, Scripting languages (Shell, Perl, Python, TCL), HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_07d0d6b0-9ac"},"title":"RTL Design & Verification Engineer (R&D Engineering, Sr Engineer)","description":"<p>We are seeking a passionate, detail-oriented engineer with an insatiable curiosity for technology and its impact on the world. You will be responsible for designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.</li>\n<li>Developing comprehensive test cases to ensure robust product functionality and performance.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>BS/MS in Computer Science, Electrical Engineering, or related field.</li>\n<li>5 years of hands-on experience in RTL design and verification.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_07d0d6b0-9ac","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/rtl-design-and-verification-engineer-r-and-d-engineering-sr-engineer/44408/90568184224","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design and verification","EDA tools","Verilog","System Verilog","TCL scripting","Formal Verification methodologies"],"x-skills-preferred":["digital","analog","mixed-signal IP/circuit design","3D-IC standards","semiconductor verification best practices"],"datePosted":"2026-03-06T07:32:08.111Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, EDA tools, Verilog, System Verilog, TCL scripting, Formal Verification methodologies, digital, analog, mixed-signal IP/circuit design, 3D-IC standards, semiconductor verification best practices"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1e32ec8b-15e"},"title":"R&D Engineering, Sr Staff Engineer (RTL Design & Verification)","description":"<p>Opening. This role exists to drive the development of industry-leading Silicon Lifecycle Management IPs that power the world&#39;s top technology companies.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.</p>\n<ul>\n<li>Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.</li>\n<li>Developing comprehensive test cases to ensure robust product functionality and performance.</li>\n<li>Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.</li>\n<li>Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.</li>\n<li>Contributing to the improvement of verification methodologies and automation flows.</li>\n<li>Documenting design specifications, verification plans, and results to ensure transparency and repeatability.</li>\n<li>Participating in code reviews and technical discussions to drive innovation and continuous improvement.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>BS/MS in Computer Science, Electrical Engineering, or related field.</li>\n<li>8+ years of hands-on experience in RTL design and verification.</li>\n<li>Proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.</li>\n<li>Experience working in Unix/Linux environments.</li>\n<li>Strong debugging and problem-solving skills, especially in complex chip design environments.</li>\n<li>Excellent written and verbal communication skills in English.</li>\n<li>Knowledge of digital, analog, and mixed-signal IP/circuit design (a plus).</li>\n<li>Familiarity with 3D-IC standards and semiconductor verification best practices (desirable).</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1e32ec8b-15e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-sr-staff-engineer-rtl-design-and-verification/44408/91089467920","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","EDA tools","Verilog","System Verilog","TCL scripting","Formal Verification methodologies"],"x-skills-preferred":["Unix/Linux environments","Digital, analog, and mixed-signal IP/circuit design","3D-IC standards and semiconductor verification best practices"],"datePosted":"2026-01-28T15:04:51.990Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, EDA tools, Verilog, System Verilog, TCL scripting, Formal Verification methodologies, Unix/Linux environments, Digital, analog, and mixed-signal IP/circuit design, 3D-IC standards and semiconductor verification best practices"}]}