We are seeking an expert analog design engineer with a passion for high-speed integrated circuits and a drive to push the boundaries of SERDES technology. As a Sr Staff Engineer, you will lead the design and development of high-performance analog and mixed-signal solutions in advanced process nodes.

Key Responsibilities:

• Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.
• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.
• Collaborating with cross-functional teams, including analog, digital, and layout engineers,to optimize design and verification strategies for superior quality and project efficiency.
• Presenting and critically reviewing simulation data within project teams and at external industry panels or customer meetings.
• Overseeing physical layout to minimize parasitics, device stress, and process variations, ensuring robust manufacturability and reliability.
• Documenting design features, creating comprehensive test plans, and ensuring traceability throughout the development lifecycle.
• Consulting on electrical characterization of SERDES IP, analyzing customer silicon data, and proposing enhancements or post-silicon updates as needed.

Impact:

• Driving the next generation of high-speed data communication through pioneering SERDES architectures.
• Enabling Synopsys customers to achieve industry-leading performance, power efficiency, and reliability in their products.
• Fostering a culture of technical excellence and innovation within a diverse, high-caliber design team.
• Accelerating project timelines by streamlining design and verification methodologies.
• Enhancing the overall quality and competitiveness of Synopsys IP offerings through expert problem-solving and continuous improvement.
• Mentoring and developing junior engineers, strengthening the team's collective expertise and future leadership pipeline.

Requirements:

• Ph.D. with 6+ years, or M.Sc. with 8+ years of practical analog IC design experience, preferably in Electrical Engineering, Computer Engineering, or a related field.
• Deep expertise in transistor-level circuit design and sound CMOS fundamentals.
• Hands-on design experience with one or more SERDES sub-circuits (e.g., receive equalizers, samplers, drivers, serializers/deserializers, voltage-controlled oscillators, PLLs, bandgap references, ADCs, DACs).
• Proficiency with schematic entry, physical layout, and design verification tools; familiarity with SPICE simulators and simulation methodologies.
• Experience with analog/digital co-design for performance optimization, including calibration, adaptation, and timing handoff.
• Knowledge of reliability and layout effects (EM, IR, aging, matching, proximity, ESD, etc.).
• Proficiency in Verilog-A for analog behavioral modeling, and experience with scripting languages such as TCL, Perl, C, Python, or MATLAB.
• Excellent communication, presentation, and documentation skills.

Team:

• You will join a dynamic, growing analog and mixed-signal design team focused on developing cutting-edge Multi-Gbps SERDES IP.
• The team is composed of passionate engineers from diverse backgrounds, collaborating closely with digital designers, layout specialists, and software/CAD experts.
• Our culture emphasizes technical excellence, innovation, and continuous learning.
• With access to best-in-class design tools and in-house support, this team thrives on solving industry-defining challenges and delivering world-class IP to Synopsys' global customers.

Rewards and Benefits:

• We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
• Our total rewards include both monetary and non-monetary offerings.
• Your recruiter will provide more details about the salary range and benefits during the hiring process.

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