As an ASIC Digital Design Engineer, you will be part of a dynamic and diverse engineering team focused on subsystem and SoC-level verification. The team is committed to technical excellence, innovation, and continuous improvement, working collaboratively to deliver industry-leading solutions for Synopsys' global clients.

Responsibilities:

Develop and execute comprehensive verification plans for subsystem features and interfaces. Build, enhance, and maintain UVM-based verification environments for complex RTL designs. Create reusable and scalable testbenches, sequences, checkers, and scoreboards to ensure thorough coverage. Debug simulation failures, analyze waveform-level issues, and drive root-cause analysis to resolution. Collaborate closely with design, architecture, and cross-functional engineering teams to align on specifications and compliance. Define and implement test scenarios, including directed, constrained-random, and corner-case verification. Support regression planning, test execution, and coverage closure activities to ensure quality silicon delivery. Contribute to methodology improvements and best practices in functional verification. Communicate progress, technical findings, and risks effectively with stakeholders and team members.

Impact:

Enhance the robustness and performance of subsystem and SoC-level designs through rigorous verification processes. Drive the delivery of high-quality silicon solutions that power next-generation technologies. Accelerate time-to-market for Synopsys' clients by ensuring reliable and efficient verification workflows. Improve verification methodologies and contribute to best practices that set industry standards. Foster collaboration across design, architecture, and engineering teams to achieve common goals. Identify and resolve technical risks early, ensuring successful project outcomes and client satisfaction.

Requirements:

Bachelor's or Master's degree in electronics, electrical engineering, or a related field. Minimum 3+ years of hands-on verification experience, preferably in subsystem or SoC-level projects. Strong proficiency in protocols such as PCIe, CXL, UCIe, Ethernet, DDR, or USB. Solid experience with SystemVerilog/UVM and assertion-based verification techniques. Expertise in functional coverage, code coverage, and regression management. Strong debugging skills using simulation and waveform analysis tools. Exposure to formal verification techniques and their application in real-world scenarios.

Team:

You'll join a dynamic and diverse engineering team focused on subsystem and SoC-level verification. The team is committed to technical excellence, innovation, and continuous improvement, working collaboratively to deliver industry-leading solutions for Synopsys' global clients.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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As a Staff Engineer in our ASIC Digital Design team, you will be responsible for leading and driving ownership of critical areas of verification alongside a team of talented verification engineers. You will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem.

Your responsibilities will include specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models. You will also code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

In addition, you will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met. You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.

You will work closely with RTL designers and architects to ensure functional correctness and collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.

As a Staff Engineer, you will have the opportunity to make a significant impact on the success of our Subsystem and contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.

You will also enhance Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystem through engineering excellence and innovation, and bolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards.

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Elevating the quality and reliability of Synopsys' industry-leading IP cores through robust verification practices is a key responsibility. You will drive continuous improvement and innovation in verification methodologies and environments. You will ensure successful project execution and timely delivery of high-quality IP verification results. You will empower team members to grow professionally, contributing to a culture of excellence and learning. You will support Synopsys' leadership in chip design and IP integration by maintaining rigorous standards. You will enhance customer satisfaction by delivering verified, high-performance IP solutions.

To be successful in this role, you will need to have a BS/BE in Electrical Engineering with 8+ years of relevant experience or MS with 6+ years in IP core/SOC verification. You will have proven experience managing and leading verification engineering teams; prior leadership/management roles are preferred. You will have expertise in verification methodologies such as UVM/VMM/OVM and HVL coding for verification. You will have advanced hands-on knowledge in test planning, environment development (unit/system level), and debugging. You will have experience with industry standard simulators (e.g., VCS) and relevant debugging tools. You will have strong functional coverage coding, test case creation, analysis, and regression management skills. You will have a clear track record in achieving quality targets on complex IP verification projects. Familiarity with industry standard buses and protocols (USB, PCI Express, Ethernet, AMBA) is a plus.

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You are an accomplished engineer with a passion for digital design and verification, eager to make a lasting impact in advanced semiconductor technology. With over a decade of hands-on experience, you bring technical mastery and strategic vision to every project. You thrive in dynamic environments, seamlessly balancing architectural planning with hands-on execution. Your expertise spans RTL development, mixed-signal IPs, and advanced verification methodologies, making you a go-to authority for complex challenges.

As a Lead RTL Verification Engineer, you will be responsible for architecting and implementing SystemVerilog/UVM-based testbenches and verification flows for mixed signal IPs such as UCIe/DDR/Die-to-Die interfaces. You will develop, execute, and drive closure for comprehensive verification plans and coverage metrics. You will also debug RTL issues, manage regressions, and lead root cause analysis for failures.

Guiding and mentoring junior engineers, establishing verification standards and best practices, collaborating with design, software, and validation teams to ensure seamless project delivery and integration, evaluating and championing new verification tools, automation scripts, and methodologies to drive innovation.

Elevate the quality and reliability of Synopsys' mixed signal IPs, directly impacting the success of global semiconductor partners. Accelerate innovation in chip design and verification, contributing to industry-leading products and solutions. Mentor and empower the next generation of engineers, fostering a culture of excellence and growth. Drive adoption of best-in-class verification standards, enhancing productivity and efficiency across teams. Enable seamless integration of complex IPs by bridging design, software, and validation disciplines. Champion advanced verification technologies, positioning Synopsys as a leader in digital design automation.

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As the initial QA owner, you will design, execute, and report on test cycles for enterprise applications and integrations. You will also define and implement QA operating rhythms and governance, including test plans, entry/exit criteria, defect triage, release readiness, and post-release validation.

Key responsibilities include:

• Building and owning the QA strategy for Enterprise Technology, including standards, test planning, and quality gates across the delivery lifecycle.

• Operating hands-on as the initial QA owner: design, execute, and report on test cycles (functional, integration, regression, and UAT support) for enterprise applications and integrations.

• Defining and implementing QA operating rhythms and governance: test plans, entry/exit criteria, defect triage, release readiness, and post-release validation.

• Partnering with product and delivery teams to translate requirements and user stories into testable acceptance criteria and comprehensive test coverage.

• Establishing and maintaining a QA toolchain (test case management, defect tracking, and reporting) and integrating it with existing delivery tooling where applicable.

• Driving integration and end-to-end testing across enterprise platforms, including but not limited to Salesforce, NetSuite, Workday, MuleSoft/integration layer, MES touchpoints, analytics platforms, Slack/Confluence, DocuSign, and Ashby.

• Designing and maintaining regression testing approaches to minimize production defects as systems scale and change velocity increases.

• Implementing lightweight automation where it adds clear value, prioritizing maintainability and high-impact regression coverage.

• Ensuring documentation, auditability, and traceability from requirements through testing and release, aligned with change management and internal control expectations.

• Tracking and communicating quality metrics (defect trends, test coverage, escape rate, cycle time) to drive continuous improvement.

The ideal candidate will have 7+ years of experience in Quality Assurance, Test Engineering, or QA leadership roles supporting enterprise technology products and integrated systems. They will also have demonstrated experience building or formalizing QA processes and operating models in a growing or scaling organization.

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