{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/redhawk"},"x-facet":{"type":"skill","slug":"redhawk","display":"Redhawk","count":2},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_524edc8e-463"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. 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Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_524edc8e-463","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-staff-engineer-16723/44408/93743819104","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Floor planning","Synthesis","Placement and routing","Timing closure","IP integration","Test chip methodology","Advanced verification flows","CAD tools","Design Compiler","PrimeTime","IC Compiler II/FC","ICV","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:19:07.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Floor planning, Synthesis, Placement and routing, Timing closure, IP integration, Test chip methodology, Advanced verification flows, CAD tools, Design Compiler, PrimeTime, IC Compiler II/FC, ICV, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_642c88a4-a92"},"title":"ASIC Physical Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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