We're looking for an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team.
\nOur high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.
\nResponsibilities:
\nRequirements:
\nPreferred Experience:
\nBenefits:
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\nYou are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.
\nKey responsibilities include:
\nWorking closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.
\nWorking closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
\nWorking closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
\nDriving the deployment and smooth execution of SLM solutions into customers’ projects.
\nEnabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.
\nThe impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.
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\nYou are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\nBSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
\n8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.
\nGood exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.
\nKnowledge on memory defectivities soft errors and reliability.
\nFamiliarity with error correcting codes such as Hamming and Hsiao.
\nHands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.
\nFamiliarity with either Synopsys TestMAX Tool chain or competitive offerings.
\nDebugging abilities to identify and resolve issues in functional verification in UVM environment.
\nHands on experience in flow automation.
\nKnowledge of Synthesis is a must with understanding of timing constraints (SDC).
\nKnowledge of Lint, CDC, RDC is a plus.
\nKnowledge of physical implementation is not a must, but good to have.
\nAbility to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.
\nCustomer facing experience is a plus – educating/guiding customer on technical details of a solution.
\nGood to have:
\nHands-on bring-up and debug experience of silicon is a plus.
\nArchitecture/micro-architecture experience.
\nUnderstanding of GenAI and Agentic AI workflows.
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\nLocation
\nSan Francisco
\nEmployment Type
\nFull time
\nDepartment
\nScaling
\nCompensation
\nThe base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.
\nMore details about our benefits are available to candidates during the hiring process.
\nThis role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.
\nAbout the Team
\nOpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
\nAbout the Role
\nWe’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.
\nThis role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.
\nIn this role you will:
\nYou Might Thrive In This Role If You Have:
\n_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._
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\nRTL & Codesign Engineer
\nLocation
\nSan Francisco
\nEmployment Type
\nFull time
\nDepartment
\nScaling
\nCompensation
\nThe base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.
\nMore details about our benefits are available to candidates during the hiring process.
\nThis role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.
\nAbout the Team
\nOpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
\nAbout the Role
\nWe’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.
\nThis role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.
\nIn this role you will:
\nYou Might Thrive In This Role If You Have:
\n_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._
\nAbout OpenAI
\nOpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
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\nAbout the Team
\nOpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
\nAbout the Role
\nYou will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems.
\nIn this role you will:
\nYou might thrive in this role if:
\nNice to have skills:
\nTo comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
\nAbout OpenAI
\nOpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world.
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\nWhat you'll do
\nWhat you need
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