{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/probes"},"x-facet":{"type":"skill","slug":"probes","display":"Probes","count":5},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d7d4d506-11e"},"title":"Electrical Engineer","description":"<p>Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. The company is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.</p>\n<p>The Air and Ground Deterrence (AGD) Division develops integrated robotic systems designed to provide multi-domain situational awareness and force protection across land, sea, and air. The Sentry Hardware team with AGD serves as the key system integrator of the Anduril Sentry Family of Systems (FoS).</p>\n<p>We are looking for an Electrical Engineer to join our rapidly growing team in Irvine, CA. This role will own rapidly developed, ruggedized electronics design in addition to scaling legacy design concepts to support full-rate production. In this role, you will partner with our Architecture and Product Management team to help drive system requirements prior to owning full PCB and/or electrical system design.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Take ownership as the main point of contact for electrical integration activities.</li>\n<li>Provide hands-on and in-field support of prototype and production-level product.</li>\n<li>Collaborate with mechanical engineers to optimize selection, design, and integration of high-power components, modules, and distribution.</li>\n<li>Trade-off component and module selections against size, weight, power, and EMC requirements.</li>\n<li>Collaborate with design team to achieve reliability goals at a system level in context of concepts of operation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 5 years of professional experience.</li>\n<li>Self-starter with the ability to design digital &amp; analog electronics from concept and functional prototype, to production-ready product.</li>\n<li>Ability to troubleshoot existing hardware to find root cause of issues and implement improvements to improve the design.</li>\n<li>Develop clear documentation to capture design requirements, specifications, test coverage, and test reports.</li>\n<li>Complete full-cycle PCB design including collecting requirements, schematic design, component selection, completion of layout, bring-up, test, debug, validation, characterization, and integration with the system.</li>\n<li>Work closely with other mechanical, software, firmware, and test engineers to deliver fully functional products.</li>\n<li>Work in a fast-paced environment supporting new developments, active deployments, and customer-operated hardware.</li>\n<li>Concurrently manage involvement in multiple projects at various stages.</li>\n<li>Eligible to obtain and maintain an active U.S. Secret security clearance.</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>Bachelor&#39;s Degree in Electrical Engineering or equivalent.</li>\n<li>5+ years of experience designing, testing, and troubleshooting complex board designs and products.</li>\n<li>Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.</li>\n<li>Familiarity with switch-mode power supply design and testing.</li>\n<li>Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.</li>\n<li>Familiarity with common MCU, CPU, FPGA devices and technologies.</li>\n<li>Knowledge of modern analog and digital electronics and electronic circuits.</li>\n<li>Exceptional organization and communication skills (both written and oral).</li>\n<li>Proficient with Altium Designer or equivalent electronic design automation design tools.</li>\n<li>Proficiency with scripting languages (Python, Matlab, etc.).</li>\n<li>Ability to root-cause full-stack HLOS application to hardware component-level issues.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d7d4d506-11e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anduril Industries","sameAs":"https://www.andurilindustries.com/","logo":"https://logos.yubhub.co/andurilindustries.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/andurilindustries/jobs/4905167007","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$98,000-$130,000 USD","x-skills-required":["Digital & Analog Electronics","PCB Design","Component Selection","Layout","Bring-up","Test","Debug","Validation","Characterization","Integration","Switch-Mode Power Supply Design","Testing","Standard Interfaces","Ethernet","CAN","I2C","SPI","PCIe","USB","MCU","CPU","FPGA","Altium Designer","Scripting Languages","Python","Matlab"],"x-skills-preferred":["Complex Board Designs","Troubleshooting","Test Equipment","Oscilloscopes","Logic Analyzers","Thermal Chambers","Current-Probes","Automation of Tests","Exceptional Organization","Communication Skills"],"datePosted":"2026-04-18T15:56:36.850Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Irvine, California, United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Digital & Analog Electronics, PCB Design, Component Selection, Layout, Bring-up, Test, Debug, Validation, Characterization, Integration, Switch-Mode Power Supply Design, Testing, Standard Interfaces, Ethernet, CAN, I2C, SPI, PCIe, USB, MCU, CPU, FPGA, Altium Designer, Scripting Languages, Python, Matlab, Complex Board Designs, Troubleshooting, Test Equipment, Oscilloscopes, Logic Analyzers, Thermal Chambers, Current-Probes, Automation of Tests, Exceptional Organization, Communication Skills","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":98000,"maxValue":130000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_28a0fa12-3a4"},"title":"Senior Circuit Designer","description":"<p>We are seeking a Senior Circuit Designer to join our team.</p>\n<p>As a Senior Circuit Designer, you will be responsible for designing embedded electronics from concept to functional prototype, including hardware selection, schematic &amp; PCB design, board bring-up, and system level integration.</p>\n<p>You will work closely with firmware/software engineers for processor/peripheral selection, board bring up, and troubleshooting.</p>\n<p>You will also work in a fast-paced environment supporting new developments, active deployments, and customer operated hardware.</p>\n<p>Concurrently, you will manage involvement in multiple projects at various stages.</p>\n<p>Required qualifications include a Bachelor’s Degree in Electrical Engineering and 10+ years of experience designing, testing, and troubleshooting complex hardware, embedded systems, and products.</p>\n<p>Experience with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C is also required.</p>\n<p>Additionally, you should have experience with microprocessor and microcontroller selection, configuration, and interfacing, as well as competence with test equipment such as oscilloscopes, logic analyzers, debuggers, current-probes, and automation of tests.</p>\n<p>Exceptional organization and communication skills are also necessary.</p>\n<p>Salary range: $146,000-$194,000 USD.</p>\n<p>Benefits include comprehensive medical, dental, and vision plans, income protection, generous time off, family planning &amp; parenting support, mental health resources, professional development, commuter benefits, relocation assistance, and a retirement savings plan.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_28a0fa12-3a4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anduril","sameAs":"https://www.anduril.com/","logo":"https://logos.yubhub.co/anduril.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/andurilindustries/jobs/5054733007","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$146,000-$194,000 USD","x-skills-required":["multi-gigabit SERDES","DDR memory busses","Ethernet MAC and PHY interfaces","FPGAs","SPI and I2C","microprocessor and microcontroller selection","configuration and interfacing","test equipment such as oscilloscopes, logic analyzers, debuggers, current-probes, and automation of tests"],"x-skills-preferred":[],"datePosted":"2026-04-18T15:52:07.698Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Costa Mesa, California, United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, SPI and I2C, microprocessor and microcontroller selection, configuration and interfacing, test equipment such as oscilloscopes, logic analyzers, debuggers, current-probes, and automation of tests","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":146000,"maxValue":194000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9cd0420a-99d"},"title":"Network Engineer, Capacity and Efficiency","description":"<p><strong>About the Role</strong></p>\n<p>We&#39;re looking for a network engineer who thinks in metrics first. You will use deep networking knowledge and rigorous measurement to figure out where and how bandwidth, latency, and dollars are being used, find optimization opportunities and land them.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Build the network observability stack. Design and deploy telemetry pipelines , sFlow/IPFIX, gNMI streaming, eBPF host probes , that turn packet counters into per-flow, per-tenant, per-workload cost and utilization data. Own the SLIs for backbone and DCN fabric health.</li>\n<li>Hunt for efficiency. Analyze inter-region traffic patterns, identify hot links and stranded capacity, and quantify the dollar impact. Build the models that tell us whether we should buy more capacity, or move the workload.</li>\n<li>Own QoS and traffic engineering. Design and operate traffic classification, marking, and shaping across the backbone. Make sure bulk checkpoint transfers don’t starve latency-sensitive inference, and that we’re not paying premium cross-region rates for traffic that could take the cheap path.</li>\n<li>Drive cost attribution. Tie network spend , egress, interconnect ports, transit, optical leases , back to the teams and workloads that generate it. Make network cost a first-class input to capacity planning and workload placement decisions.</li>\n<li>Influence decisions you don&#39;t own. A large fraction of this role is convincing other teams to act on what your data shows: making the case to research that a traffic pattern needs to change, to finance that an interconnect tranche is worth buying, to Systems Networking that a QoS policy needs rewriting.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Have 5+ years operating large-scale production networks , data center fabrics (spine-leaf, Clos), backbone/WAN, or hyperscaler-adjacent environments.</li>\n<li>Are genuinely fluent across the stack: BGP (including policy and communities), ECMP, VXLAN/EVPN or equivalent overlays, QoS (DSCP, queuing, shaping), and L1/optical basics (DWDM, coherent, LAGs).</li>\n<li>Know at least one major CSP’s networking model deeply , AWS (VPC, TGW, Direct Connect, Gateway Load Balancer) or GCP (Shared VPC, Interconnect, Cloud Router, Network Connectivity Center) , and understand how their overlays interact with physical underlays.</li>\n<li>Have built or operated network telemetry at scale: streaming telemetry (gNMI/OpenConfig), flow export (sFlow, IPFIX, NetFlow), or eBPF-based host-side instrumentation. You can reason about sampling, cardinality, and storage tradeoffs.</li>\n<li>Comfortable writing Python or Go to build tooling, telemetry pipelines, infrastructure-as-code, config management for network devices and automation, that you’ll ship to production.</li>\n<li>Think quantitatively by default. You reach for a notebook or a Grafana query before you reach for an opinion, and you can turn messy counter data into a defensible cost model.</li>\n<li>Communicate crisply. You can explain to a finance partner why a 10% egress reduction matters, and to a network engineer why a specific ECMP imbalance is costing real money.</li>\n</ul>\n<p><strong>Nice to Have</strong></p>\n<ul>\n<li>SRE experience for large-scale network infrastructure , designing for reliability, defining SLOs/SLIs for network services, capacity planning with error budgets, and incident response for network-impacting outages at scale.</li>\n<li>Background on a cloud provider&#39;s networking team or a cloud networking product team , building or operating the interconnect, backbone, or SDN control plane from the provider side, not just consuming it as a customer.</li>\n<li>Familiarity with AI/ML infrastructure traffic patterns like collective communication (all-reduce, all-gather), checkpoint/weight transfer, inference serving, and how these stress networks differ than traditional workloads in terms of burst behavior, flow synchronization, and bandwidth symmetry.</li>\n<li>Experience with HPC fabrics like InfiniBand, RoCE v2, lossless Ethernet, or custom high-radix topologies and an understanding of how job placement, congestion management, and adaptive routing interact at scale.</li>\n<li>Background in traffic engineering for large backbones and the operational judgment to know when TE is worth the complexity.</li>\n<li>Hands-on time with multi-cloud connectivity: cross-cloud peering, private interconnect products, and the billing models that come with them.</li>\n<li>Experience building cost/chargeback systems for shared infrastructure, or FinOps exposure in a large cloud environment.</li>\n</ul>\n<p><strong>Representative Projects</strong></p>\n<ul>\n<li>Build a per-flow cost attribution pipeline that traces every byte of cross-region egress back to the team and workload that generated it</li>\n<li>Design QoS policy for the private backbone that prevents bulk checkpoint transfers from starving inference traffic</li>\n<li>Model whether it&#39;s cheaper to buy an additional 1.6Tb interconnect tranche or to re-route traffic through existing capacity</li>\n<li>Instrument DCN fabric utilization with streaming telemetry and build the Grafana dashboards that become the team&#39;s source of truth for network observability</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9cd0420a-99d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anthropic","sameAs":"https://anthropic.com","logo":"https://logos.yubhub.co/anthropic.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/anthropic/jobs/5177143008","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["network engineering","network observability","telemetry pipelines","sFlow/IPFIX","gNMI streaming","eBPF host probes","BGP","ECMP","VXLAN/EVPN","QoS","DSCP","queuing","shaping","L1/optical basics","DWDM","coherent","LAGs","AWS","GCP","cloud networking","infrastructure-as-code","config management","automation","Python","Go","quantitative analysis","cost modeling","communication"],"x-skills-preferred":["SRE","cloud provider's networking team","cloud networking product team","AI/ML infrastructure traffic patterns","HPC fabrics","traffic engineering","multi-cloud connectivity","cost/chargeback systems","FinOps"],"datePosted":"2026-04-18T15:42:29.482Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco, CA | New York City, NY"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"network engineering, network observability, telemetry pipelines, sFlow/IPFIX, gNMI streaming, eBPF host probes, BGP, ECMP, VXLAN/EVPN, QoS, DSCP, queuing, shaping, L1/optical basics, DWDM, coherent, LAGs, AWS, GCP, cloud networking, infrastructure-as-code, config management, automation, Python, Go, quantitative analysis, cost modeling, communication, SRE, cloud provider's networking team, cloud networking product team, AI/ML infrastructure traffic patterns, HPC fabrics, traffic engineering, multi-cloud connectivity, cost/chargeback systems, FinOps"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f500c2e7-79c"},"title":"Senior Post Silicon Validation Engineer","description":"<p>We are seeking a Senior Post Silicon Validation Engineer to join our team. As a Senior Post Silicon Validation Engineer, you will be responsible for leading the design, automation, and validation of System Level Tests (SLT) for High Volume Manufacturing (HVM) for complex, high power, high speed System-on-Chip (SoC) designs.</p>\n<p>Your primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.</p>\n<p>In addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.</p>\n<p>You will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.</p>\n<p>Finally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.</p>\n<p>To be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.</p>\n<p>Additionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.</p>\n<p>If you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f500c2e7-79c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Post-Silicon-Validation-Engineer_JR2013152","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering","12+ years of relevant industry experience","Experience in post-silicon electrical validation of high power, high speed, complex SoCs","Proven driver and leader of a full system validation from end to end (silicon out to production start) with attention to detail and a passion for root causing issues","Silicon validation experience, preferably in the area of SerDes, LSIO, Logic, and Memory","Experience in system marginality validation","Good understanding of lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.","Strong understanding of Firmware and able to debug and create new test cases","Software proficiency in Python for test scripting, data handling, and reporting","Knowledge of board and package design, signal integrity, data handling, and reporting"],"x-skills-preferred":["Python","Firmware","Lab equipment","Measurement techniques","Signal integrity","Data handling","Reporting"],"datePosted":"2026-03-09T20:43:50.606Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering, 12+ years of relevant industry experience, Experience in post-silicon electrical validation of high power, high speed, complex SoCs, Proven driver and leader of a full system validation from end to end (silicon out to production start) with attention to detail and a passion for root causing issues, Silicon validation experience, preferably in the area of SerDes, LSIO, Logic, and Memory, Experience in system marginality validation, Good understanding of lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc., Strong understanding of Firmware and able to debug and create new test cases, Software proficiency in Python for test scripting, data handling, and reporting, Knowledge of board and package design, signal integrity, data handling, and reporting, Python, Firmware, Lab equipment, Measurement techniques, Signal integrity, Data handling, Reporting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_716d3247-e3f"},"title":"ML/Research Engineer, Safeguards","description":"<p><strong>About Anthropic</strong></p>\n<p>Anthropic&#39;s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems.</p>\n<p><strong>About the role</strong></p>\n<p>We are looking for ML Engineers and Research Engineers to help detect and mitigate misuse of our AI systems. As a member of the Safeguards ML team, you will build systems that identify harmful use—from individual policy violations to sophisticated, coordinated attacks—and develop defenses that keep our products safe as capabilities advance. You will also work on systems that protect user wellbeing and ensure our models behave appropriately across a wide range of contexts. This work feeds directly into Anthropic&#39;s Responsible Scaling Policy commitments.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Develop classifiers to detect misuse and anomalous behavior at scale. This includes developing synthetic data pipelines for training classifiers and methods to automatically source representative evaluations to iterate on</li>\n<li>Build systems to monitor for harms that span multiple exchanges, such as coordinated cyber attacks and influence operations, and develop new methods for aggregating and analyzing signals across contexts</li>\n<li>Evaluate and improve the safety of agentic products—developing both threat models and environments to test for agentic risks, and developing and deploying mitigations for prompt injection attacks</li>\n<li>Conduct research on automated red-teaming, adversarial robustness, and other research that helps test for or find misuse</li>\n</ul>\n<p><strong>You may be a good fit if you</strong></p>\n<ul>\n<li>Have 4+ years of experience in ML engineering, research engineering, or applied research, in academia or industry</li>\n<li>Have proficiency in Python and experience building ML systems</li>\n<li>Are comfortable working across the research-to-deployment pipeline, from exploratory experiments to production systems</li>\n<li>Are worried about misuse risks of AI systems, and want to work to mitigate them</li>\n<li>Have strong communication skills and ability to explain complex technical concepts to non-technical stakeholders</li>\n</ul>\n<p><strong>Strong candidates may also have experience with</strong></p>\n<ul>\n<li>Language modeling and transformers</li>\n<li>Building classifiers, anomaly detection systems, or behavioral ML</li>\n<li>Adversarial machine learning or red-teaming</li>\n<li>Interpretability or probes</li>\n<li>Reinforcement learning</li>\n<li>High-performance, large-scale ML systems</li>\n</ul>\n<p><strong>Logistics</strong></p>\n<p><strong>Education requirements:</strong> We require at least a Bachelor&#39;s degree in a related field or equivalent experience. <strong>Location-based hybrid policy:</strong> Currently, we expect all staff to be in one of our offices at least 25% of the time. However, some roles may require more time in our offices.</p>\n<p><strong>Visa sponsorship</strong></p>\n<p>We do sponsor visas! However, we aren&#39;t able to successfully sponsor visas for every role and every candidate. But if we make you an offer, we will make every reasonable effort to get you a visa, and we retain an immigration lawyer to help with this.</p>\n<p><strong>We encourage you to apply even if you do not believe you meet every single qualification.</strong></p>\n<p>Not all strong candidates will meet every single qualification as listed. Research shows that people who identify as being from underrepresented groups are more prone to experiencing imposter syndrome and doubting the strength of their candidacy, so we urge you not to exclude yourself prematurely and to submit an application if you&#39;re interested in this work.</p>\n<p><strong>Your safety matters to us.</strong></p>\n<p>To protect yourself from potential scams, remember that Anthropic recruiters only contact you from @anthropic.com email addresses. In some cases, we may partner with vetted recruiting agencies who will identify themselves as working on behalf of Anthropic. Be cautious of emails from other domains. Legitimate Anthropic recruiters will never ask for money, fees, or banking information before your first day. If you&#39;re ever unsure about a communication, don&#39;t click any links—visit anthropic.com/careers directly for confirmed position openings.</p>\n<p><strong>How we&#39;re different</strong></p>\n<p>We believe that the highest-impact AI research will be big science. At Anthropic we work as a single cohesive team on just a few large-scale research efforts. And we value impact — advancing our long-term goals of steerable, trustworthy AI — rather than work on smaller and more specific puzzles. We view AI research as an empirical science, which has as much in common with physics and biology as with traditional efforts in computer science. We&#39;re an extremely collaborative group, and we host frequent research discussions to ensure that we are pursuing the highest-impact work at any given time. As such, we greatly value communication skills.</p>\n<p>The easiest way to understand our research directions is to read our recent research. This research continues many of the directions our team worked on prior to Anthropic, including: GPT-3, Circuit-Based Interpretability, Multimodal Neurons, Scaling Laws, AI &amp; Compute, Concrete Problems in AI Safety, and Learning from Human Preferences.</p>\n<p><strong>Come work with us!</strong></p>\n<p>Anthropic is a public benefit corporation headquartered in San Francisco. We offer competitive compensation and benefits, optional</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_716d3247-e3f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anthropic","sameAs":"https://job-boards.greenhouse.io","logo":"https://logos.yubhub.co/anthropic.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/anthropic/jobs/4949336008","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$350,000 - $500,000USD","x-skills-required":["Python","Machine Learning","Research Engineering","Adversarial Machine Learning","Red-teaming","Interpretability","Probes","Reinforcement Learning","High-performance, large-scale ML systems"],"x-skills-preferred":["Language modeling and transformers","Building classifiers, anomaly detection systems, or behavioral ML"],"datePosted":"2026-03-08T13:46:45.711Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco, CA | New York City, NY"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Python, Machine Learning, Research Engineering, Adversarial Machine Learning, Red-teaming, Interpretability, Probes, Reinforcement Learning, High-performance, large-scale ML systems, Language modeling and transformers, Building classifiers, anomaly detection systems, or behavioral ML","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":350000,"maxValue":500000,"unitText":"YEAR"}}}]}