At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 12+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions.

What You’ll Be Doing:

• Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

• Collaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.

• Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.

• Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.

• Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.

The Impact You Will Have:

• Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.

• Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.

• Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.

• Position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.

• Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.

• Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.

What You’ll Need:

• Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.

• 15+ years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.

• Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.

• In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.

• Experience with LLMs, GPT models, and other generative AI techniques.

• Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.

Who You Are:

• Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.

• Excellent communicator, able to clearly articulate technical concepts to diverse audiences.

• Collaborative team player who thrives in a fast-paced, cross-functional environment.

• Customer-focused mindset with a passion for delivering exceptional support and building lasting relationships.

• Effective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.

The Team You’ll Be A Part Of:

You will join a high-impact Applications Engineering team focused on enabling customer success with Synopsys’ most advanced physical design solutions. This collaborative group works at the intersection of technology development and customer engagement, driving innovation and excellence in chip design across global semiconductor leaders. The team values knowledge sharing, mentorship, and continuous learning, fostering a supportive environment where everyone can make a significant impact.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Engineering, Principal Engineer

Bengaluru, Karnataka, India

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Hire Type EmployeeJob ID 17045Date posted 04/27/2026

A peek inside our office

Po Popal

Workplace Resources, Sr Director

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 12+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.

What You’ll Be Doing:

• Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

• Collaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.

• Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.

• Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.

• Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.

The Impact You Will Have:

• Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.

• Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.

• Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.

• Position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.

• Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.

• Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.

What You’ll Need:

• Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.

• 15+ years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.

• Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.

• In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.

• Experience with LLMs, GPT models, and other generative AI techniques.

• Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.

Who You Are:

• Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.

• Excellent communicator, able to clearly articulate technical concepts to diverse audiences.

• Collaborative team player who thrives in a fast-paced, cross-functional environment.

• Customer-focused mindset with a passion for delivering exceptional support and building lasting relationships.

• Effective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.

The Team You’ll Be A Part Of:

You will join a high-impact Applications Engineering team focused on enabling customer success with Synopsys’ most advanced physical design solutions. This collaborative group works at the intersection of technology development and customer engagement, driving innovation and excellence in chip design across global semiconductor leaders. The team values knowledge sharing, mentorship, and continuous learning, fostering a supportive environment where everyone can make a significant impact.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You take pride in solving the toughest physical design problems, the kind where advanced nodes, tight margins, and complex IP all collide. You're the one who spots timing issues before they're fire drills and who automates flows so the team can actually sleep before tape-out. If a tool throws a curveball, you debug and document, not just fix for yourself. You like working across teams,architecture, RTL, circuits,because you know every decision you make echoes downstream. You want your work to ship and matter. At Synopsys, you'll own the path from RTL to GDS and raise the bar for everyone around you.

Key responsibilities include:

• Owning and optimizing RTL-to-GDSII flow for UCIE IP, including STA and signoff (PrimeTime, IC Compiler II, ICV, RedHawk)
• Integrating covercells, macros, and IP, ensuring clean abutment and QA
• Automating tool flows, debugging issues, and documenting best practices
• Collaborating with architecture, RTL, and circuit teams on test chip development
• Preparing tape-out views, documentation, and managing foundry checklists

Impact you'll have:

• Deliver high-quality, high-performance UCIE IP that meets aggressive PPA goals
• Eliminate late-stage surprises through robust flows and early issue detection
• Save team time by automating repeatable tasks and sharing solutions
• Enable smooth integration for SoC teams and downstream users
• Raise technical standards and reliability across projects

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You are the person teams turn to when timing closure looks impossible and the clock tree feels like a puzzle with missing pieces. You know the difference between a design that passes signoff and one that ships with margin to spare, because you have spent years making those calls at 7nm and below. You do not just push buttons in ICC2 or PrimeTime,you know why a constraint matters, and you catch issues before they ripple downstream. When someone asks about integrating a tricky mixed-signal macro, you have a mental toolkit of what can go wrong and how to make it work. You thrive on the hard problems: GHz-level timing, power optimization, and the reality of silicon bring-up. You want your work to show up in real products, not just in a tapeout report. Sharing what you know is second nature,mentoring junior engineers, reviewing a teammate’s floorplan, or explaining a tradeoff to a colleague in the US. You care about getting the details right, but you do not get stuck in them. You move projects forward, ask the right questions, and always look for a better way to do things.

Implement and integrate Physical Design for ASICs at advanced nodes (10nm, 7nm, 6nm and below) using tools like Synopsys ICC2, PrimeTime, and StarRC. Drive timing closure for high-frequency designs above 4GHz, handling constraint management, analysis, and optimization. Work hands-on with clock tree synthesis, skew balancing, and robust clock distribution for complex SoCs and IPs. Collaborate closely with teams in Bangalore and the US, joining technical discussions, design reviews, and troubleshooting sessions. Integrate mixed-signal hard macro IPs, solving unique interface and floorplan challenges as they arise. Mentor junior engineers, sharing best practices and elevating the team’s technical capability. Develop and optimize automation scripts in Tcl, Perl, or Python to streamline physical design flows and improve productivity. Support and improve methodologies for floorplanning, placement, routing, and power optimization.

Deliver HPC Controller IPs that will power the next wave of consumer and enterprise devices. Push Synopsys’ reputation for silicon-proven, high-performance IP at the most advanced process nodes. Raise the bar for quality and innovation in timing closure, clock tree synthesis, and mixed-signal integration. Help global teams align and execute, ensuring projects hit milestones and customers get what they need, on time. Enable faster, more robust tapeouts by improving design flows and mentoring the next generation of engineers. Influence product differentiation through hands-on technical contributions and creative problem solving. Shorten time-to-market for customers by anticipating and solving critical design challenges early.

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As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.

Key Responsibilities:

• Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
• Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
• Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
• Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
• Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
• Driving tool flow automation and debugging to enhance productivity and design reliability.
• Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.

Impact:

• Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
• Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
• Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
• Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
• Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
• Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.

Requirements:

• 6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
• Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
• Familiarity with IP integration, test chip methodology, and advanced verification flows.
• Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
• Experience coordinating complex, cross-functional projects and leading technical execution.
• Authorization to work in the USA.

Team:

You'll join the Test Chip PHY development team within Synopsys's Silicon IP business. This group is dedicated to integrating and validating Synopsys's broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Driving increased adoption and usage of Synopsys PrimeTime and ECO in both pre-sale and post-sale engagements with customers.
• Conducting in-depth competitive benchmarks and product evaluations to demonstrate PrimeTime's technical and business advantages.
• Providing expert-level training, onboarding, and technical support to empower customers through successful chip tapeouts.
• Collaborating with R&D, marketing, and sales teams to define requirements and influence enhancements to PrimeTime's features.
• Engaging directly with customers to gather actionable feedback and advocate for their needs within Synopsys.
• Articulating complex technical solutions and methodologies to diverse audiences, from design engineers to senior management.
• Troubleshooting critical issues related to timing closure, signal integrity, and process variations.

As a Sr Staff Engineer, you will have a significant impact on customer satisfaction, product adoption, and the strengthening of Synopsys's market presence. You will also contribute to the company's reputation as a global leader and innovator in electronic design automation.

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You will drive customer scenario reproduction, deep-dive debugging, and root-cause analysis of complex, cross-component issues. You will proactively identify product weak areas, corner cases, and scalability/performance risks and ensure early detection. You will work closely with R&D, Product Engineering, and Field teams to clarify requirements, influence design decisions, validate fixes, and ensure smooth integration.

You will lead functional, regression, stress, accuracy, and sign-off-oriented testing for STA features and advanced flows. You will architect and enhance automation frameworks using Perl, Tcl, and Python to improve productivity, robustness, and validation coverage. You will analyze large-scale validation and regression data to identify trends, systemic gaps, and improvement opportunities.

You will effectively leverage AI-assisted engineering tools (e.g., VS Code / Cursor-based workflows with multiple LLMs) for faster testcase and automation script development, debug acceleration and hypothesis generation, log analysis, flow understanding, and code reviews. You will apply sound technical judgment to validate, review, and refine AI-assisted outputs, ensuring correctness, accuracy, and compliance with quality standards.

You will prepare and present clear, executive-ready validation status, quality metrics, risks, and recommendations. You will participate in feature readiness reviews, postmortems, and continuous improvement initiatives. You will drive best practices in validation methodology, tooling, and knowledge sharing across the team.

As a STA PrimeTime Test & Validation Sr Specialist, you will own and drive quality sign-off for critical PrimeTime STA features. You will significantly reduce customer-reported issues through proactive, risk-based validation. You will improve tool accuracy, robustness, scalability, and real-world customer readiness. You will strengthen cross-team alignment by serving as a trusted technical Subject Matter Expert (SME).

You will elevate overall team capability through mentorship, technical leadership, and adoption of modern productivity tools. You will influence product roadmap and feature decisions through validation-driven insights.

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You will be responsible for owning and evolving major architectural components of PrimeTime, including timing engines, path search frameworks, constraint modeling, and distributed/parallel analysis flows. You will define long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis, collaborating closely with senior R&D leadership.

Key responsibilities include:

• Owning and evolving major architectural components of PrimeTime
• Defining long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis
• Driving architectural consistency across PrimeTime, Fusion Compiler integration points, and broader sign-off ecosystems
• Leading the design and implementation of next-generation STA algorithms addressing multi-billion-cell designs, advanced timing effects, and non-linear behaviours
• Resolving cross-cutting technical issues and making principled tradeoffs between accuracy, performance, memory footprint, and usability at sign-off
• Acting as the go-to technical authority for customer escalations, sign-off discrepancies, and complex architectural challenges
• Diagnosing systemic issues involving SDC interpretation, timing convergence, path pessimism/optimism, and tool correlations across flows
• Mentoring and influencing engineers through technical reviews, discussions, and leadership,raising the technical bar across the organization

As a Sr Staff Engineer, you will have a strong sense of ownership and accountability, and be able to drive technical excellence and innovation. You will be a collaborative influencer, able to mentor and inspire technical teams, and have excellent communication skills, capable of articulating complex technical concepts to diverse audiences.

You will join a team that is passionate about delivering innovative solutions that define industry standards for timing sign-off. Together, you will tackle complex architectural challenges, drive technical excellence, and shape the future of silicon design by enabling customers to achieve reliable and high-performance tapeouts.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.

Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.

• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.

• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.

• Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.

• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.

• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.

• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.

• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.

• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.

• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.

• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

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We currently have 700 open roles.

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STA PrimeTime Test & Validation Sr Specialist

Technical Leadership & Validation Ownership

• Lead and own validation of complex PrimeTime STA features and flows, from requirement analysis through quality sign-off.
• Define and drive validation strategy, depth, and coverage for assigned functional areas.
• Act as technical lead for L1/L2 engineers, providing guidance on STA concepts, debugging approaches, testcase design, and best practices.
• Review and approve validation plans, testcases, regression results, and quality sign-off metrics.

Product Quality, Debug, and Cross-Team Collaboration

• Drive customer scenario reproduction, deep-dive debugging, and root-cause analysis of complex, cross-component issues.
• Proactively identify product weak areas, corner cases, and scalability/performance risks and ensure early detection.
• Work closely with R&D, Product Engineering, and Field teams to clarify requirements, influence design decisions, validate fixes, and ensure smooth integration.
• Lead functional, regression, stress, accuracy, and sign-off-oriented testing for STA features and advanced flows.

Automation, Data Analysis & AI-Assisted Productivity

• Architect and enhance automation frameworks using Perl, Tcl, and Python to improve productivity, robustness, and validation coverage.
• Analyze large-scale validation and regression data to identify trends, systemic gaps, and improvement opportunities.
• Effectively leverage AI-assisted engineering tools (e.g., VS Code / Cursor-based workflows with multiple LLMs) for:
• Faster testcase and automation script development
• Debug acceleration and hypothesis generation
• Log analysis, flow understanding, and code reviews
• Improving documentation quality and consistency
• Apply sound technical judgment to validate, review, and refine AI-assisted outputs, ensuring correctness, accuracy, and compliance with quality standards.

Communication & Continuous Improvement

• Prepare and present clear, executive-ready validation status, quality metrics, risks, and recommendations.
• Participate in feature readiness reviews, postmortems, and continuous improvement initiatives.
• Drive best practices in validation methodology, tooling, and knowledge sharing across the team.

The Impact You Will Have

• Own and drive quality sign-off for critical PrimeTime STA features.
• Significantly reduce customer-reported issues through proactive, risk-based validation.
• Improve tool accuracy, robustness, scalability, and real-world customer readiness.
• Strengthen cross-team alignment by serving as a trusted technical Subject Matter Expert (SME).
• Elevate overall team capability through mentorship, technical leadership, and adoption of modern productivity tools.
• Influence product roadmap and feature decisions through validation-driven insights.

What You’ll Need

• Strong, hands-on understanding of Static Timing Analysis fundamentals.
• BSEE with 5+ years of relevant experience OR MSEE with 4+ years of relevant experience.
• Deep hands-on experience with:
• Synopsys PrimeTime or equivalent STA tools
• Advanced timing concepts, SDC constraints, and real-world sign-off scenarios
• OCV/AOCV/POCV, derates, PBA, ECO, and what-if analysis flows
• Hierarchical, distributed, and large-scale STA flows
• Proven ability to debug complex, ambiguous, cross-component issues.
• Strong proficiency in Perl, Tcl, and Python for automation and framework development.
• Experience using AI-assisted development tools responsibly to enhance engineering productivity and validation quality.
• Track record of technical ownership, leadership, and sound decision-making.
• High standards for quality, rigor, documentation, and sign-off discipline.

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Architect, AI Solutions – Digital IP Methodology & Solutions

Sunnyvale, California, United States

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Hire Type EmployeeJob ID 17037Base Salary Range $208000-$312000Date posted 04/21/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 20+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.

You excel in dynamic, high-performance teams, proactively sharing knowledge and mentoring peers. Your communication skills enable you to translate technical complexities into actionable insights for both customers and colleagues. You are innovative, adaptable, and eager to stay ahead in a fast-evolving domain. Your passion for continuous learning and improvement drives you to explore new methodologies, ensuring customer success and the advancement of Synopsys’ cutting-edge tools.

Above all, you are motivated by the impact of your work on the semiconductor industry and the broader technology landscape. You are ready to be a technical leader and trusted advisor, shaping the future of physical design and pushing the boundaries of what’s possible.

What You’ll Be Doing:

• Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

• Collaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.

• Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.

• Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.

• Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.

The Impact You Will Have:

• Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.

• Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.

• Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.

• Position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.

• Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.

• Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.

What You’ll Need:

• Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.

• 15+ plus years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.

• Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.

• In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.

• Experience with LLMs, GPT models, and other generative AI techniques.

• Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.

Who You Are:

• Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.

• Excellent communicator, able to clearly articulate technical concepts to diverse audiences.

• Collaborative team player who thrives in a fast-paced, cross-functional environment.

• Customer-focused mindset with a passion for delivering exceptional support and building lasting relationships.

• Effective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a Sr Director of ASIC Physical Design, you will own and drive the end-to-end physical design flow for high-speed die-to-die interconnect and interface chips targeting 2 GHz+ on advanced process nodes (sub-7nm/5nm/3nm).

Key responsibilities include:

• Leading floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification with emphasis on die-to-die interface placement and bump/pad ring constraints.

• Achieving timing closure across all corners and modes, with expertise in multi-corner multi-mode sign-off for high-speed serial and parallel interfaces.

• Driving power integrity, signal integrity, and thermal analysis to meet stringent tape-out criteria for high-bandwidth die-to-die links.

• Defining and owning physical design methodology, Synopsys tool flows, and best practices across the organization.

• Building, mentoring, and leading a globally distributed team, establishing effective communication and collaboration norms to foster cohesion and engineering excellence.

• Collaborating cross-functionally with RTL design, DV, architecture, CAD/EDA, and program management teams globally.

• Owning physical design schedules and milestones for multiple concurrent projects, communicating status to senior leadership and mitigating risks proactively.

• Championing automation and scripting to improve PPA outcomes and team productivity.

The impact you will have:

• Enable the physical implementation of high-speed die-to-die interconnects that power large-scale AI accelerators, GPU clusters, and multi-die systems.

• Deliver ultra-low latency, high-bandwidth chip-to-chip communication at the core of next-generation AI infrastructure.

• Advance the adoption of cutting-edge process nodes and interface standards, positioning Synopsys as a leader in silicon innovation.

• Ensure robust engineering quality, execution velocity, and successful tape-outs across global teams.

• Drive organizational excellence by fostering a culture of accountability, growth, and technical mastery.

• Shape methodologies and tool flows that set industry benchmarks for high-speed, advanced-node physical design.

• Contribute to the strategic direction of AI silicon and interconnect products, impacting the broader technology ecosystem.

Requirements:

• 15+ years of hands-on physical design experience, with deep expertise in high-frequency (≥2 GHz) chip design.

• Expertise with Synopsys IC Compiler II (ICC2), PrimeTime, Fusion Compiler, StarRC, IC Validator, and PrimePower.

• Track record of taping out high-speed interface ICs, die-to-die interconnect chips, SerDes, or similar designs at advanced process nodes (7nm, 5nm, 3nm).

• Understanding of die-to-die interface standards and protocols (UCIe, BoW, HBI, XSR, or proprietary) and their physical implementation.

• Experience with power intent flows (UPF/CPF), low-power design techniques, and dynamic/static power optimization.

• Strong scripting skills (Tcl, Python, Perl) for tool flow automation and PPA optimization.

• Proven ability to lead and grow globally distributed engineering teams of 10+ people.

• Cross-cultural communication and collaboration skills; experience working across US, Asia, or European engineering centers.

• BS or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).

As a Sr Director of ASIC Physical Design, you will join a globally distributed Silicon Engineering team focused on the physical implementation of cutting-edge AI silicon and high-speed die-to-die interconnects.

Our team spans multiple sites and time zones, collaborating with process technology, packaging, RTL, DV, architecture, CAD/EDA, and program management teams.

We pride ourselves on a culture of technical depth, low bureaucracy, and a relentless drive for engineering excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Staff Engineer in ASIC Physical Design, you will contribute to the development of advanced semiconductor solutions, collaborating with cross-functional teams to design, verify, and manufacture complex SoCs and test chips. Your expertise in the physical design flow and familiarity with industry-leading tools will enable you to drive technical execution and lead complex projects.

Key Responsibilities:

• Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
• Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
• Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
• Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
• Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
• Driving tool flow automation and debugging to enhance productivity and design reliability.
• Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.

Impact:

• Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
• Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
• Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
• Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
• Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
• Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.

Requirements:

• 9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
• Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
• Familiarity with IP integration, test chip methodology, and advanced verification flows.
• Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
• Experience coordinating complex, cross-functional projects and leading technical execution.
• Authorization to work in the USA.

Team:

You'll join the Test Chip PHY development team within Synopsys's Silicon IP business. This group is dedicated to integrating and validating Synopsys's broad portfolio of IP blocks,logic, memory, interfaces, analog, security, and embedded processors,into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Staff Engineer in SOC Engineering, you will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. You will execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

Key Responsibilities:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence
• Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency

Key Requirements:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm)
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs
• Exposure to high-frequency design and low-power design methodologies

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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What you'll do

• Apply engineering expertise to support EDA product specifications and deployment for leading semiconductor design houses and foundries.
• Engage directly with global customers, IP providers, and foundries to understand and address design challenges for cutting-edge SoCs and 3DICs.

What you need

• At least 5+ years of experience in the semiconductor domain, with a strong background in STA analysis, ECO, timing closure, or PDN at block or SoC level.
• Proficiency in providing technical support for PDN and/or Timing Signoff domains, with proven ability to assist clients and resolve issues.

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