{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/primetime"},"x-facet":{"type":"skill","slug":"primetime","display":"Primetime","count":25},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_524edc8e-463"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_524edc8e-463","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-staff-engineer-16723/44408/93743819104","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Floor planning","Synthesis","Placement and routing","Timing closure","IP integration","Test chip methodology","Advanced verification flows","CAD tools","Design Compiler","PrimeTime","IC Compiler II/FC","ICV","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:19:07.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Floor planning, Synthesis, Placement and routing, Timing closure, IP integration, Test chip methodology, Advanced verification flows, CAD tools, Design Compiler, PrimeTime, IC Compiler II/FC, ICV, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_98bbddfd-457"},"title":"Applications Engineering, Sr Staff Engineer - Static Timing Analysis (STA)","description":"<p>We are seeking a highly skilled Applications Engineer with deep expertise in Static Timing Analysis (STA) to join our team. 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You will also provide expert-level training, onboarding, and technical support to empower customers through successful chip tapeouts.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Driving increased adoption and usage of Synopsys PrimeTime and ECO in both pre-sale and post-sale engagements with customers.</li>\n<li>Conducting in-depth competitive benchmarks and product evaluations to demonstrate PrimeTime&#39;s technical and business advantages.</li>\n<li>Providing expert-level training, onboarding, and technical support to empower customers through successful chip tapeouts.</li>\n<li>Collaborating with R&amp;D, marketing, and sales teams to define requirements and influence enhancements to PrimeTime&#39;s features.</li>\n<li>Engaging directly with customers to gather actionable feedback and advocate for their needs within Synopsys.</li>\n<li>Articulating complex technical solutions and methodologies to diverse audiences, from design engineers to senior management.</li>\n<li>Troubleshooting critical issues related to timing closure, signal integrity, and process variations.</li>\n</ul>\n<p>As a Sr Staff Engineer, you will have a significant impact on customer satisfaction, product adoption, and the strengthening of Synopsys&#39;s market presence. You will also contribute to the company&#39;s reputation as a global leader and innovator in electronic design automation.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_98bbddfd-457","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/holon/applications-engineering-sr-staff-engineer-static-timing-analysis-sta/44408/94283087888","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Static Timing Analysis (STA)","PrimeTime","ECO","timing closure","signal integrity","process variations"],"x-skills-preferred":["scripting skills (Tcl, Perl, or Python)","automating STA flows"],"datePosted":"2026-04-24T14:17:27.940Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Holon, Tel Aviv, Israel"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Static Timing Analysis (STA), PrimeTime, ECO, timing closure, signal integrity, process variations, scripting skills (Tcl, Perl, or Python), automating STA flows"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e34499cc-52a"},"title":"STA PrimeTime Test & Validation Sr Specialist","description":"<p>We are seeking a highly skilled and technically strong Lead Validation Engineer with deep expertise in Static Timing Analysis (STA) and PrimeTime flows. As a STA PrimeTime Test &amp; Validation Sr Specialist, you will lead and own validation of complex PrimeTime STA features and flows, from requirement analysis through quality sign-off. You will define and drive validation strategy, depth, and coverage for assigned functional areas. You will act as technical lead for L1/L2 engineers, providing guidance on STA concepts, debugging approaches, testcase design, and best practices.</p>\n<p>You will drive customer scenario reproduction, deep-dive debugging, and root-cause analysis of complex, cross-component issues. You will proactively identify product weak areas, corner cases, and scalability/performance risks and ensure early detection. You will work closely with R&amp;D, Product Engineering, and Field teams to clarify requirements, influence design decisions, validate fixes, and ensure smooth integration.</p>\n<p>You will lead functional, regression, stress, accuracy, and sign-off-oriented testing for STA features and advanced flows. You will architect and enhance automation frameworks using Perl, Tcl, and Python to improve productivity, robustness, and validation coverage. You will analyze large-scale validation and regression data to identify trends, systemic gaps, and improvement opportunities.</p>\n<p>You will effectively leverage AI-assisted engineering tools (e.g., VS Code / Cursor-based workflows with multiple LLMs) for faster testcase and automation script development, debug acceleration and hypothesis generation, log analysis, flow understanding, and code reviews. You will apply sound technical judgment to validate, review, and refine AI-assisted outputs, ensuring correctness, accuracy, and compliance with quality standards.</p>\n<p>You will prepare and present clear, executive-ready validation status, quality metrics, risks, and recommendations. You will participate in feature readiness reviews, postmortems, and continuous improvement initiatives. You will drive best practices in validation methodology, tooling, and knowledge sharing across the team.</p>\n<p>As a STA PrimeTime Test &amp; Validation Sr Specialist, you will own and drive quality sign-off for critical PrimeTime STA features. You will significantly reduce customer-reported issues through proactive, risk-based validation. You will improve tool accuracy, robustness, scalability, and real-world customer readiness. You will strengthen cross-team alignment by serving as a trusted technical Subject Matter Expert (SME).</p>\n<p>You will elevate overall team capability through mentorship, technical leadership, and adoption of modern productivity tools. You will influence product roadmap and feature decisions through validation-driven insights.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e34499cc-52a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/sta-primetime-test-and-validation-sr-specialist/44408/94220125168","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Static Timing Analysis","PrimeTime","Perl","Tcl","Python","AI-assisted engineering tools","VS Code","Cursor-based workflows","multiple LLMs"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:16:25.444Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Static Timing Analysis, PrimeTime, Perl, Tcl, Python, AI-assisted engineering tools, VS Code, Cursor-based workflows, multiple LLMs"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cd352346-abd"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutionsΈ. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes</li>\n<li>Driving timing closure efforts, especially above ~2GHz</li>\n<li>Resolving complex challenges related to mixed signal and macro IP integration</li>\n<li>Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements</li>\n<li>Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams</li>\n<li>Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects</li>\n<li>Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications</li>\n<li>Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)</li>\n<li>Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration</li>\n<li>Strong analytical and problem-solving skills, with a track record of resolving complex technical issues</li>\n<li>Ability to independently lead project tasks, mentor junior team members, and work collaboratively</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away from work for vacation, sick leave, and family care</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP (Employee Stock Purchase Plan)</li>\n<li>Retirement plans</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cd352346-abd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-physical-design-staff-engineer/44408/94169001536","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR/HBM/HBI IP integration","Timing closure","Mixed signal and macro IP integration","Clock tree design"],"x-skills-preferred":["Design Compiler (DC)","IC Compiler II (ICC2)","PrimeTime SI (PT-SI)","Formality (FC)"],"datePosted":"2026-04-24T14:16:07.686Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR/HBM/HBI IP integration, Timing closure, Mixed signal and macro IP integration, Clock tree design, Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), Formality (FC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_199e305e-039"},"title":"Application Engineering, Sr Engineer","description":"<p>Engineer the Future with Us</p>\n<p>We currently have 700 open roles</p>\n<p>Innovation Starts Here</p>\n<p>Find Jobs For</p>\n<p>Where?When autocomplete results are available use up and down arrows to review and enter to select. Touch device users, explore by touch or with swipe gestures.</p>\n<p><strong>Application Engineering, Sr Enginer</strong></p>\n<p>Bengaluru, Karnataka, India</p>\n<p>Save</p>\n<p><strong>Hire Type</strong> Employee<strong>Job ID</strong> 17054<strong>Date posted</strong> 04/20/2026</p>\n<p>A peek inside our office</p>\n<p>Po Popal</p>\n<p>Workplace Resources, Sr Director</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Applications Engineer – Static Timing Analysis</li>\n<li>PrimeTime Specialist</li>\n<li>STA Solutions Engineer</li>\n<li>Silicon Verification Engineer</li>\n<li>Customer Success Engineer – EDA Tools</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.</p>\n<p>Our Silicon Design &amp; Verification business is all about building high-performance silicon chips,faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance,eliminating months off their project schedules.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned engineer with a keen interest in cutting-edge semiconductor technology and a passion for delivering customer-centric solutions. With a strong background in static timing analysis, you understand the intricacies of chip design and the critical role of timing verification in successful tapeouts. You thrive on solving complex technical challenges, whether through competitive benchmarking, customer training, or advanced collaboration initiatives. Your experience with Synopsys PrimeTime sets you apart, and you’re adept at explaining technical concepts to both engineers and management audiences.</p>\n<p>You possess exceptional communication skills, enabling you to build relationships and foster trust with customers and internal teams alike. You are comfortable leading technical discussions, delivering workshops, and supporting users through the entire lifecycle of their projects. Your analytical mindset helps you dissect timing-related issues, process variations, and signal integrity challenges, ensuring that your customers achieve optimal results.</p>\n<p>As a collaborative team player, you value diverse perspectives and enjoy working across functions,including R&amp;D, marketing, and sales,to drive product enhancements and customer satisfaction. You are proactive, resourceful, and adaptable, always ready to learn and grow in a fast-evolving industry. Your dedication to excellence and innovation makes you a valuable asset to Synopsys and its customers.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Driving increased adoption of Synopsys PrimeTime by executing competitive benchmarks and product evaluations for customers.</li>\n<li>Articulating product advantages and technical superiority to customer design teams and management in both pre-sale and post-sale engagements.</li>\n<li>Delivering customer training sessions, workshops, and hands-on support to enhance user proficiency and satisfaction.</li>\n<li>Providing tape-out support, troubleshooting timing issues, and guiding customers through complex design challenges.</li>\n<li>Collaborating with R&amp;D, marketing, and sales teams to relay customer feedback and contribute to product enhancements.</li>\n<li>Engaging in advanced initiatives that foster innovation and strengthen customer relationships.</li>\n<li>Developing technical documentation and best practices to streamline customer adoption and usage.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerating customer project schedules by enabling efficient and accurate timing analysis using PrimeTime.</li>\n<li>Enhancing product usage and satisfaction, driving customer loyalty and long-term partnerships.</li>\n<li>Contributing to the continuous improvement of Synopsys STA tools by providing actionable insights from real-world customer engagements.</li>\n<li>Supporting industry-leading chip design teams in achieving successful tapeouts and meeting performance targets.</li>\n<li>Empowering customers to overcome complex timing, process variation, and signal integrity challenges.</li>\n<li>Strengthening Synopsys’ reputation as the provider of choice for advanced silicon design and verification solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Hands-on experience with Synopsys PrimeTime static timing analysis tool.</li>\n<li>Deep understanding of timing corners, modes, process variations, and signal integrity issues.</li>\n<li>Familiarity with synthesis, physical design, extraction, and ECO methodologies.</li>\n<li>Strong proficiency in TCL scripting for tool customization and automation.</li>\n<li>Excellent verbal and written communication skills, with prior customer-facing experience preferred.</li>\n<li>BSEE or equivalent with 3–5 years of relevant experience, or MSEE/equivalent with 2–4 years.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Clear, confident communicator able to engage technical and non-technical audiences.</li>\n<li>Analytical problem-solver with a detail-oriented approach to complex technical challenges.</li>\n<li>Collaborative team player who thrives in cross-functional environments.</li>\n<li>Adaptable and resourceful, comfortable with evolving technologies and project priorities.</li>\n<li>Customer-focused, demonstrating empathy and proactive support.</li>\n<li>Self-motivated, eager to learn and contribute to innovation.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the applications engineering team supporting the industry-leading Static Timing Analysis tool, PrimeTime. The team’s mission is to drive customer success by delivering expert guidance and technical support, ensuring seamless adoption and optimal usage of Synopsys STA solutions. Working closely with customers and internal stakeholders, the team fosters a culture of innovation, collaboration, and continuous improvement, shaping the next generation of chip design and verification technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_199e305e-039","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/application-engineering-sr-enginer/44408/94212498304","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"Competitive salary and benefits package","x-skills-required":["Synopsys PrimeTime","static timing analysis","chip design","signal integrity","TCL scripting","physical design","synthesis","ECO methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:16:00.977Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Synopsys PrimeTime, static timing analysis, chip design, signal integrity, TCL scripting, physical design, synthesis, ECO methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6038d71f-d7d"},"title":"R&D Engineering, Sr Staff Engineer- PrimeTime (Static Timing Analysis)","description":"<p>You will join a world-class R&amp;D team dedicated to advancing the PrimeTime platform, collaborating with experts in static timing analysis, algorithm design, and EDA systems. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.</p>\n<p>Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n</ul>\n<ul>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n</ul>\n<ul>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n</ul>\n<ul>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n</ul>\n<ul>\n<li>Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n</ul>\n<ul>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n</ul>\n<ul>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n</ul>\n<ul>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n</ul>\n<ul>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n</ul>\n<ul>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n</ul>\n<ul>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n</ul>\n<ul>\n<li>Support strategic customer engagements and help expand Synopsys&#39; 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Touch device users, explore by touch or with swipe gestures.</p>\n<p><strong>Architect, AI Solutions – Digital IP Methodology &amp; Solutions</strong></p>\n<p>Sunnyvale, California, United States</p>\n<p>Save</p>\n<p><strong>Hire Type</strong> Employee<strong>Job ID</strong> 17037<strong>Base Salary Range</strong> $208000-$312000<strong>Date posted</strong> 04/21/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 20+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place &amp; route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.</p>\n<p>You excel in dynamic, high-performance teams, proactively sharing knowledge and mentoring peers. Your communication skills enable you to translate technical complexities into actionable insights for both customers and colleagues. You are innovative, adaptable, and eager to stay ahead in a fast-evolving domain. Your passion for continuous learning and improvement drives you to explore new methodologies, ensuring customer success and the advancement of Synopsys’ cutting-edge tools.</p>\n<p>Above all, you are motivated by the impact of your work on the semiconductor industry and the broader technology landscape. You are ready to be a technical leader and trusted advisor, shaping the future of physical design and pushing the boundaries of what’s possible.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.</li>\n</ul>\n<ul>\n<li>Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.</li>\n</ul>\n<ul>\n<li>Collaborating closely with Synopsys R&amp;D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.</li>\n</ul>\n<ul>\n<li>Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place &amp; route, timing closure, and power optimization.</li>\n</ul>\n<ul>\n<li>Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.</li>\n</ul>\n<ul>\n<li>Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&amp;D teams.</li>\n</ul>\n<ul>\n<li>Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.</li>\n</ul>\n<ul>\n<li>Position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.</li>\n</ul>\n<ul>\n<li>Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.</li>\n</ul>\n<ul>\n<li>Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.</li>\n</ul>\n<ul>\n<li>15+ plus years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.</li>\n</ul>\n<ul>\n<li>Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.</li>\n</ul>\n<ul>\n<li>In-depth understanding of synthesis, design planning, place &amp; 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Sr Director of ASIC Physical Design, you will own and drive the end-to-end physical design flow for high-speed die-to-die interconnect and interface chips targeting 2 GHz+ on advanced process nodes (sub-7nm/5nm/3nm).</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification with emphasis on die-to-die interface placement and bump/pad ring constraints.</li>\n</ul>\n<ul>\n<li>Achieving timing closure across all corners and modes, with expertise in multi-corner multi-mode sign-off for high-speed serial and parallel interfaces.</li>\n</ul>\n<ul>\n<li>Driving power integrity, signal integrity, and thermal analysis to meet stringent tape-out criteria for high-bandwidth die-to-die links.</li>\n</ul>\n<ul>\n<li>Defining and owning physical design methodology, Synopsys tool flows, and best practices across the organization.</li>\n</ul>\n<ul>\n<li>Building, mentoring, and leading a globally distributed team, establishing effective communication and collaboration norms to foster cohesion and engineering excellence.</li>\n</ul>\n<ul>\n<li>Collaborating cross-functionally with RTL design, DV, architecture, CAD/EDA, and program management teams globally.</li>\n</ul>\n<ul>\n<li>Owning physical design schedules and milestones for multiple concurrent projects, communicating status to senior leadership and mitigating risks proactively.</li>\n</ul>\n<ul>\n<li>Championing automation and scripting to improve PPA outcomes and team productivity.</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Enable the physical implementation of high-speed die-to-die interconnects that power large-scale AI accelerators, GPU clusters, and multi-die systems.</li>\n</ul>\n<ul>\n<li>Deliver ultra-low latency, high-bandwidth chip-to-chip communication at the core of next-generation AI infrastructure.</li>\n</ul>\n<ul>\n<li>Advance the adoption of cutting-edge process nodes and interface standards, positioning Synopsys as a leader in silicon innovation.</li>\n</ul>\n<ul>\n<li>Ensure robust engineering quality, execution velocity, and successful tape-outs across global teams.</li>\n</ul>\n<ul>\n<li>Drive organizational excellence by fostering a culture of accountability, growth, and technical mastery.</li>\n</ul>\n<ul>\n<li>Shape methodologies and tool flows that set industry benchmarks for high-speed, advanced-node physical design.</li>\n</ul>\n<ul>\n<li>Contribute to the strategic direction of AI silicon and interconnect products, impacting the broader technology ecosystem.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>15+ years of hands-on physical design experience, with deep expertise in high-frequency (≥2 GHz) chip design.</li>\n</ul>\n<ul>\n<li>Expertise with Synopsys IC Compiler II (ICC2), PrimeTime, Fusion Compiler, StarRC, IC Validator, and PrimePower.</li>\n</ul>\n<ul>\n<li>Track record of taping out high-speed interface ICs, die-to-die interconnect chips, SerDes, or similar designs at advanced process nodes (7nm, 5nm, 3nm).</li>\n</ul>\n<ul>\n<li>Understanding of die-to-die interface standards and protocols (UCIe, BoW, HBI, XSR, or proprietary) and their physical implementation.</li>\n</ul>\n<ul>\n<li>Experience with power intent flows (UPF/CPF), low-power design techniques, and dynamic/static power optimization.</li>\n</ul>\n<ul>\n<li>Strong scripting skills (Tcl, Python, Perl) for tool flow automation and PPA optimization.</li>\n</ul>\n<ul>\n<li>Proven ability to lead and grow globally distributed engineering teams of 10+ people.</li>\n</ul>\n<ul>\n<li>Cross-cultural communication and collaboration skills; experience working across US, Asia, or European engineering centers.</li>\n</ul>\n<ul>\n<li>BS or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).</li>\n</ul>\n<p>As a Sr Director of ASIC Physical Design, you will join a globally distributed Silicon Engineering team focused on the physical implementation of cutting-edge AI silicon and high-speed die-to-die interconnects.</p>\n<p>Our team spans multiple sites and time zones, collaborating with process technology, packaging, RTL, DV, architecture, CAD/EDA, and program management teams.</p>\n<p>We pride ourselves on a culture of technical depth, low bureaucracy, and a relentless drive for engineering excellence.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c7ea2375-1cc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-director-in-hcmc-da-nang/44408/93750516784","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Physical Design","High-Frequency Chip Design","Synopsys IC Compiler II","PrimeTime","Fusion Compiler","StarRC","IC Validator","PrimePower","Die-to-Die Interface Standards","Power Intent Flows","Low-Power Design Techniques","Dynamic/Static Power Optimization","Scripting Skills (Tcl, Python, Perl)","Leadership and Team Management"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:13:37.968Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Physical Design, High-Frequency Chip Design, Synopsys IC Compiler II, PrimeTime, Fusion Compiler, StarRC, IC Validator, PrimePower, Die-to-Die Interface Standards, Power Intent Flows, Low-Power Design Techniques, Dynamic/Static Power Optimization, Scripting Skills (Tcl, Python, Perl), Leadership and Team Management"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_642c88a4-a92"},"title":"ASIC Physical Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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Your expertise in the physical design flow and familiarity with industry-leading tools will enable you to drive technical execution and lead complex projects.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks,logic, memory, interfaces, analog, security, and embedded processors,into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_642c88a4-a92","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-sr-staff-engineer-16724/44408/93743819072","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Design Compiler","PrimeTime","IC Compiler II/FC","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:52.721Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Design Compiler, PrimeTime, IC Compiler II/FC, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7375c418-b8a"},"title":"SOC Engineering, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7375c418-b8a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-staff-engineer/44408/94212497968","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$120,000 - $180,000 per year","x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimization","static timing analysis (STA)","physical verification","EMIR analysis","timing closure","floor-planning","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime","Python","PERL","TCL","high-frequency design","low-power design methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:44.698Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimization, static timing analysis (STA), physical verification, EMIR analysis, timing closure, floor-planning, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, Python, PERL, TCL, high-frequency design, low-power design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":120000,"maxValue":180000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4f7dae70-9ee"},"title":"R&D Engineer, Staff (PD, PnR, CTS)","description":"<p>Join Synopsys as a Staff R&amp;D Engineer in Physical Design (PD), Place and Route (PnR), and Chip Technology Software (CTS). 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The team is dedicated to developing advanced SLM IPs and subsystems, leveraging expertise in backend and physical design to deliver robust, high-performance solutions.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3511e871-def"},"title":"Application Engineering, Staff Engineer","description":"<p>We&#39;re seeking an expert in static timing analysis to join our applications engineering team. As a Staff Engineer, you will be responsible for supporting the industry-leading Synopsys PrimeTime Static Timing Analysis tool across pre-sale and post-sale engagements.</p>\n<p>Your key responsibilities will include driving product adoption through competitive benchmarking, customer evaluations, and articulating product advantages to design teams and management. You will also deliver customer training, technical presentations, and hands-on workshops to maximize user proficiency and satisfaction.</p>\n<p>In addition, you will provide tape-out support, troubleshoot complex timing issues, and ensure successful project completion. You will collaborate with R&amp;D, marketing, and sales to relay customer feedback and influence product enhancements.</p>\n<p>To succeed in this role, you will need expertise in Synopsys PrimeTime STA tool, with hands-on experience and deep knowledge of its features. You will also require strong understanding of timing corners, process variations, and signal integrity-related issues.</p>\n<p>If you are a collaborative team player who values diverse perspectives and fosters inclusive environments, we encourage you to apply.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3511e871-def","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/application-engineering-staff-engineer/44408/92918452480","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Synopsys PrimeTime STA tool","Timing corners","Process variations","Signal integrity-related issues","TCL scripting","Physical design","Extraction","ECO methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:10.521Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Synopsys PrimeTime STA tool, Timing corners, Process variations, Signal integrity-related issues, TCL scripting, Physical design, Extraction, ECO methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5be91f86-bf9"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</p>\n<p>You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</p>\n<p>You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.</p>\n<p>You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.</p>\n<p>You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.</p>\n<p>You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.</p>\n<p>You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.</p>\n<p>You will mentor junior engineers and contribute to team knowledge sharing initiatives.</p>\n<p><strong>Impact</strong></p>\n<p>You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.</p>\n<p>You will advance Synopsys&#39; leadership in IP implementation at cutting-edge technology nodes.</p>\n<p>You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.</p>\n<p>You will facilitate seamless cross-site collaboration, ensuring global project success.</p>\n<p>You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.</p>\n<p>You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electronics, Electrical Engineering, or related field.</p>\n<p>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</p>\n<p>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</p>\n<p>Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.</p>\n<p>Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.</p>\n<p>Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.</p>\n<p>Strong analytical and debugging skills for addressing complex design challenges.</p>\n<p><strong>Team</strong></p>\n<p>You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.</p>\n<p>The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.</p>\n<p>Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5be91f86-bf9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IP implementation","Timing closure","Clock tree synthesis","Skew balancing","Mixed-signal IP integration","Scripting languages (Tcl, Perl, Python)","Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:24.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IP implementation, Timing closure, Clock tree synthesis, Skew balancing, Mixed-signal IP integration, Scripting languages (Tcl, Perl, Python), Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_40a899dc-af8"},"title":"Senior/Staff ASIC Design Verification Engineer","description":"<p>Our organisation is seeking a skilled Senior/Staff ASIC Design Verification Engineer to join our team in Ho Chi Minh City, Vietnam. As a key member of our engineering team, you will be responsible for designing and developing cutting-edge semiconductor solutions. Your expertise in ASIC RTL design flow, RTL and GLS verification, and high-speed interface protocols will be essential in advancing our technology and enabling innovations in various industries.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.</li>\n<li>Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.</li>\n<li>Define, develop, and execute functional verification plans and test strategies.</li>\n<li>Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.</li>\n<li>Generate VCD files and perform power analysis/reporting using PrimeTime PX.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum of 2 years of experience in ASIC RTL design flow.</li>\n<li>Proficiency in RTL and GLS verification, with strong debugging capabilities.</li>\n<li>Excellent teamwork and communication skills, with professional proficiency in English.</li>\n<li>Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_40a899dc-af8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/senior-staff-asic-design-verification-engineer/44408/92568976592","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC RTL design flow","RTL and GLS verification","High-speed interface protocols","UVM-based methodologies","PrimeTime PX"],"x-skills-preferred":["High-speed interface protocols"],"datePosted":"2026-03-10T12:09:27.363Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design flow, RTL and GLS verification, High-speed interface protocols, UVM-based methodologies, PrimeTime PX, High-speed interface protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_04934540-478"},"title":"Physical Design Specialist (PDS)","description":"<p>We are looking for a Physical Design Specialist (PDS) to join our team. In this role, you will be responsible for supporting the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</li>\n<li>In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_04934540-478","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-principal-engineer/44408/90265976416","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Design Implementation experience","RTL to GDSII full flow experience","Strong interest and understanding of Advanced Node & Design methodologies","In-depth Synopsys Back end tool experience","Knowledge of several Clock Tree Synthesis methodologies","Excellent verbal and written presentation/communication skills","Customer sensitivity"],"x-skills-preferred":["BSEE or equivalent","Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)","Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus)","Tool knowledge (preferred): STA (Primetime, Tempus)"],"datePosted":"2026-03-06T07:29:04.274Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Design Implementation experience, RTL to GDSII full flow experience, Strong interest and understanding of Advanced Node & Design methodologies, In-depth Synopsys Back end tool experience, Knowledge of several Clock Tree Synthesis methodologies, Excellent verbal and written presentation/communication skills, Customer sensitivity, BSEE or equivalent, Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus), Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus), Tool knowledge (preferred): STA (Primetime, Tempus)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d6bfdcde-f3e"},"title":"Application Engineering, Sr Staff Engineer","description":"<p>We are seeking a technically adept engineer with a deep understanding of static timing analysis and a passion for helping others succeed. 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