Key Responsibilities:

• Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.
• Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.
• Define, develop, and execute functional verification plans and test strategies.
• Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.
• Generate VCD files and perform power analysis/reporting using PrimeTime PX.

Requirements:

• Minimum of 2 years of experience in ASIC RTL design flow.
• Proficiency in RTL and GLS verification, with strong debugging capabilities.
• Excellent teamwork and communication skills, with professional proficiency in English.
• Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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