Network Engineer - ML Infrastructure (High-Speed Interconnects) · xAI

Sat, 18 Apr 2026 15:46:04 GMT
Engineering

xAI · Palo Alto, CA · $180,000 - $440,000 USD · onsite

We are seeking exceptional ML Infrastructure Engineers with deep expertise in high-speed interconnect technologies to design, build, and optimise the network fabric that powers large-scale AI training and inference clusters.

This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms. You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centres, including our primary front and backend networks that train Grok and that customers use for inference.

Responsibilities:

Design, validate, and productise high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).

Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterisation.

Investigate the opportunity for LPO and LRO in our network.

Evaluate early co-packaged and near-packaged engines for switches and GPUs.

Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.

Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.

Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.

Perform system-level simulation of end-to-end fabric performance.

Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.

Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.

Basic Qualifications:

At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacentre environment.

Master's or PhD degree in Electrical Engineering, Photonics or Physics.

Deep knowledge of PAM4 SerDes performance, equalisation, jitter, crosstalk.

Solid operational understanding of FEC, Retimers, TIAs and Drivers.

Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.

Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterisation.

Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.

Knowledge of SiPh design process, yield improvement and reliability testing.

Familiarity with CPO technologies and challenges/risk areas.

Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.

Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.

Compensation and Benefits:

$180,000 - $440,000 USD

Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.