{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/power"},"x-facet":{"type":"skill","slug":"power","display":"Power","count":8},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ccd31d35-3ef"},"title":"Analog Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a skilled and motivated analog design engineer, passionate about developing advanced integrated circuits for high-speed communication systems. With a good understanding of CMOS technologies and track record in designing medium complexity analog circuits, you thrive in fast-paced, collaborative environments. You have expertise in some analog functions such as ADCs, DACs, PLLs, and transceiver blocks, and you are adept at delivering robust designs that meet stringent electrical specifications and reliability constraints. Analytical and detail-oriented, you know how to evaluate the impact of layout parasitics and optimizing for performance, power, and area.</p>\n<p>You are comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills enable you to interact effectively within a global and multi-cultural team, and your organizational abilities ensure timely delivery of milestones. You are proactive in problem-solving and continuous improvement, and you value mentorship, sometimes guiding junior engineers. Whether you have industry experience or specialized academic training, you are eager to contribute to cutting-edge projects that power innovations in mobile, automotive, cloud, HPC, AI, IoT, 5G, and storage. Inclusivity, diversity, and collaboration are important to you, and you are ready to make a significant impact at Synopsys.</p>\n<p>Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. Define and plan analog design activities, setting clear milestones and deliverables for project success. Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed. Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area. Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements. Engage with a global, multi-cultural, and cross-functional R&amp;D team, contributing to a collaborative and innovative work environment.</p>\n<p>Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices. Enhance Synopsys&#39; reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs. Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace. Foster innovation and continuous improvement within the analog and mixed-signal R&amp;D team, setting benchmarks for technical excellence.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ccd31d35-3ef","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/analog-design-staff-engineer/44408/93724982160?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS technologies","analog circuit design","ADCs","DACs","PLLs","transceiver blocks","layout parasitics","performance","power","area","SerDes products","Ethernet","PCIe standards","silicon correlation","simulation results","discrepancies","design refinements"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:58.214Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS technologies, analog circuit design, ADCs, DACs, PLLs, transceiver blocks, layout parasitics, performance, power, area, SerDes products, Ethernet, PCIe standards, silicon correlation, simulation results, discrepancies, design refinements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e179812d-e4c"},"title":"Technical Program Manager, Compute Infrastructure","description":"<p>We&#39;re seeking a Technical Program Manager for Compute Infrastructure to join our engineer-first TPM team. As a Technical Program Manager, you will own the end-to-end delivery of large-scale GPU clusters, partnering with engineers to bring clusters online across external providers and partners. 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If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p><strong>About the Team</strong></p>\n<p>The Stargate team is responsible for building the physical infrastructure that powers large-scale AI systems. We design and deliver next-generation data centers optimized for dense compute clusters, advanced networking, and rapidly evolving hardware platforms.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a CPU &amp; Storage Technical Lead to define and drive the server compute and storage architecture strategy for Stargate infrastructure.</p>\n<p>In this role, you will own technical direction across CPU platforms, memory configurations, local and disaggregated storage systems, and their integration into large-scale AI clusters. You will evaluate vendor roadmaps, lead platform tradeoff decisions, and ensure compute and storage systems are optimized for training, inference, and supporting services.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ul>\n<li>Own CPU and storage technical strategy for Stargate compute infrastructure across current and future generations.</li>\n</ul>\n<ul>\n<li>Evaluate CPU platforms across performance, efficiency, memory bandwidth, PCIe topology, cost, and roadmap alignment.</li>\n</ul>\n<ul>\n<li>Define storage architectures for AI environments, including boot media, local NVMe, shared storage, caching tiers, metadata services, and high-performance data pipelines.</li>\n</ul>\n<ul>\n<li>Drive server platform decisions involving CPU, memory, NIC, GPU, and storage subsystem integration.</li>\n</ul>\n<ul>\n<li>Partner with performance modeling teams to quantify tradeoffs across compute, memory, I/O, and storage bottlenecks.</li>\n</ul>\n<ul>\n<li>Work with silicon and hardware vendors on roadmap influence, feature requests, qualification plans, and technical escalations.</li>\n</ul>\n<ul>\n<li>Lead bring-up and validation efforts for new CPU and storage platforms in lab and production environments.</li>\n</ul>\n<ul>\n<li>Partner with networking and cluster architecture teams to optimize end-to-end node design and data movement.</li>\n</ul>\n<ul>\n<li>Support supply chain and sourcing teams with technical vendor assessments and second-source strategies.</li>\n</ul>\n<ul>\n<li>Drive reliability, serviceability, and fleet lifecycle planning for compute and storage platforms.</li>\n</ul>\n<ul>\n<li>Translate future AI workload requirements into infrastructure platform specifications.</li>\n</ul>\n<ul>\n<li>Provide technical leadership across cross-functional stakeholders and executive reviews.</li>\n</ul>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related technical field; advanced degree preferred.</li>\n</ul>\n<ul>\n<li>10+ years of experience in server hardware, systems architecture, data center infrastructure, or hyperscale compute platforms.</li>\n</ul>\n<ul>\n<li>Deep expertise in modern CPU architectures (x86, ARM, accelerator host systems) and server platform design.</li>\n</ul>\n<ul>\n<li>Strong understanding of memory systems, PCIe/CXL fabrics, NUMA behavior, and platform-level performance constraints.</li>\n</ul>\n<ul>\n<li>Experience with storage systems including NVMe, SSD qualification, RAID, distributed storage, object/file systems, or high-performance data pipelines.</li>\n</ul>\n<ul>\n<li>Experience evaluating hardware tradeoffs across performance, cost, power, thermals, and supply availability.</li>\n</ul>\n<ul>\n<li>Familiarity with GPU clusters and AI training/inference infrastructure strongly preferred.</li>\n</ul>\n<ul>\n<li>Experience working directly with OEMs, ODMs, silicon vendors, or storage vendors.</li>\n</ul>\n<ul>\n<li>Strong systems thinking with ability to connect component decisions to fleet-level outcomes.</li>\n</ul>\n<ul>\n<li>Excellent communication skills with the ability to influence engineering and executive stakeholders.</li>\n</ul>\n<ul>\n<li>Proven ability to operate in fast-moving, ambiguous environments with high ownership.</li>\n</ul>\n<p><strong>Preferred Skills</strong></p>\n<ul>\n<li>Experience designing infrastructure for large-scale AI or HPC environments.</li>\n</ul>\n<ul>\n<li>Familiarity with CPU vendor roadmaps across AMD, Intel, and ARM ecosystems.</li>\n</ul>\n<ul>\n<li>Experience with distributed storage architectures supporting GPU clusters.</li>\n</ul>\n<ul>\n<li>Knowledge of fleet operations, hardware lifecycle management, and production deployments at scale.</li>\n</ul>\n<ul>\n<li>Prior experience in hyperscale cloud, AI infrastructure, or advanced compute environments.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p>We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.</p>\n<p>For additional information, please see [OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement](https://cdn.openai.com/policies/eeo-policy-statement.pdf).</p>\n<p>Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_736969e6-3f9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://openai.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/18a60850-cf8b-4374-a214-ef78b9712deb?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"Full time","x-salary-range":"$342K – $555K","x-skills-required":["server hardware","systems architecture","data center infrastructure","hyperscale compute platforms","modern CPU architectures","server platform design","memory systems","PCIe/CXL fabrics","NUMA behavior","platform-level performance constraints","storage systems","NVMe","SSD qualification","RAID","distributed storage","object/file systems","high-performance data pipelines","hardware tradeoffs","performance","cost","power","thermals","supply availability","GPU clusters","AI training/inference infrastructure","OEMs","ODMs","silicon vendors","storage vendors","strong systems thinking","component decisions","fleet-level outcomes","excellent communication skills","influence engineering and executive stakeholders","fast-moving","ambiguous environments","high ownership"],"x-skills-preferred":["infrastructure for large-scale AI or HPC environments","CPU vendor roadmaps across AMD, Intel, and ARM ecosystems","distributed storage architectures supporting GPU clusters","fleet operations","hardware lifecycle management","production deployments at scale","hyperscale cloud","AI infrastructure","advanced compute environments"],"datePosted":"2026-04-24T12:21:17.145Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco; Seattle"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"server hardware, systems architecture, data center infrastructure, hyperscale compute platforms, modern CPU architectures, server platform design, memory systems, PCIe/CXL fabrics, NUMA behavior, platform-level performance constraints, storage systems, NVMe, SSD qualification, RAID, distributed storage, object/file systems, high-performance data pipelines, hardware tradeoffs, performance, cost, power, thermals, supply availability, GPU clusters, AI training/inference infrastructure, OEMs, ODMs, silicon vendors, storage vendors, strong systems thinking, component decisions, fleet-level outcomes, excellent communication skills, influence engineering and executive stakeholders, fast-moving, ambiguous environments, high ownership, infrastructure for large-scale AI or HPC environments, CPU vendor roadmaps across AMD, Intel, and ARM ecosystems, distributed storage architectures supporting GPU clusters, fleet operations, hardware lifecycle management, production deployments at scale, hyperscale cloud, AI infrastructure, advanced compute environments","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":342000,"maxValue":555000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6f0891f0-3ed"},"title":"Electrical Harness Design Engineer","description":"<p>We are seeking an experienced Electrical Harness Design Engineer to join our team. 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You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centres, including our primary front and backend networks that train Grok and that customers use for inference.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Design, validate, and productise high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).</li>\n<li>Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up &amp; characterisation.</li>\n<li>Investigate the opportunity for LPO and LRO in our network.</li>\n<li>Evaluate early co-packaged and near-packaged engines for switches and GPUs.</li>\n<li>Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.</li>\n<li>Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.</li>\n<li>Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.</li>\n<li>Perform system-level simulation of end-to-end fabric performance.</li>\n<li>Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.</li>\n<li>Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.</li>\n</ul>\n<p>Basic Qualifications:</p>\n<ul>\n<li>At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacentre environment.</li>\n<li>Master&#39;s or PhD degree in Electrical Engineering, Photonics or Physics.</li>\n<li>Deep knowledge of PAM4 SerDes performance, equalisation, jitter, crosstalk.</li>\n<li>Solid operational understanding of FEC, Retimers, TIAs and Drivers.</li>\n<li>Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.</li>\n<li>Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterisation.</li>\n<li>Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.</li>\n<li>Knowledge of SiPh design process, yield improvement and reliability testing.</li>\n<li>Familiarity with CPO technologies and challenges/risk areas.</li>\n<li>Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.</li>\n<li>Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.</li>\n</ul>\n<p>Compensation and Benefits:</p>\n<p>$180,000 - $440,000 USD</p>\n<p>Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short &amp; 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We lead strategy, supplier engagements, commercial architecture, execution, and long-term enablement across advanced systems including custom silicon, accelerators, CPU platforms, networking, memory, power delivery, cooling, and full rack solutions.</p>\n<p>We are a small, high-impact team working across engineering, operations, finance, legal, and executive leadership to scale OpenAI’s fleet worldwide.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a Sr. Strategic Sourcing Manager to own and lead sourcing strategy and global supplier partnerships for the High Speed Interconnects (e.g., power systems, high-speed interconnect, memory subsystems, networking modules, mechanical enclosures, thermal systems, etc.). You will be the single-threaded leader across supplier strategy, selection, negotiations, and commercial/operational execution.</p>\n<p>You will be accountable for enabling massive growth, reducing long-term cost curves, securing supply resilience, and aligning supplier technology roadmaps with OpenAI’s future system architecture needs.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ol>\n<li>Own the category end-to-end: strategy, business case, supplier selection, executive alignment, and operational enablement</li>\n</ol>\n<ol>\n<li>Lead complex commercial negotiations including MSAs, NRE, cost models, open-book pricing, ramp/capacity commitments, and risk-buy frameworks</li>\n</ol>\n<ol>\n<li>Build and scale a reliable global supply base with redundancy and geopolitical compliance, including mapping and influencing sub-tier suppliers to ensure resilience across the extended supply chain.</li>\n</ol>\n<ol>\n<li>Translate engineering requirements into actionable sourcing plans with tier-1 manufacturing partners</li>\n</ol>\n<ol>\n<li>Drive cost benchmarking and teardown insights to shape long-term cost-down strategies</li>\n</ol>\n<ol>\n<li>Maintain tight alignment with Operations, Capacity Planning, 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We lead strategy, supplier engagements, commercial architecture, execution, and long-term enablement across advanced systems including custom silicon, accelerators, CPU platforms, networking, memory, power delivery, cooling, and full rack solutions.</p>\n<p>We are a small, high-impact team working across engineering, operations, finance, legal, and executive leadership to scale OpenAI’s fleet worldwide.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a Sr. Strategic Sourcing Manager to own and lead sourcing strategy and global supplier partnerships for the Memory Storage &amp; CPUs category (e.g., power systems, high-speed interconnect, memory subsystems, networking modules, mechanical enclosures, thermal systems, etc.). You will be the single-threaded leader across supplier strategy, selection, negotiations, and commercial/operational execution.</p>\n<p>You will be accountable for enabling massive growth, reducing long-term cost curves, securing supply resilience, and aligning supplier technology roadmaps with OpenAI’s future system architecture needs.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ol>\n<li>Own the category end-to-end: strategy, business case, supplier selection, executive alignment, and operational enablement</li>\n</ol>\n<ol>\n<li>Lead complex commercial negotiations including MSAs, NRE, cost models, open-book pricing, ramp/capacity commitments, and risk-buy frameworks</li>\n</ol>\n<ol>\n<li>Build and scale a reliable global supply base with redundancy and geopolitical compliance, including mapping and influencing sub-tier suppliers to ensure resilience across the extended supply chain.</li>\n</ol>\n<ol>\n<li>Translate engineering requirements into actionable sourcing plans with tier-1 manufacturing partners</li>\n</ol>\n<ol>\n<li>Drive cost benchmarking and teardown insights to shape long-term cost-down strategies</li>\n</ol>\n<ol>\n<li>Maintain tight alignment with Operations, Capacity Planning, Finance, and Program Management to ensure supply readiness against growth milestones</li>\n</ol>\n<ol>\n<li>Build executive-level relationships with suppliers to ensure priority allocation and roadmap synchronization</li>\n</ol>\n<ol>\n<li>Define scalable sourcing processes and dashboards for risk, cost, and performance transparency</li>\n</ol>\n<ol>\n<li>Mentor and uplift sourcing peers by role-modeling strong cross-functional leadership and commercial excellence</li>\n</ol>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>8+ years of strategic sourcing or supplier management experience in advanced electronics, cloud infrastructure, telecom, or semiconductor supply chains</li>\n</ul>\n<ul>\n<li>Demonstrated success owning a category and supplier portfolio at scale (supply assurance, commercial strategy, cost roadmap), including leading complex negotiations</li>\n</ul>\n<ul>\n<li>Strong understanding of electronic and module-level cost drivers (e.g., power, PCBAs, connectors, cooling, memory, networking)</li>\n</ul>\n<ul>\n<li>Proven ability to influence and partner with Engineering, Program Management, Legal, and Finance at senior levels</li>\n</ul>\n<ul>\n<li>Executive presence and ability to communicate clearly in high-stakes supplier and leadership forums</li>\n</ul>\n<ul>\n<li>Comfort with fast-paced ambiguity and decisive decision-making in compressed timelines</li>\n</ul>\n<p><strong>Preferred Qualifications</strong></p>\n<ul>\n<li>Experience in hyperscale datacenter supply chain environments</li>\n</ul>\n<ul>\n<li>Familiarity with export controls and high-risk country strategies</li>\n</ul>\n<ul>\n<li>Technical background in \\[mechanical/electrical engineering, high-speed IO, thermal systems, or rack-scale architecture\\]</li>\n</ul>\n<ul>\n<li>Experience building sourcing playbooks, processes, and scalable operational mechanisms</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0d0b005c-107","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/23014bc8-37d4-4fd9-9a77-d95fdd33437f?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$226K – $378K","x-skills-required":["strategic sourcing","supplier management","advanced electronics","cloud infrastructure","telecom","semiconductor supply chains","electronic and module-level cost drivers","power","PCBAs","connectors","cooling","memory","networking"],"x-skills-preferred":["hyperscale datacenter supply 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architecture","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":226000,"maxValue":378000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_41ccc086-acb"},"title":"Camera ISP Software Engineer, Consumer Devices","description":"<p><strong>Job Posting</strong></p>\n<p><strong>Camera ISP Software Engineer, Consumer Devices</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Consumer Products</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$293K – $325K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>The Consumer Products team at OpenAI builds and ships end-to-end hardware and software experiences that bring frontier AI into the physical world. We work across industrial design, hardware engineering, embedded systems, and AI research to create category-defining consumer devices that feel intuitive, reliable, and deeply integrated with OpenAI’s models.</p>\n<p>Within this organisation, the Camera team is responsible for delivering robust, production-ready imaging systems that operate under real-world constraints such as motion, power, latency, and manufacturing variation. Our work spans early silicon and board bring-up through mass production, and directly supports both user-facing experiences and on-device perception for AI-driven features.</p>\n<p>We operate as a small, highly technical team with deep ownership, close cross-functional collaboration, and a strong bias toward shipping high-quality products rather than incremental demos.</p>\n<p><strong>About the Role</strong></p>\n<p>As a Camera ISP Software Engineer, you will own end-to-end ISP bring-up and tuning across prototype and production hardware. You’ll work across software tuning and hardware-accelerated pipelines to deliver stable, high-quality imaging under real-world constraints such as motion, power, and manufacturing variation.</p>\n<p>This role is ideal for engineers who thrive in ambiguous early-stage environments, enjoy deep technical ownership, and take pride in shipping production-grade imaging systems.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of four days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Own end-to-end ISP tuning and bring-up, from early prototypes through production hardware.</li>\n</ul>\n<ul>\n<li>Tune core 3A and image-quality blocks including AE, AWB, AF, noise reduction (spatial and temporal), sharpening, tone mapping, color correction, HDR/WDR, flicker mitigation, lens shading, defect pixel correction, and related ISP stages.</li>\n</ul>\n<ul>\n<li>Build repeatable capture and evaluation workflows, combining controlled lab sweeps with real-world validation.</li>\n</ul>\n<ul>\n<li>Validate robustness across sensor, module, and manufacturing variation with clear, defensible success criteria.</li>\n</ul>\n<ul>\n<li>Deliver production-grade tuning artifacts, including versioned tuning packs, parameter manifests, change logs, and curated RAW and processed datasets with supporting documentation.</li>\n</ul>\n<ul>\n<li>Partner closely with camera firmware, systems, and hardware teams to debug pipelines, configure sensors, and resolve board-level and silicon-level issues as designs evolve.</li>\n</ul>\n<p><strong>You might thrive in this role if you:</strong></p>\n<ul>\n<li>Deep experience shipping ISP tuning for embedded or mobile camera products, from bring-up through production.</li>\n</ul>\n<ul>\n<li>Strong fundamentals across 3A (AE/AWB/AF), noise modeling, sharpening and detail trade-offs, tone mapping, and color pipelines.</li>\n</ul>\n<ul>\n<li>Proven ability to run data-driven tuning loops, including repeatable capture, rigorous evaluation, and disciplined versioning of tuning artifacts.</li>\n</ul>\n<ul>\n<li>Hands-on experience debugging end-to-end camera pipelines on real hardware, including RAW capture, processed outputs, and hardware-accelerated paths.</li>\n</ul>\n<ul>\n<li>Ability to collaborate cross-functionally and translate system-level constraints (power, latency, motion, reliability) into concrete tuning decisions and validation plans.</li>\n</ul>\n<p><strong>Preferred Qualifications</strong></p>\n<ul>\n<li>Experience with common mobile or embedded SoC camera stacks and vendor frameworks.</li>\n</ul>\n<ul>\n<li>Experience tuning imaging pipelines explicitly for downstream machine-learning consumers, with iteration driven by model feedback.</li>\n</ul>\n<ul>\n<li>Experience designing motion-aware temporal imaging strategies that remain stable under rapid device or scene motion.</li>\n</ul>\n<p><strong>Experience Level</strong></p>\n<p>Mid</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Workplace Type</strong></p>\n<p>Hybrid</p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Industry</strong></p>\n<p>Technology</p>\n<p><strong>Salary Range</strong></p>\n<p>$293K – $325K</p>\n<p><strong>Required Skills</strong></p>\n<ul>\n<li>Camera ISP tuning</li>\n<li>Embedded systems</li>\n<li>AI research</li>\n<li>Industrial design</li>\n<li>Hardware engineering</li>\n<li>Machine learning</li>\n<li>Image processing</li>\n<li>Computer vision</li>\n</ul>\n<p><strong>Preferred Skills</strong></p>\n<ul>\n<li>Mobile or embedded SoC camera stacks</li>\n<li>Vendor frameworks</li>\n<li>Imaging pipelines</li>\n<li>Motion-aware temporal imaging strategies</li>\n<li>Downstream machine-learning consumers</li>\n<li>Model feedback</li>\n<li>System-level constraints</li>\n<li>Power</li>\n<li>Latency</li>\n<li>Motion</li>\n<li>Reliability</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_41ccc086-acb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/10c30695-c831-44e3-b6b9-cb31e2643791?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$293K – $325K","x-skills-required":["Camera ISP tuning","Embedded systems","AI research","Industrial design","Hardware engineering","Machine learning","Image processing","Computer vision"],"x-skills-preferred":["Mobile or embedded SoC camera stacks","Vendor frameworks","Imaging pipelines","Motion-aware temporal imaging strategies","Downstream machine-learning consumers","Model feedback","System-level constraints","Power","Latency","Motion","Reliability"],"datePosted":"2026-03-06T18:25:08.682Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"engineering","industry":"technology","skills":"Camera ISP tuning, Embedded systems, AI research, Industrial design, Hardware engineering, Machine learning, Image processing, Computer vision, Mobile or embedded SoC camera stacks, Vendor frameworks, Imaging pipelines, Motion-aware temporal imaging strategies, Downstream machine-learning consumers, Model feedback, System-level constraints, Power, Latency, Motion, Reliability","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":293000,"maxValue":325000,"unitText":"YEAR"}}}]}