As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.

Key responsibilities include:

• Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products
• Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles
• Mentoring and developing team members, fostering technical growth, and a culture of innovation
• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges

The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.

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Job Description

We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams - architecture, verification, physical implementation, and firmware - to deliver industry-leading SecurityIP solutions.

Responsibilities

• Leading a diverse team of design engineers in the development of next-generation SecurityIP solutions.
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Driving all phases of SecurityIP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth and a culture of innovation.
• Engaging with customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Impact

• Delivering industry-leading SecurityIP solutions that set new benchmarks for speed, bandwidth, and efficiency.
• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
• Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
• Enhancing product quality and reliability through rigorous design and verification processes.
• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, with 12-15 years of complex technical development experience.
• Minimum 2 years’ experience in people management and employee development.
• Proficiency in synthesizable Verilog and SystemVerilog design concepts and implementation.
• Strong background in front-end design flows: linting, synthesis, static timing analysis (STA), cross-domain clocking, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding of SecurityIP architecture is a plus.

Team

You’ll join the Synopsys SecurityIP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic and high-energy work environment to bring industry-defining products to market.

Your responsibilities will include:

• Collaborating with cross-functional teams to craft essential next-generation product features that are important for performance, power optimization, and power management.
• Collaborating to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation.
• Working with various Arch & Design teams to come up with test plans of new features.
• Collaborating with other validation & bring-up teams to bring up/characterize silicon power and power saving features.
• Working with design & estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.
• Developing power consumption models to be used in binning, productization, and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.

We need to see:

• B. Tech or M. Tech in Electronics Engineering stream, with 3+ years related work experience, excellent problem-solving, collaborative, and interpersonal skills.
• Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.
• Hands-on experience with silicon bring up, validation, and productization, good knowledge in board and system design considerations, Power supply design.
• Very good problem-solving and hardware debugging skills, very good data analysis and logical reasoning skills.
• Strong familiarity with HW lab environment and understanding of various lab equipment.
• Experience in working with windows. Linux exposure is highly preferred.
• Working experience with scripting languages like perl and/or python is a plus point.
• Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high-energy environment.
• Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability, and aging mechanisms.
• Background with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $266K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We are seeking a highly skilled cross-stack power architect with deep expertise in making ML systems energy efficient. This hands-on individual contributor will sit within our silicon implementation team and work closely with architecture, kernels, chip design, silicon implementation, platform design, and the broader industry ecosystem to architect, implement, and deploy performance-per-watt optimized next-generation AI accelerator chips and systems.

In this role, you will:

• Oversee power architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to maximize performance under power envelope

• Build chip and system-level power models grounded in empirical data and experience to guide organization-wide energy efficiency strategy. This requires a detailed understanding of ML workloads, ML chip and system architecture, silicon design, implementation, and characterization

• Collaborate with chip and platform architecture/design teams to explore and implement power management features, including the specification and implementation of digital/mixed-signal IP, sensing and telemetry, firmware/system software, and silicon characterization methodology (in partnership with engineering teams)

• Partner with silicon design and implementation teams, to optimize performance under power envelope. This includes (but is not limited to) clocking and power domain architecture, voltage/frequency selection, microarchitecture and physical-design driven power reduction, post-silicon voltage margin optimization and workload-informed power optimization

• Work with ecosystem partners (EDA, ASIC, IP, component vendors) to drive innovations that can improve energy efficiency

Qualifications:

• Relevant degree and strong industry experience focused on the end-to-end energy-efficient ML silicon codesign

• Hands-on experience with power architecture, power estimation, power management and power optimization is required.

• Fundamental understanding of ML chip and platform architecture, performance modeling and workload power/performance characteristics is strongly preferred.

• Hands-on experience with power bring-up and power validation is strongly preferred.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.

• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.

• Drive flow development and optimization to improve design quality and predictability.

• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).

• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.

• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.

• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.

What you need

• Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why this matters

Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.

Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.

Enhance the predictability and simplicity of implementation processes for complex interface IPs.

Accelerate the adoption of next-generation design technologies and tools across the industry.

Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.

Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.

What you’ll need

• Minimum 7years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why you’ll love this role

• Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.

• Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.

• Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.

• Participate in professional development opportunities to enhance your skills and expertise.

• Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

• In addition to company holidays, we have ETO and FTO Programs.

• Family Support

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

• Save for your future with our retirement plans that vary by region and country.

• Compensation

• Competitive salaries.

• Awards

• We're proud to receive several recognitions.

• Explore the Possibilities with Synopsys

• Search Synopsys Careers

• Join our Talent Community

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.

What you need

• MSEE (preferred) or equivalent with a minimum of 5 years' experience in digital design and verification.
• Proven proficiency in Verilog or VHDL for ASIC development.
• Experience with code quality metrics and coverage-driven verification methodologies.
• In-depth knowledge of high-speed digital and mixed-signal design, asynchronous clock crossings, and DFT methodologies.
• Strong understanding of CDC, synthesis, and power optimization techniques.
• Hands-on experience with simulation tools and collaborative debugging in verification environments.
• Ability to develop system-level specifications for complex digital and analog systems.

What you'll be doing:

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.
• Driving the creation, execution, and tracking of comprehensive test plans, including functional, assertion, and code coverage metrics.
• Overseeing design flows for clock domain crossing (CDC), synthesis, design-for-test (DFT), and low-power methodologies.
• Collaborating closely with verification teams to debug issues, analyze failure cases, and run gate-level simulations.
• Coordinating with cross-functional teams and providing technical leadership throughout the product lifecycle, from specification development to performance testing of test chips.
• Mentoring and developing junior engineers, fostering a culture of continuous learning and innovation.

The Impact You Will Have:

• Accelerate the delivery of industry-leading mixed-signal ASIC solutions, enabling next-generation connectivity standards.
• Enhance the quality and reliability of high-speed SERDES products through rigorous design and verification practices.
• Drive process improvements that elevate team productivity and product performance.
• Champion best practices in digital and mixed-signal design, setting new benchmarks for quality and efficiency.
• Foster a collaborative and innovative team environment, empowering engineers to reach their full potential.
• Strengthen Synopsys' reputation as a global leader in semiconductor technology through successful project execution and customer satisfaction.

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