As a Power & Resource Efficiency Engineer, you'll sit at the intersection of IT and facilities , building the systems, models, and control loops that optimize how we allocate and consume power, cooling, and physical capacity across our TPU/GPU fleet.

You'll own the technical strategy for turning raw data center capacity into reliable, efficient compute, working across power topology, workload scheduling, and real-time telemetry to push utilization as close to the physical envelope as possible while maintaining our availability commitments.

Responsibilities

• Build models that forecast consumption across electrical and mechanical subsystems, informing capacity planning, energy procurement, oversubscription targets and risks, including statistical modeling of cluster utilization, workload profiles, and failure modes.

• Design IT/OT interfaces that bridge compute orchestration with facility controls, enabling real-time telemetry across accelerator hardware, power distribution, cooling, and schedulers.

• Build and operate load management systems that use power and cooling topology to enable load management and power/thermal-aware placement to maximize throughput while meeting SLOs.

• Partner with data center providers to drive design optimizations and hold them accountable to SLA-grade performance standards, providing technical diligence on partner architectures.

What We're Looking For

• Deep knowledge of data center power distribution and cooling architectures, and how they interact with IT load profiles. Experience with reliability engineering, SLA development, and failure-mode analysis.

• Proficiency in statistical modeling and simulation for infrastructure capacity or power utilization.

• Familiarity with SCADA/BMS/EPMS, telemetry pipelines, and control systems. Experience building software that bridges IT and OT.

• Exposure to accelerator deployments and their power management interfaces strongly preferred.

• Demand response, grid interaction, or behind-the-meter generation experience is a plus.

• Ability to translate between infrastructure engineering, software teams, and external partners.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Power Systems, Controls Engineering, or a related field.

• 5+ years of experience in data center infrastructure or facility engineering.

• Demonstrated experience with data center power distribution and cooling system architectures.

• Experience building or operating software-based power management, load scheduling, or control systems.

• Proficiency in Python or similar languages for statistical modeling, simulation, or automation of data center infrastructure optimizations.

• Familiarity with SCADA, BMS, EPMS, or industrial control systems and associated protocols (Modbus, BACnet, SNMP).

• Track record of cross-functional collaboration across hardware, software, and facilities teams.

Preferred Qualifications

• Master's or PhD in Controls, Power Systems, or related discipline and 3+ years of experience in data center infrastructure or facility engineering.

• Experience with accelerator-class deployments and their power management interfaces.

• Background in control theory, dynamical systems, or cyber-physical systems design.

• Experience with energy storage, microgrid integration, demand response, or behind-the-meter generation.

• Familiarity with reliability engineering methods.

• Experience with SLA development, availability modeling, or service credit frameworks.

• Exposure to ML/optimization techniques applied to infrastructure or energy systems.

Salary

The annual compensation range for this role is $320,000-$405,000 USD.

Benefits

We offer competitive compensation and benefits, optional equity donation matching, generous vacation and parental leave, flexible working hours, and a lovely office space in which to collaborate with our team.

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The ideal candidate will have 5+ years of experience in electrical engineering, focusing on system-level design, development, and testing. They will also have a degree in Electrical Engineering or equivalent and experience with analog and digital electronics design, testing, and troubleshooting. Proficiency in laboratory skills, including setting up and running experiments, is also required.

The Electrical Engineer will participate in system testing at laboratory, ground, and flight test levels, providing detailed data analysis and feedback. They will conduct troubleshooting and testing of electronic components and subsystems to ensure optimal performance. The successful candidate will work closely with technical leads and project teams to support system integration efforts.

The Electrical Engineer will document test results, system designs, and processes to maintain thorough technical records. They will also assist in the design and development of PCB layouts in collaboration with the electrical engineering team.

The salary range for this role is $129,000-$171,000 USD. The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full-time offers; and are considered part of Anduril's total compensation package.

Additionally, Anduril offers top-tier benefits for full-time employees, including healthcare benefits, income protection, generous time off, family planning and parenting support, mental health resources, professional development, commuter benefits, relocation assistance, and a retirement savings plan.

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You'll own the technical strategy for turning raw data center capacity into reliable, efficient compute, working across power topology, workload scheduling, and real-time telemetry to push utilization as close to the physical envelope as possible while maintaining our availability commitments.

Key responsibilities include:

• Building models that forecast consumption across electrical and mechanical subsystems, informing capacity planning, energy procurement, oversubscription targets and risks, including statistical modeling of cluster utilization, workload profiles, and failure modes.

• Designing IT/OT interfaces that bridge compute orchestration with facility controls, enabling real-time telemetry across accelerator hardware, power distribution, cooling, and schedulers.

• Building and operating load management systems that use power and cooling topology to enable load management and power/thermal-aware placement to maximize throughput while meeting SLOs.

• Partnering with data center providers to drive design optimizations and hold them accountable to SLA-grade performance standards, providing technical diligence on partner architectures.

In this role, you'll need to have deep knowledge of data center power distribution and cooling architectures, and how they interact with IT load profiles. Experience with reliability engineering, SLA development, and failure-mode analysis is also essential.

Additionally, proficiency in statistical modeling and simulation for infrastructure capacity or power utilization, familiarity with SCADA/BMS/EPMS, telemetry pipelines, and control systems, and exposure to accelerator deployments and their power management interfaces are highly desirable.

This is a challenging and rewarding role that requires a unique blend of technical expertise, business acumen, and collaboration skills. If you're passionate about data center infrastructure, AI, and sustainability, we encourage you to apply.

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We are seeking an accomplished architect with expertise in high-speed analog and mixed-signal IC design. You will thrive on solving complex challenges and leading teams to deliver innovative transceiver solutions for silicon photonics.

Key responsibilities include:

Architecting 224G & 448G analog transceiver solutions for silicon photonics. Collaborating across engineering teams to drive integration and innovation. Mentoring engineers and supporting technical growth. Representing Synopsys in industry forums. Shaping technical roadmaps for emerging markets. Ensuring designs meet stringent performance and reliability standards.

As an Analog Design Architect, you will advance Synopsys' leadership in silicon photonics and high-speed analog design. You will enable next-generation data center and cloud connectivity, drive technical excellence and innovation, promote collaboration and knowledge sharing, influence industry standards, and open new business opportunities.

Requirements include:

Deep experience in high-speed analog/mixed-signal IC and transceiver design. Expertise in 224G & 448G architectures and silicon photonics integration. Proficiency with EDA tools and IC layout. Strong grasp of signal integrity and power management. Ability to translate technical needs into scalable solutions.

Ideal candidates are innovative and collaborative leaders with a clear communication style, detail-oriented and adaptable, and passionate about advancing technology.

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As a Failure Analysis Engineer, you will be responsible for diagnosing and analyzing functional failures in highly complex electronic assemblies throughout the product lifecycle. You will provide expert technical support to Contract Manufacturers during production and test phases, ensuring rapid resolution of manufacturing-related failures.

Key responsibilities:

• Diagnose and analyze functional failures in highly complex electronic assemblies
• Provide expert technical support to Contract Manufacturers during production and test phases
• Collaborate closely with R&D teams to root-cause prototype and pre-production issues
• Perform hands-on failure analysis, including hardware manipulation, measurement, mounting/demounting, and rework of assemblies
• Utilize laboratory equipment (oscilloscopes, multimeters, logic analyzers, power supplies) to characterize failures and confirm hypotheses
• Leverage Linux-based environments and develop/maintain Tcl scripts to automate tests, extract data, reproduce failures, and support diagnostics
• Document analysis results, root causes, and corrective actions clearly and thoroughly
• Interface with cross-functional teams (Engineering, Manufacturing, Quality, Field Service) to drive timely and aligned issue resolution
• Identify recurring failure patterns and propose continuous improvements to design, process, or test methodologies
• Ensure compliance with internal procedures, quality requirements, and relevant industrial standards

Requirements:

• Engineering degree in Electronics (mandatory)
• Minimum 5 years of experience in failure analysis, hardware debugging, electronics design, manufacturing support, or related technical role
• Deep expertise in complex electronic assemblies, including mixed-signal, digital, analog, and power electronics
• Strong system-level understanding of mechanical integration, power management, and thermal impacts on electronics reliability
• Hands-on proficiency with laboratory equipment (oscilloscopes, multimeters, logic analyzers, power supplies)
• Solid experience working in Linux environments for analysis, data extraction, and debugging
• Proven ability to develop and deploy Tcl scripts for test automation and diagnostics
• Fluency in both French and English (spoken and written); German language skills are a plus

Experience Level: Senior Employment Type: Full-time Workplace Type: Onsite Category: Engineering Industry: Technology Salary Range: Competitive salary Required Skills: Failure analysis, electronics design, manufacturing support, Linux, Tcl scripting, oscilloscopes, multimeters, logic analyzers, power supplies Preferred Skills: German language skills, experience with complex electronic assemblies, system-level understanding of mechanical integration, power management, and thermal impacts on electronics reliability

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You will work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic and high-energy work environment to bring industry-defining products to market.

Your responsibilities will include:

• Collaborating with cross-functional teams to craft essential next-generation product features that are important for performance, power optimization, and power management.
• Collaborating to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation.
• Working with various Arch & Design teams to come up with test plans of new features.
• Collaborating with other validation & bring-up teams to bring up/characterize silicon power and power saving features.
• Working with design & estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.
• Developing power consumption models to be used in binning, productization, and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.

We need to see:

• B. Tech or M. Tech in Electronics Engineering stream, with 3+ years related work experience, excellent problem-solving, collaborative, and interpersonal skills.
• Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.
• Hands-on experience with silicon bring up, validation, and productization, good knowledge in board and system design considerations, Power supply design.
• Very good problem-solving and hardware debugging skills, very good data analysis and logical reasoning skills.
• Strong familiarity with HW lab environment and understanding of various lab equipment.
• Experience in working with windows. Linux exposure is highly preferred.
• Working experience with scripting languages like perl and/or python is a plus point.
• Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high-energy environment.
• Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability, and aging mechanisms.
• Background with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

Get an idea of what your daily routine around the office can be like

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $266K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We are seeking a highly skilled cross-stack power architect with deep expertise in making ML systems energy efficient. This hands-on individual contributor will sit within our silicon implementation team and work closely with architecture, kernels, chip design, silicon implementation, platform design, and the broader industry ecosystem to architect, implement, and deploy performance-per-watt optimized next-generation AI accelerator chips and systems.

In this role, you will:

• Oversee power architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to maximize performance under power envelope

• Build chip and system-level power models grounded in empirical data and experience to guide organization-wide energy efficiency strategy. This requires a detailed understanding of ML workloads, ML chip and system architecture, silicon design, implementation, and characterization

• Collaborate with chip and platform architecture/design teams to explore and implement power management features, including the specification and implementation of digital/mixed-signal IP, sensing and telemetry, firmware/system software, and silicon characterization methodology (in partnership with engineering teams)

• Partner with silicon design and implementation teams, to optimize performance under power envelope. This includes (but is not limited to) clocking and power domain architecture, voltage/frequency selection, microarchitecture and physical-design driven power reduction, post-silicon voltage margin optimization and workload-informed power optimization

• Work with ecosystem partners (EDA, ASIC, IP, component vendors) to drive innovations that can improve energy efficiency

Qualifications:

• Relevant degree and strong industry experience focused on the end-to-end energy-efficient ML silicon codesign

• Hands-on experience with power architecture, power estimation, power management and power optimization is required.

• Fundamental understanding of ML chip and platform architecture, performance modeling and workload power/performance characteristics is strongly preferred.

• Hands-on experience with power bring-up and power validation is strongly preferred.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $250K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

The Frontier Systems team at OpenAI builds, launches, and supports the largest supercomputers in the world that OpenAI uses for its most cutting-edge model training.

We take data center designs, turn them into real, working systems and build any software needed for running large-scale frontier model trainings.

Our mission is to bring up, stabilize and keep these hyperscale supercomputers reliable and efficient during the training of the frontier models.

About the Role

On the Frontier Systems team, you’ll build critical infrastructure that keeps our supercomputers running reliably for cutting-edge AI research. Even a single hardware failure can derail a large-scale training run, so minimizing disruptions is core to the mission.

Engineers here own their work end-to-end and are trusted to make a real impact. This role is for someone who goes deep - who thrives on root-causing system-level issues and building automation to catch and fix problems at scale.

In this role, you will:

• Own and improve the system health checks that keep our hyperscale supercomputers stable during model training.

• Lead deep dives into hardware failures and system-level bugs to understand how things break at scale.

• Build automation that monitors and fixes issues across thousands of machines - so researchers can keep moving without interruption.

You might thrive in this role if you have:

• 7+ years of industry experience in software engineering

• Proficiency with Python and shell scripting

• A high degree of comfort digging into noisy data with SQL, PromQL, and Pandas or any other tool necessary

• Experience developing reproducible analyses

• A balance of strengths in building and operationalizing

Prior hardware expertise is not required for this role.

Bonus if you have:

• Experience with low level details of hardware components, protocols, and associated Linux tooling (e.g., PCIe, Infiniband, networking, power management, kernel perf tuning)

• Experience with visualization of large data centers and networks.

• Expertise with network operations and tooling

• Expertise with power management and stabilization

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

You will lead the NVM TestChip and IP design flow across multiple technologies and foundries, ensuring robust and scalable solutions for diverse applications.

• Architecting, designing, and verifying CMOS-based non-volatile memory IP modules, from concept to production tapeout.
• Collaborating with product engineers to perform silicon verification, in-depth testing, and debugging to validate IP performance on silicon.
• Conducting post-layout extraction, simulation, and comprehensive testing in conjunction with silicon validation teams.

What you need

• 5–12+ years of industry experience in circuit design, with a strong emphasis on analog circuit design and analysis; memory design experience is a significant plus.
• Deep understanding of layout considerations for advanced nodes, including parasitic effects, matching techniques, and signal integrity.
• Expertise in electrical problem-solving, including root cause analysis of circuit failures and development of effective solutions.
• Hands-on experience with TestChip tapeout flows, silicon debugging (FIB, micro-probing, post-layout RC extraction), and statistical design methodologies (e.g., Monte-Carlo analysis).
• Strong transistor-level analog design skills, including sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design.
• Proficiency with circuit simulation tools (HSIM, HSPICE, etc.) and custom schematic/layout editors (e.g., Custom Compiler).
• Experience with low power design, power management circuitry, and FinFET design is a plus.

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