These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a Sr Director of ASIC Physical Design, you will own and drive the end-to-end physical design flow for high-speed die-to-die interconnect and interface chips targeting 2 GHz+ on advanced process nodes (sub-7nm/5nm/3nm).

Key responsibilities include:

• Leading floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification with emphasis on die-to-die interface placement and bump/pad ring constraints.

• Achieving timing closure across all corners and modes, with expertise in multi-corner multi-mode sign-off for high-speed serial and parallel interfaces.

• Driving power integrity, signal integrity, and thermal analysis to meet stringent tape-out criteria for high-bandwidth die-to-die links.

• Defining and owning physical design methodology, Synopsys tool flows, and best practices across the organization.

• Building, mentoring, and leading a globally distributed team, establishing effective communication and collaboration norms to foster cohesion and engineering excellence.

• Collaborating cross-functionally with RTL design, DV, architecture, CAD/EDA, and program management teams globally.

• Owning physical design schedules and milestones for multiple concurrent projects, communicating status to senior leadership and mitigating risks proactively.

• Championing automation and scripting to improve PPA outcomes and team productivity.

The impact you will have:

• Enable the physical implementation of high-speed die-to-die interconnects that power large-scale AI accelerators, GPU clusters, and multi-die systems.

• Deliver ultra-low latency, high-bandwidth chip-to-chip communication at the core of next-generation AI infrastructure.

• Advance the adoption of cutting-edge process nodes and interface standards, positioning Synopsys as a leader in silicon innovation.

• Ensure robust engineering quality, execution velocity, and successful tape-outs across global teams.

• Drive organizational excellence by fostering a culture of accountability, growth, and technical mastery.

• Shape methodologies and tool flows that set industry benchmarks for high-speed, advanced-node physical design.

• Contribute to the strategic direction of AI silicon and interconnect products, impacting the broader technology ecosystem.

Requirements:

• 15+ years of hands-on physical design experience, with deep expertise in high-frequency (≥2 GHz) chip design.

• Expertise with Synopsys IC Compiler II (ICC2), PrimeTime, Fusion Compiler, StarRC, IC Validator, and PrimePower.

• Track record of taping out high-speed interface ICs, die-to-die interconnect chips, SerDes, or similar designs at advanced process nodes (7nm, 5nm, 3nm).

• Understanding of die-to-die interface standards and protocols (UCIe, BoW, HBI, XSR, or proprietary) and their physical implementation.

• Experience with power intent flows (UPF/CPF), low-power design techniques, and dynamic/static power optimization.

• Strong scripting skills (Tcl, Python, Perl) for tool flow automation and PPA optimization.

• Proven ability to lead and grow globally distributed engineering teams of 10+ people.

• Cross-cultural communication and collaboration skills; experience working across US, Asia, or European engineering centers.

• BS or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).

As a Sr Director of ASIC Physical Design, you will join a globally distributed Silicon Engineering team focused on the physical implementation of cutting-edge AI silicon and high-speed die-to-die interconnects.

Our team spans multiple sites and time zones, collaborating with process technology, packaging, RTL, DV, architecture, CAD/EDA, and program management teams.

We pride ourselves on a culture of technical depth, low bureaucracy, and a relentless drive for engineering excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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