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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c7ea2375-1cc"},"title":"ASIC Physical Design, Sr Director","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Sr Director of ASIC Physical Design, you will own and drive the end-to-end physical design flow for high-speed die-to-die interconnect and interface chips targeting 2 GHz+ on advanced process nodes (sub-7nm/5nm/3nm).</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification with emphasis on die-to-die interface placement and bump/pad ring constraints.</li>\n</ul>\n<ul>\n<li>Achieving timing closure across all corners and modes, with expertise in multi-corner multi-mode sign-off for high-speed serial and parallel interfaces.</li>\n</ul>\n<ul>\n<li>Driving power integrity, signal integrity, and thermal analysis to meet stringent tape-out criteria for high-bandwidth die-to-die links.</li>\n</ul>\n<ul>\n<li>Defining and owning physical design methodology, Synopsys tool flows, and best practices across the organization.</li>\n</ul>\n<ul>\n<li>Building, mentoring, and leading a globally distributed team, establishing effective communication and collaboration norms to foster cohesion and engineering excellence.</li>\n</ul>\n<ul>\n<li>Collaborating cross-functionally with RTL design, DV, architecture, CAD/EDA, and program management teams globally.</li>\n</ul>\n<ul>\n<li>Owning physical design schedules and milestones for multiple concurrent projects, communicating status to senior leadership and mitigating risks proactively.</li>\n</ul>\n<ul>\n<li>Championing automation and scripting to improve PPA outcomes and team productivity.</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Enable the physical implementation of high-speed die-to-die interconnects that power large-scale AI accelerators, GPU clusters, and multi-die systems.</li>\n</ul>\n<ul>\n<li>Deliver ultra-low latency, high-bandwidth chip-to-chip communication at the core of next-generation AI infrastructure.</li>\n</ul>\n<ul>\n<li>Advance the adoption of cutting-edge process nodes and interface standards, positioning Synopsys as a leader in silicon innovation.</li>\n</ul>\n<ul>\n<li>Ensure robust engineering quality, execution velocity, and successful tape-outs across global teams.</li>\n</ul>\n<ul>\n<li>Drive organizational excellence by fostering a culture of accountability, growth, and technical mastery.</li>\n</ul>\n<ul>\n<li>Shape methodologies and tool flows that set industry benchmarks for high-speed, advanced-node physical design.</li>\n</ul>\n<ul>\n<li>Contribute to the strategic direction of AI silicon and interconnect products, impacting the broader technology ecosystem.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>15+ years of hands-on physical design experience, with deep expertise in high-frequency (≥2 GHz) chip design.</li>\n</ul>\n<ul>\n<li>Expertise with Synopsys IC Compiler II (ICC2), PrimeTime, Fusion Compiler, StarRC, IC Validator, and PrimePower.</li>\n</ul>\n<ul>\n<li>Track record of taping out high-speed interface ICs, die-to-die interconnect chips, SerDes, or similar designs at advanced process nodes (7nm, 5nm, 3nm).</li>\n</ul>\n<ul>\n<li>Understanding of die-to-die interface standards and protocols (UCIe, BoW, HBI, XSR, or proprietary) and their physical implementation.</li>\n</ul>\n<ul>\n<li>Experience with power intent flows (UPF/CPF), low-power design techniques, and dynamic/static power optimization.</li>\n</ul>\n<ul>\n<li>Strong scripting skills (Tcl, Python, Perl) for tool flow automation and PPA optimization.</li>\n</ul>\n<ul>\n<li>Proven ability to lead and grow globally distributed engineering teams of 10+ people.</li>\n</ul>\n<ul>\n<li>Cross-cultural communication and collaboration skills; experience working across US, Asia, or European engineering centers.</li>\n</ul>\n<ul>\n<li>BS or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).</li>\n</ul>\n<p>As a Sr Director of ASIC Physical Design, you will join a globally distributed Silicon Engineering team focused on the physical implementation of cutting-edge AI silicon and high-speed die-to-die interconnects.</p>\n<p>Our team spans multiple sites and time zones, collaborating with process technology, packaging, RTL, DV, architecture, CAD/EDA, and program management teams.</p>\n<p>We pride ourselves on a culture of technical depth, low bureaucracy, and a relentless drive for engineering excellence.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c7ea2375-1cc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-director-in-hcmc-da-nang/44408/93750516784","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Physical Design","High-Frequency Chip Design","Synopsys IC Compiler II","PrimeTime","Fusion Compiler","StarRC","IC Validator","PrimePower","Die-to-Die Interface Standards","Power Intent Flows","Low-Power Design Techniques","Dynamic/Static Power Optimization","Scripting Skills (Tcl, Python, Perl)","Leadership and Team Management"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:13:37.968Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Physical Design, High-Frequency Chip Design, Synopsys IC Compiler II, PrimeTime, Fusion Compiler, StarRC, IC Validator, PrimePower, Die-to-Die Interface Standards, Power Intent Flows, Low-Power Design Techniques, Dynamic/Static Power Optimization, Scripting Skills (Tcl, Python, Perl), Leadership and Team Management"}]}