Key responsibilities include:

• Working with a cross-functional team to design market-leading hardware products.
• Full cycle PCB design, including collecting requirements, schematic design, component selection, supervision or completion of layout, bring-up, test, debug, and integration with the system.
• Driving product maturity through rapid prototyping, design verification, and qualification activities.
• Applying modern design standards and guidelines to create high-reliability, highly manufacturable assemblies.
• Implementing combinations of high-speed digital, precision analog, RF, and high-power designs.
• Leading the team in establishing internal guidelines for design for manufacturing (DFM) and quality fabrication and assembly outputs.
• Conducting peer-level and cross-discipline design reviews.
• Low-level firmware development for bring-up and test.
• Root cause analysis in support of production operations.

Requirements include:

• 4+ years of professional experience in hardware product development.
• Full understanding of PCB Layout techniques to meet mechanical, electrical, and manufacturing requirements.
• Ability to read and interpret schematics and apply best practices appropriate for each design.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Knowledge of modern analog and digital electronics and electronic circuits.
• Ability to determine work priorities based on broad direction from management.
• Experience using Altium Designer or equivalent E-CAD tools.
• Excellent communication skills and ability to work effectively with others.
• Ability to work within our company and team culture.
• Must have an active U.S. Secret security clearance.

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In addition to a competitive salary, we offer a variety of benefits to support your needs, including medical, dental, and vision insurance, company-paid life insurance, voluntary supplemental life insurance, short and long-term disability insurance, flexible spending account, health savings account, tuition reimbursement, ability to participate in employee stock purchase program (ESPP), mental wellness benefits through Spring Health, family-forming support provided by Carrot, paid parental leave, flexible, full-service childcare support with Kinside, 401(k) with a generous employer match, flexible PTO, catered lunch each day in our office and data center locations, and a casual work environment.

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The role involves leading the complete subsystem lifecycle,from requirements gathering and architecture definition to final release phases. This includes crafting subsystem architectures, developing comprehensive functional specifications, defining and implementing micro-architectures, and driving RTL quality checks.

The ideal candidate will have a minimum of 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects. They should be proficient with standard protocols including PCIe, DDR, UFS, USB, and AMBA, and have demonstrated expertise in low power design methodologies and DFT architecture.

As a leader, the candidate will inspire and guide their peers, leveraging their experience to drive innovation, efficiency, and reliability. They should be committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions.

The role offers a comprehensive range of health, wellness, and financial benefits to cater to the needs of the employee. The total rewards include both monetary and non-monetary offerings.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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At Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.

Key Responsibilities:

• Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
• Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.
• Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.
• Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).
• Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.
• Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys' product lines.

Impact:

• Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.
• Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.
• Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys' tools, driving industry-leading outcomes.
• Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.
• Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.
• Strengthen Synopsys' position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.

Requirements:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.
• 5+ years of experience in chip design, EDA, or related fields.
• Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).
• Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.
• Solid understanding of Unix/Linux environments and design flow automation.
• Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.
• Familiarity with low power design techniques, computer architecture, and machine learning principles.

Who We're Looking For:

• A creative problem solver who approaches challenges with curiosity and resilience.
• An effective communicator who collaborates well with multidisciplinary teams.
• Detail-oriented with a passion for quality and continuous improvement.
• Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.
• Committed to learning, growth, and sharing knowledge with others.

The Team You'll Be A Part Of:

You'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Collaborate to define product goals Conceive, design, evaluate, and produce novel gaming hardware Work closely with contract manufacturers to prototype and produce hardware at scales from tens to millions of units

Electrical engineers at Valve have significant industry experience. We usually don’t hire recent graduates.

Members of our team typically have the following skills:

Proven start-to-finish design skills with industry-standard CAD/EDA tools (Altium Designer experience strongly preferred), including schematic entry, PCB layout, component definition, and CAD library management Hands-on electronics prototyping experience, including soldering and rework of fine-pitch SMT components Strong lab skills, including the use of common test and measurement equipment (oscilloscopes, logic analyzers, etc.) to debug and characterize complex electronic circuits Experience with embedded systems design and common digital communication interfaces (USB, SPI, I2C) Experience working directly on-site with manufacturing partners A proven track record of designing and shipping high-volume consumer electronics products Experience in design for manufacture and design for test (DFM/DFT) of electronic devices Ability to think and work across a variety of subject areas

Bachelor's degree (or equivalent work experience) in electrical engineering or a related field

Our team includes individuals with expertise in the following areas:

Analog circuit design and simulation (e.g. SPICE) Low-power design, including battery management and charging circuits for portable devices RF/wireless circuit design, including design of antennas and for EMC Firmware development for 8, 16, 32-bit microcontrollers (e.g. ARM) High speed/HDI board design Digital Signal Processing (DSP) High speed video interfaces (HDMI, Display Port, LVDS, MIPI) Regulatory compliance testing (e.g. FCC/CE/UL) C/C++ software development Test automation FPGA/ASIC design

What We Offer

An organization where 100% of time is dedicated as groups see fit The opportunity to collaborate with experts across a range of disciplines A work environment and flexible schedule in support of families and domestic partnerships A culture eager to become stronger through diversity of all forms Exceptional health insurance coverage Unrivaled employer match for our 401(k) retirement plan Generous vacation and family leave On-site amenities in support of health and efficiency Fertility and adoption assistance Reimbursement for child care during interviews

Valve strives to improve the diversity of our teams to better serve our diverse global audience. We welcome and encourage individuals from all backgrounds to apply.

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What you'll do

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in SystemVerilog and Verilog for RTL development.

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What you'll do

You will lead the NVM TestChip and IP design flow across multiple technologies and foundries, ensuring robust and scalable solutions for diverse applications.

• Architecting, designing, and verifying CMOS-based non-volatile memory IP modules, from concept to production tapeout.
• Collaborating with product engineers to perform silicon verification, in-depth testing, and debugging to validate IP performance on silicon.
• Conducting post-layout extraction, simulation, and comprehensive testing in conjunction with silicon validation teams.

What you need

• 5–12+ years of industry experience in circuit design, with a strong emphasis on analog circuit design and analysis; memory design experience is a significant plus.
• Deep understanding of layout considerations for advanced nodes, including parasitic effects, matching techniques, and signal integrity.
• Expertise in electrical problem-solving, including root cause analysis of circuit failures and development of effective solutions.
• Hands-on experience with TestChip tapeout flows, silicon debugging (FIB, micro-probing, post-layout RC extraction), and statistical design methodologies (e.g., Monte-Carlo analysis).
• Strong transistor-level analog design skills, including sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design.
• Proficiency with circuit simulation tools (HSIM, HSPICE, etc.) and custom schematic/layout editors (e.g., Custom Compiler).
• Experience with low power design, power management circuitry, and FinFET design is a plus.

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