{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/power-architecture"},"x-facet":{"type":"skill","slug":"power-architecture","display":"Power Architecture","count":2},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a3415fac-8d5"},"title":"ML HW-SW Co-design Software Manager","description":"<p>We are seeking a highly motivated and experienced Software Engineering Manager to join our HW-SW Co-design team and drive groundbreaking advances for machine learning acceleration.</p>\n<p>At Google DeepMind, we&#39;ve built a unique culture and work environment where long-term ambitious research can flourish. We are a team of scientists, engineers, machine learning experts and more, working together to advance the state of the art in artificial intelligence.</p>\n<p>The role requires a blend of deep technical expertise, strategic thinking, and strong leadership. You will lead a multi-disciplinary team to evolve the software side of our hw-sw co-design project.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Closely collaborate with our hardware team to define and drive strategy for next-generation machine learning accelerators.</li>\n<li>Manage relationships and technical execution across a virtual team that spans both Google and outside partners.</li>\n<li>Drive the team to deliver high-quality aligned to tight schedules.</li>\n</ul>\n<p>Minimum Qualifications:</p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering, Computer Science, or equivalent practical experience.</li>\n<li>10+ years of experience in ASIC design and development.</li>\n<li>3+ years of Management Experience</li>\n<li>Proven track record of technical leadership and successfully delivering complex silicon projects (tape-outs) to production.</li>\n<li>Deep expertise in at least one core silicon discipline (e.g., RTL, PD, DV) and strong familiarity with the entire ASIC flow.</li>\n<li>Experience with managing silicon vendors and other external partners.</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>Master&#39;s or Ph.D. in a related field.</li>\n<li>Experience leading and managing teams across the full silicon development cycle, from RTL to bringup.</li>\n<li>Experience with high-performance compute IPs (e.g., GPUs, ML accelerators).</li>\n<li>Knowledge of high-performance and low-power architectures for ML acceleration.</li>\n<li>Excellent communication, and leadership skills.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a3415fac-8d5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Google DeepMind","sameAs":"https://deepmind.com/","logo":"https://logos.yubhub.co/deepmind.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/deepmind/jobs/7558868","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC design and development","RTL","PD","DV","Silicon vendors management","External partners management","Technical leadership","Complex silicon projects delivery"],"x-skills-preferred":["Master's or Ph.D. in a related field","Experience leading and managing teams","High-performance compute IPs","High-performance and low-power architectures for ML acceleration","Excellent communication, and leadership skills"],"datePosted":"2026-03-16T14:43:22.254Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View, California, US"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design and development, RTL, PD, DV, Silicon vendors management, External partners management, Technical leadership, Complex silicon projects delivery, Master's or Ph.D. in a related field, Experience leading and managing teams, High-performance compute IPs, High-performance and low-power architectures for ML acceleration, Excellent communication, and leadership skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9eb55da5-7fd"},"title":"Power Architect","description":"<p><strong>Power Architect</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$266K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled cross-stack power architect with deep expertise in making ML systems energy efficient. This hands-on individual contributor will sit within our silicon implementation team and work closely with architecture, kernels, chip design, silicon implementation, platform design, and the broader industry ecosystem to architect, implement, and deploy performance-per-watt optimized next-generation AI accelerator chips and systems.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Oversee power architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to maximize performance under power envelope</li>\n</ul>\n<ul>\n<li>Build chip and system-level power models grounded in empirical data and experience to guide organization-wide energy efficiency strategy. This requires a detailed understanding of ML workloads, ML chip and system architecture, silicon design, implementation, and characterization</li>\n</ul>\n<ul>\n<li>Collaborate with chip and platform architecture/design teams to explore and implement power management features, including the specification and implementation of digital/mixed-signal IP, sensing and telemetry, firmware/system software, and silicon characterization methodology (in partnership with engineering teams)</li>\n</ul>\n<ul>\n<li>Partner with silicon design and implementation teams, to optimize performance under power envelope. This includes (but is not limited to) clocking and power domain architecture, voltage/frequency selection, microarchitecture and physical-design driven power reduction, post-silicon voltage margin optimization and workload-informed power optimization</li>\n</ul>\n<ul>\n<li>Work with ecosystem partners (EDA, ASIC, IP, component vendors) to drive innovations that can improve energy efficiency</li>\n</ul>\n<p><strong>Qualifications:</strong></p>\n<ul>\n<li>Relevant degree and strong industry experience focused on the end-to-end energy-efficient ML silicon codesign</li>\n</ul>\n<ul>\n<li>Hands-on experience with power architecture, power estimation, power management and power optimization is required.</li>\n</ul>\n<ul>\n<li>Fundamental understanding of ML chip and platform architecture, performance modeling and workload power/performance characteristics is strongly preferred.</li>\n</ul>\n<ul>\n<li>Hands-on experience with power bring-up and power validation is strongly preferred.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9eb55da5-7fd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/12ae9cf8-54e8-40fb-aba4-1f737ce68052","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$266K – $445K • Offers Equity","x-skills-required":["Power architecture","Power estimation","Power management","Power optimization","ML chip and system architecture","Silicon design","Implementation","Characterization"],"x-skills-preferred":["Digital/mixed-signal IP","Sensing and telemetry","Firmware/system software","Silicon characterization methodology","Clocking and power domain architecture","Voltage/frequency selection","Microarchitecture and physical-design driven power reduction","Post-silicon voltage margin optimization","Workload-informed power optimization"],"datePosted":"2026-03-06T18:38:42.250Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Power architecture, Power estimation, Power management, Power optimization, ML chip and system architecture, Silicon design, Implementation, Characterization, Digital/mixed-signal IP, Sensing and telemetry, Firmware/system software, Silicon characterization methodology, Clocking and power domain architecture, Voltage/frequency selection, Microarchitecture and physical-design driven power reduction, Post-silicon voltage margin optimization, Workload-informed power optimization","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":266000,"maxValue":445000,"unitText":"YEAR"}}}]}