At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and passionate ASIC Digital Design Engineer who thrives in dynamic and collaborative environments. You have a proven track record in RTL design and verification, and you are excited about contributing to cutting-edge technology. With your extensive expertise, you can handle complex and unique issues, often requiring innovative solutions. You are adept at communicating with both internal and external stakeholders, ensuring that your designs meet the highest standards of quality and performance.

What You’ll Be Doing:

• Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.
• Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.
• Developing and executing comprehensive test plans to verify the functionality and performance of your designs.
• Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.
• Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team.
• Staying up to date with the latest industry trends and technologies, continuously improving your skills and knowledge.

The Impact You Will Have:

• Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.
• Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.
• Enhancing the overall quality and performance of Synopsys' products through meticulous design and verification processes.
• Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.
• Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.
• Contributing to Synopsys' reputation as a leader in the semiconductor industry through your expertise and innovative solutions.

What You’ll Need:

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design, using industry standard HDLs; Verilog, SystemVerilog.
• Proficiency in using industry-standard EDA tools and methodologies for design and verification.
• Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC design, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Broad knowledge of the full digital ASIC and IP development flow, including RTL design, lint, CDC, RDC, synthesis and STA.
• Experience with power analysis and RTL level power optimization techniques.
• Familiarity with verification languages and methodologies; SystemVerilog, SVA, UVM.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Who You Are:

• A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.
• A strategic thinker with the ability to implement goals that have a direct impact on department results.
• A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.
• A collaborative team player who thrives in dynamic and fast-paced environments.
• A lifelong learner who stays up to date with the latest industry trends and continuously seeks to improve their skills and knowledge.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. Our team collaborates closely with various departments, including analog design, physical design, and applications engineering, to ensure the seamless integration of all design components. We are committed to continuous learning and improvement, fostering a culture of innovation and excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a seasoned R&D Engineer with over 4 years of experience, specializing in the development of complex software projects. Your expertise in C/C++ coding and a solid understanding of data structures and algorithms are second to none. You are passionate about learning and exploring new technologies, which drives your innovative approach to problem-solving. Your ability to resolve issues creatively and autonomously select methods and techniques to achieve solutions sets you apart. You thrive on working from project inception to completion and enjoy contributing to complex aspects of a project. Your ability to mentor junior peers and network with internal and external personnel on assigned tasks showcases your leadership and communication skills.

As a Staff R&D SW Engineer - Power Analysis, you will be responsible for designing, developing, and troubleshooting software programs as part of the Platform Power team for Fusion Compiler/ICC2. You will lead the development of complex software projects with a focus on C/C++ coding, applying your knowledge of data structures and algorithms to solve intricate problems, and exploring and integrating new technologies to enhance software performance and functionality.

The impact you will have is enhancing the efficiency and effectiveness of software programs within the Platform Power team, driving innovation through the application of cutting-edge technologies, contributing to the successful completion of complex projects that push the boundaries of technological advancements, fostering a collaborative environment by networking with internal and external personnel, elevating the team's capabilities by mentoring junior engineers, and ensuring the delivery of high-quality software solutions that meet and exceed organizational goals.

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Key responsibilities include:

• Strong problem-solving skills and the ability to debug complex software issues in large-scale systems.
• 2–5 years of industry experience in software development or EDA-related R&D roles.
• Ability to contribute independently to feature development, bug fixes, and performance improvements.
• Good communication skills and the ability to collaborate effectively within a cross-functional team.

Ideal candidates will have proficiency in C/C++ development, with strong fundamentals in data structures and algorithms. Experience working on Linux platforms and familiarity with build systems, debugging tools, and development workflows on Linux is a plus. Exposure to scripting languages such as Tcl, Perl, or Python will be an added advantage.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You will work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic and high-energy work environment to bring industry-defining products to market.

Your responsibilities will include:

• Collaborating with cross-functional teams to craft essential next-generation product features that are important for performance, power optimization, and power management.
• Collaborating to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation.
• Working with various Arch & Design teams to come up with test plans of new features.
• Collaborating with other validation & bring-up teams to bring up/characterize silicon power and power saving features.
• Working with design & estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.
• Developing power consumption models to be used in binning, productization, and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.

We need to see:

• B. Tech or M. Tech in Electronics Engineering stream, with 3+ years related work experience, excellent problem-solving, collaborative, and interpersonal skills.
• Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.
• Hands-on experience with silicon bring up, validation, and productization, good knowledge in board and system design considerations, Power supply design.
• Very good problem-solving and hardware debugging skills, very good data analysis and logical reasoning skills.
• Strong familiarity with HW lab environment and understanding of various lab equipment.
• Experience in working with windows. Linux exposure is highly preferred.
• Working experience with scripting languages like perl and/or python is a plus point.
• Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high-energy environment.
• Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability, and aging mechanisms.
• Background with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.

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You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.

You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.

You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.

You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.

You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

• Providing expert support and training to customers on PrimeTime, PrimeClosure, and PrimeShield, ensuring optimal use and maximum productivity.
• Independently coordinating and supporting multiple customer designs through tape-out, verifying designs meet or exceed customer expectations.

What you need

• Bachelor’s degree in Electrical Engineering with a minimum of 12 years of experience, or a Master’s degree with at least 8 years of experience.
• In-depth understanding of timing, power, statistical and electromigration characterization, and signal integrity in advanced SoC design.

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