Collaborate with experienced mixed-signal design and verification teams to develop and verify high-speed NRZ and PAM-based SerDes products.

Engage in dynamic PHY IP development, tackling challenging problems and adapting to constant technological advances.

Participate in initial and ongoing training led by top experts, gaining exposure to advanced digital and analog design methodologies.

Contribute to scripting and automation tasks to support design verification processes.

You'll be working on real-world projects, developing high-speed NRZ and PAM-based SerDes products, engaging in dynamic PHY IP development, participating in training sessions, and contributing to scripting and automation tasks.

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As a highly skilled A&MS Design Staff Engineer, you will lead the design of analog and mixed-signal circuits, blocks, and subsystems. You will develop architecture proposals and evaluate design tradeoffs for performance, power, area, and cost. You will perform circuit simulation, verification, and optimization using industry-standard EDA tools. You will support tape-out activities, silicon bring-up, debug, and characterization. You will collaborate with layout engineers to ensure design intent, robustness, and manufacturability. You will define and execute validation plans to meet product requirements. You will review design specifications, schematics, and test results. You will mentor junior engineers and contribute technical leadership across projects. You will work closely with system, digital, validation, and product teams to resolve technical issues. You will drive continuous improvement in design methodologies and best practices.

Key responsibilities include:

• Leading the design of analog and mixed-signal circuits, blocks, and subsystems
• Developing architecture proposals and evaluating design tradeoffs for performance, power, area, and cost
• Performing circuit simulation, verification, and optimization using industry-standard EDA tools
• Supporting tape-out activities, silicon bring-up, debug, and characterization
• Collaborating with layout engineers to ensure design intent, robustness, and manufacturability
• Defining and executing validation plans to meet product requirements
• Reviewing design specifications, schematics, and test results
• Mentoring junior engineers and contributing technical leadership across projects
• Working closely with system, digital, validation, and product teams to resolve technical issues
• Driving continuous improvement in design methodologies and best practices

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As a Staff Engineer in Analog Design, you will be part of a fast-growing team dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. You will design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.

Key Responsibilities:

• Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.
• Define and plan analog design activities, setting clear milestones and deliverables for project success.
• Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed.
• Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area.
• Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements.

Impact:

• Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices.
• Enhance Synopsys' reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs.
• Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace.
• Foster innovation and continuous improvement within the analog and mixed-signal R&D team, setting benchmarks for technical excellence.

Requirements:

• M.Sc. degree in Electrical Engineering with 3+ years of experience, or Ph.D. in Electrical Engineering with 1.5+ years of experience.
• Background in CMOS analog circuit design, preferably including ADC, DAC, PLL, Rx, Tx, References, or related areas.
• Familiarity with industry-standard IC design packages and EDA tools.
• Experience working in UNIX operating systems.
• Good written and verbal communication skills in English.
• System-level knowledge of SerDes architecture is a plus.

Team:

You will join Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a skilled and motivated analog design engineer, passionate about developing advanced integrated circuits for high-speed communication systems. With a good understanding of CMOS technologies and track record in designing medium complexity analog circuits, you thrive in fast-paced, collaborative environments. You have expertise in some analog functions such as ADCs, DACs, PLLs, and transceiver blocks, and you are adept at delivering robust designs that meet stringent electrical specifications and reliability constraints. Analytical and detail-oriented, you know how to evaluate the impact of layout parasitics and optimizing for performance, power, and area.

You are comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills enable you to interact effectively within a global and multi-cultural team, and your organizational abilities ensure timely delivery of milestones. You are proactive in problem-solving and continuous improvement, and you value mentorship, sometimes guiding junior engineers. Whether you have industry experience or specialized academic training, you are eager to contribute to cutting-edge projects that power innovations in mobile, automotive, cloud, HPC, AI, IoT, 5G, and storage. Inclusivity, diversity, and collaboration are important to you, and you are ready to make a significant impact at Synopsys.

Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. Define and plan analog design activities, setting clear milestones and deliverables for project success. Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed. Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area. Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements. Engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices. Enhance Synopsys' reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs. Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace. Foster innovation and continuous improvement within the analog and mixed-signal R&D team, setting benchmarks for technical excellence.

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You will be comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills will enable you to interact effectively within a global and multi-cultural team, and your organizational abilities will ensure timely delivery of milestones. You will be proactive in problem-solving and continuous improvement, and you will value mentorship, sometimes guiding junior engineers.

You will join Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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As an experienced analog design engineer, you will be responsible for driving the design and development of medium to large complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. You will guide analog designers to ensure designs meet electrical specifications and reliability constraints. You will also define methods and procedures for project execution, including planning analog design activities and associated milestones.

You will conduct and prepare design reviews, following up on improvements, and ensuring high quality outcomes. You will evaluate and minimize parasitic effects related to layout implementations, collaborating with layout teams to optimize performance, power, and area. You will ensure silicon correlation with simulation results, validating design accuracy and robustness.

You will mentor and train less experienced analog designers, fostering skill development within the team. You will engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

The successful candidate will have a proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References, etc. They will have experience coordinating design activities across teams and managing medium complexity designs. They will be familiar with industry-standard IC design packages and EDA tools.

The ideal candidate will be a collaborative team player who thrives in multicultural, global environments. They will be an analytical thinker with strong problem-solving and organizational skills. They will be an effective communicator, able to lead reviews and share knowledge clearly.

The team you will be a part of is Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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