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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cd9b4525-d64"},"title":"Senior Electrical Engineer","description":"<p>The Anduril Battlespace Awareness Radar team is seeking an experienced Senior Electrical Engineer to transform ambitious concepts into manufacturable reality for the next generation of US radars. In this role, you will design high-speed mixed-signal architectures and circuits, manage signal integrity in complex PCBs, and mature prototypes into products.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Designing combinations of high-speed digital, precision analog, RF, and high-power architectures</li>\n<li>Designing embedded electronics from concept to functional prototype, including hardware selection, schematic &amp; PCB design, board bring-up, and system level integration</li>\n<li>Troubleshooting issues that span the electrical and software boundaries, with solid skills using both lab equipment (Oscilloscopes, DMM, etc.) and basic software debugging tools</li>\n<li>Working with modern SoCs and networking hardware to build Anduril platforms</li>\n<li>Collaborating with firmware/software engineers for processor/peripheral selection, board bring up, and troubleshooting</li>\n<li>Working closely with other electrical, mechanical, software, firmware, and test engineers to deliver fully functional products</li>\n</ul>\n<p>Requirements include:</p>\n<ul>\n<li>Bachelor’s Degree in Electrical Engineering</li>\n<li>8+ years of experience designing, testing, and troubleshooting complex hardware, embedded systems, and products</li>\n<li>Demonstrated experience with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C</li>\n<li>Experience with microprocessor and microcontroller selection, configuration, and interfacing</li>\n<li>Experience with component, schematic capture, high speed board design, and guiding PCB layout</li>\n<li>Competence with test equipment such as oscilloscopes, logic analyzers, debuggers, current-probes, sprectrum/network analyzers, and automation of tests</li>\n<li>Familiarity with product development processes and tools</li>\n<li>Knowledge of embedded software development, including use of timers, interrupts, hardware peripherals such as SPI controllers and ADCs</li>\n<li>Experience with signal integrity and power integrity rules and simulation</li>\n<li>Exceptional organization and communication skills (both written and oral)</li>\n<li>Proficient with Altium Designer or equivalent electronic design tools</li>\n<li>Familiar with common programming languages like Python for test automation</li>\n</ul>\n<p>Preferred qualifications include:</p>\n<ul>\n<li>Familiarity with RF design and layout</li>\n<li>Past experience with placement and routing of PCBs</li>\n<li>Experience with JESD204 and PCIe</li>\n<li>Familiarity with military standards (MIL-STD-461/704/1275)</li>\n<li>Experience with high speed ADC/DAC&#39;s and software defined radios</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cd9b4525-d64","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anduril","sameAs":"https://www.anduril.com/","logo":"https://logos.yubhub.co/anduril.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/andurilindustries/jobs/5030375007","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$126,000-$167,000 USD","x-skills-required":["multi-gigabit SERDES","DDR memory busses","Ethernet MAC and PHY interfaces","FPGAs","SPI and I2C","microprocessor and microcontroller selection","component, schematic capture, high speed board design","signal integrity and power integrity rules and simulation","Altium Designer","Python for test automation"],"x-skills-preferred":["RF design and layout","placement and routing of PCBs","JESD204 and PCIe","military standards (MIL-STD-461/704/1275)","high speed ADC/DAC's and software defined radios"],"datePosted":"2026-04-24T15:18:15.364Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Fort Collins, Colorado, United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, SPI and I2C, microprocessor and microcontroller selection, component, schematic capture, high speed board design, signal integrity and power integrity rules and simulation, Altium Designer, Python for test automation, RF design and layout, placement and routing of PCBs, JESD204 and PCIe, military standards (MIL-STD-461/704/1275), high speed ADC/DAC's and software defined radios","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":126000,"maxValue":167000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_524edc8e-463"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_524edc8e-463","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-staff-engineer-16723/44408/93743819104","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Floor planning","Synthesis","Placement and routing","Timing closure","IP integration","Test chip methodology","Advanced verification flows","CAD tools","Design Compiler","PrimeTime","IC Compiler II/FC","ICV","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:19:07.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Floor planning, Synthesis, Placement and routing, Timing closure, IP integration, Test chip methodology, Advanced verification flows, CAD tools, Design Compiler, PrimeTime, IC Compiler II/FC, ICV, Calibre, RedHawk, FinFet technologies"}]}