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You will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.</li>\n<li>Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</li>\n<li>Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.</li>\n<li>Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.</li>\n<li>Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.</li>\n<li>Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.</li>\n<li>Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys&#39; technical edge.</li>\n</ul>\n<p>You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys&#39; reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.</p>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.</li>\n<li>5-8 years of hands-on experience in the Physical Verification (PV) domain.</li>\n<li>Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.</li>\n<li>Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.</li>\n<li>Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.</li>\n<li>Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.</li>\n<li>Exposure to competitive EDA tools and awareness of their strengths and limitations.</li>\n</ul>\n<p>You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&amp;D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.</p>\n<p>Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_318fd022-66f"},"title":"Application Engineering, Sr Engineer - ICV Runset Development","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. 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architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.</p>\n<p>With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.</p>\n<p>You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.</p>\n<p>Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.</p>\n<p>You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.</p>\n<p>As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.</p>\n<p>Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.</p>\n<p>You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.</p>\n<p>Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.</p>\n<p>Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</p>\n<p>Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.</p>\n<p>Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.</p>\n<p>Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.</p>\n<p>Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.</p>\n<p>Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.</p>\n<p>Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.</p>\n<p>Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.</p>\n<p>Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.</p>\n<p>Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.</p>\n<p>Contribute to the development of next-generation verification methodologies and best practices within Synopsys.</p>\n<p>Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.</p>\n<p>B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.</p>\n<p>5-8 years of hands-on experience in the Physical Verification (PV) domain.</p>\n<p>Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.</p>\n<p>Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.</p>\n<p>Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.</p>\n<p>Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.</p>\n<p>Exposure to competitive EDA tools and awareness of their strengths and limitations.</p>\n<p>An analytical thinker with strong problem-solving abilities and meticulous attention to detail.</p>\n<p>A collaborative team player who fosters knowledge sharing and mentorship.</p>\n<p>Effective communicator, capable of translating technical concepts to diverse audiences.</p>\n<p>Adaptable and proactive, with a passion for continuous learning and innovation.</p>\n<p>Customer-focused, with a commitment to delivering high-quality solutions on time.</p>\n<p>Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.</p>\n<p>Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.</p>\n<p>Work closely with foundry partners, internal R&amp;D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.</p>\n<p>We offer a comprehensive range of health, wellness, and financial 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design flows, foundry process requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_536b7243-e5c"},"title":"Application Engineering, Staff Engineer - Physical Verification (Runset Development)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.</p>\n<p>You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. 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