Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.

You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

As a member of our high-performing Customer Application Services team, you will collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.

Responsibilities:

• Support customers in enjoying Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge.
• Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).
• Collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.
• Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.
• Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.

Key Qualifications:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),
• Tool knowledge (preferred): STA (Primetime, Tempus)

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

16005

Remote Eligible

No

Date Posted

03/05/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.

What You’ll Be Doing:

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.

• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

• Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.

• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

• Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.

• Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.

The Impact You Will Have:

• Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.

• Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development.

• Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.

• Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.

• Elevate the technical capabilities of the application engineering team through mentorship and cross-training.

• Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.

• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).

• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.

• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.

• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.

• Outstanding verbal and written communication, presentation, and customer interaction skills.

Who You Are:

• Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.

• Analytical thinker with a problem-solving mindset and a passion for continuous improvement.

• Adaptable and resilient in the face of evolving customer requirements and technology landscapes.

• Strong organizational skills, able to manage multiple projects and priorities with poise.

• Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.

The Team You’ll Be A Part Of:

You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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What you'll do

• Creating and optimizing design flows and solutions to meet aggressive PPA targets for high-frequency cores, automotive, and high-capacity AI/compute designs.
• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong understanding of ASIC design flow, VLSI, and CAD development.

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What you'll do

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.
• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 9+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes (like 2nm/3nm/5nm etc).
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.
• Outstanding verbal and written communication, presentation, and customer interaction skills.

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