{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/physical-design"},"x-facet":{"type":"skill","slug":"physical-design","display":"Physical Design","count":30},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f1d798f0-268"},"title":"Applications Engineering, Sr Engineer","description":"<p>Engineer the Future with Us</p>\n<p>We are seeking a proactive, customer-oriented engineer to join our Customer Application Services team. As a Senior Applications Engineer, you will be responsible for managing and providing ICV runset support for key foundry customers, ensuring optimal product performance and customer satisfaction.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Manage and provide ICV runset support for key foundry customers, ensuring optimal product performance and customer satisfaction.</li>\n<li>Deliver post-sales technical expertise during the runset programming, implementation, and maintenance of Synopsys products.</li>\n<li>Implement detailed customer installation requirements and customize solutions to fit unique client environments.</li>\n<li>Ensure client needs are met and that Synopsys solutions function according to technical specifications and industry standards.</li>\n<li>Collaborate with sales teams to provide pre-sales technical support, contributing to successful business development and customer onboarding.</li>\n<li>Troubleshoot and resolve moderately complex technical issues.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Basic understanding of the design process, with a preference for Design Rule Checking (DRC).</li>\n<li>Solid grasp of ASIC design flow, VLSI concepts, and/or CAD engineering principles.</li>\n<li>Familiarity with competitive EDA tool products and expertise in areas such as Verification, Place and Route, Design Reuse, and/or Physical Design.</li>\n<li>Ability to manage projects from initiation through completion, delivering high-quality technical solutions.</li>\n<li>Creative problem-solving skills and the ability to exercise judgment in selecting methods and techniques to obtain solutions.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You will join the Customer Application Services team, a group of passionate engineers dedicated to delivering technical excellence and customer success. The team works closely with foundries, design teams, and sales professionals, providing deep expertise and support throughout the product lifecycle.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f1d798f0-268","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/applications-engineering-sr-engineer/44408/92631659472","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC design flow","VLSI concepts","CAD engineering principles","EDA tool products","Verification","Place and Route","Design Reuse","Physical Design"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:22.191Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design flow, VLSI concepts, CAD engineering principles, EDA tool products, Verification, Place and Route, Design Reuse, Physical Design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5110661a-564"},"title":"Solutions Engineering, Staff Engineer","description":"<p>We are seeking an experienced Solutions Engineer to join our team in Bhubaneswar, India. As a Staff Engineer, you will be responsible for post-silicon debug activities, enabling Product Requirement Documents (PRDs), working to enable IP as a product development platform, handling hands-on post-silicon test setups, collaborating on top-level physical design, board-level, and package-level designs, developing post-silicon reports, and conducting debug analysis.</p>\n<p>The successful candidate will have hands-on experience in post-silicon test setups, sound knowledge of Digital/AMS chip design and post-silicon debug, a BS or MS degree in Electrical Engineering with 3+ years of experience, understanding of top-level physical design, board-level, and package-level designs, and expertise in RTL development and physical design.</p>\n<p>As a member of our rapidly expanding PVT IP group, you will collaborate with a group of innovative and highly skilled professionals to drive the future of technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5110661a-564","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bhubaneswar/solutions-engineering-staff-engineer/44408/92910391056","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["post-silicon test setups","Digital/AMS chip design","RTL development","physical design"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:28.996Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bhubaneswar"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"post-silicon test setups, Digital/AMS chip design, RTL development, physical design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3511e871-def"},"title":"Application Engineering, Staff Engineer","description":"<p>We&#39;re seeking an expert in static timing analysis to join our applications engineering team. As a Staff Engineer, you will be responsible for supporting the industry-leading Synopsys PrimeTime Static Timing Analysis tool across pre-sale and post-sale engagements.</p>\n<p>Your key responsibilities will include driving product adoption through competitive benchmarking, customer evaluations, and articulating product advantages to design teams and management. You will also deliver customer training, technical presentations, and hands-on workshops to maximize user proficiency and satisfaction.</p>\n<p>In addition, you will provide tape-out support, troubleshoot complex timing issues, and ensure successful project completion. You will collaborate with R&amp;D, marketing, and sales to relay customer feedback and influence product enhancements.</p>\n<p>To succeed in this role, you will need expertise in Synopsys PrimeTime STA tool, with hands-on experience and deep knowledge of its features. You will also require strong understanding of timing corners, process variations, and signal integrity-related issues.</p>\n<p>If you are a collaborative team player who values diverse perspectives and fosters inclusive environments, we encourage you to apply.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3511e871-def","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/application-engineering-staff-engineer/44408/92918452480","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Synopsys PrimeTime STA tool","Timing corners","Process variations","Signal integrity-related issues","TCL scripting","Physical design","Extraction","ECO methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:10.521Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Synopsys PrimeTime STA tool, Timing corners, Process variations, Signal integrity-related issues, TCL scripting, Physical design, Extraction, ECO methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8868aa47-ecb"},"title":"Solutions Engineering, Staff Engineer","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>We are seeking an experienced and highly motivated individual with a passion for technology and innovation. You will serve as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs) and working to enable IP as a product development platform. You will handle hands-on post-silicon test setups, collaborate on top-level physical design, board-level, and package-level designs, and develop post-silicon reports and conduct debug analysis.</p>\n<p>The successful candidate will drive the successful development and deployment of PVT IP sensors, enhance the reliability and performance of Synopsys&#39; silicon lifecycle monitoring solutions, ensure high-quality product development through meticulous testing and debugging, and contribute to the continuous innovation in chip design and software security.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Serving as the single point of contact for post-silicon debug activities</li>\n<li>Enabling Product Requirement Documents (PRDs)</li>\n<li>Working to enable IP as a product development platform</li>\n<li>Handling hands-on post-silicon test setups</li>\n<li>Collaborating on top-level physical design, board-level, and package-level designs</li>\n<li>Developing post-silicon reports and conducting debug analysis</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Hands-on experience in post-silicon test setups</li>\n<li>Sound knowledge of Digital/AMS chip design and post-silicon debug</li>\n<li>BS or MS degree in Electrical Engineering with 3+ years of experience</li>\n<li>Understanding of top-level physical design, board-level, and package-level designs</li>\n<li>Expertise in RTL development and physical design</li>\n</ul>\n<p>The ideal candidate will be a strong communicator with excellent teamwork and interpersonal skills, detail-oriented with a mindset geared towards IP debug and documentation, proactive learner with the ability to adapt to new IP functionalities, effective leader with strong people management skills, and highly motivated and capable of mentoring both internal teams and external customers.</p>\n<p>You will be part of the rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. This team is dedicated to conceptualizing, designing, and productizing state-of-the-art sensors that play a critical role in the silicon lifecycle monitoring process. Collaborate with a group of innovative and highly skilled professionals to drive the future of technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8868aa47-ecb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bhubaneswar/solutions-engineering-staff-engineer/44408/93159885488","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL development","physical design","post-silicon debug","Digital/AMS chip design","top-level physical design","board-level design","package-level design"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:07.011Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bhubaneswar"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL development, physical design, post-silicon debug, Digital/AMS chip design, top-level physical design, board-level design, package-level design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_17454de9-f23"},"title":"Applications Engineering, Staff Engineer_ICV","description":"<p>Engineer the Future with Us</p>\n<p>We currently have 614 open roles</p>\n<p><strong>Innovation Starts Here</strong></p>\n<p>Find Jobs For</p>\n<p>Where?When autocomplete results are available use up and down arrows to review and enter to select. Touch device users, explore by touch or with swipe gestures.</p>\n<p><strong>Applications Engineering, Staff Engineer_ICV</strong></p>\n<p>Hsinchu, Taiwan</p>\n<p>Save</p>\n<p>Category: EngineeringHire Type: Employee</p>\n<p><strong>Job ID</strong> 16575<strong>Date posted</strong> 03/23/2026</p>\n<p><strong><strong>We Are:</strong></strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong><strong>You Are:</strong></strong></p>\n<p>You are a highly skilled and passionate engineer, eager to make a tangible impact on the semiconductor industry by leveraging your expertise in design flows and customer applications. You thrive in collaborative and fast-paced environments, bringing both technical depth and adaptability to every challenge. Your ability to communicate complex ideas clearly to both technical and non-technical stakeholders makes you a trusted advisor and partner. You are committed to delivering exceptional customer experiences, always seeking innovative solutions that address client needs and drive success.</p>\n<p>With a solid foundation in ASIC design, VLSI, and CAD engineering, you continuously expand your knowledge to stay ahead of industry trends. You possess a keen analytical mind, capable of troubleshooting and resolving intricate issues efficiently. Your creative problem-solving skills and meticulous attention to detail ensure that projects are executed flawlessly from conception through completion. You enjoy mentoring others and contributing to moderately complex aspects of projects, enhancing team performance.</p>\n<p>You embrace diversity, respect different perspectives, and believe in the power of inclusion to foster innovation. Your dedication, resilience, and positive attitude enable you to thrive in dynamic environments, and you’re motivated by the opportunity to support key foundry customers and help shape the future of electronic design automation. If you’re ready to elevate your career and make a difference, Synopsys is the place for you.</p>\n<p><strong><strong>What You’ll Be Doing:</strong></strong></p>\n<ul>\n<li>Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.</li>\n</ul>\n<ul>\n<li>Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.</li>\n</ul>\n<ul>\n<li>Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.</li>\n</ul>\n<ul>\n<li>Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.</li>\n</ul>\n<ul>\n<li>Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.</li>\n</ul>\n<ul>\n<li>Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.</li>\n</ul>\n<p><strong><strong>The Impact You Will Have:</strong></strong></p>\n<ul>\n<li>Enhancing customer satisfaction by delivering tailored, high-quality technical solutions and ongoing support.</li>\n</ul>\n<ul>\n<li>Driving successful adoption of Synopsys products within key foundries, solidifying long-term partnerships and business growth.</li>\n</ul>\n<ul>\n<li>Contributing to the continuous improvement of runset programming and installation processes, raising industry standards.</li>\n</ul>\n<ul>\n<li>Supporting the sales team with technical insights, helping to win new business and expand Synopsys’s market reach.</li>\n</ul>\n<ul>\n<li>Identifying opportunities for innovation and improvement in EDA tools, directly influencing product development and competitiveness.</li>\n</ul>\n<ul>\n<li>Mentoring junior team members and sharing best practices, fostering a collaborative and high-performing work environment.</li>\n</ul>\n<p><strong><strong>What You’ll Need:</strong></strong></p>\n<ul>\n<li>Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.</li>\n</ul>\n<ul>\n<li>Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.</li>\n</ul>\n<ul>\n<li>Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.</li>\n</ul>\n<ul>\n<li>Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to manage projects from start to completion, contributing to moderately complex aspects of technical initiatives.</li>\n</ul>\n<p><strong><strong>Who You Are:</strong></strong></p>\n<ul>\n<li>Creative and resourceful problem solver, able to think outside the box and address challenges proactively.</li>\n</ul>\n<ul>\n<li>Judicious decision-maker, skilled in selecting effective methods and techniques for optimal solutions.</li>\n</ul>\n<ul>\n<li>Collaborative team player with a strong sense of ownership and accountability.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient, comfortable navigating evolving priorities and customer requirements.</li>\n</ul>\n<ul>\n<li>Inclusive and respectful, valuing diverse perspectives and fostering a positive team culture.</li>\n</ul>\n<p><strong><strong>The Team You’ll Be A Part Of:</strong></strong></p>\n<p>You’ll join a dynamic Customer Application Services team based in Taiwan, dedicated to supporting key foundry partners and advancing Synopsys’s leadership in EDA solutions. The team is composed of experienced engineers and technical experts who collaborate closely with customers, sales, and product development groups. Together, you’ll tackle complex challenges, drive innovation, and ensure the successful implementation of industry-leading design automation tools.</p>\n<p><strong><strong>Rewards and Benefits:</strong></strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_17454de9-f23","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-icv/44408/93175106624","x-work-arrangement":null,"x-experience-level":"Staff","x-job-type":"Employee","x-salary-range":null,"x-skills-required":["ASIC design","VLSI","CAD engineering","EDA tool products","verification","place and route","design reuse","physical design"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:06.954Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design, VLSI, CAD engineering, EDA tool products, verification, place and route, design reuse, physical design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_223485dd-7d5"},"title":"Applications Engineering, Sr Engineer","description":"<p>Engineer the Future with Us</p>\n<p>We currently have 614 open roles</p>\n<p><strong>Innovation Starts Here</strong></p>\n<p>Find Jobs For</p>\n<p>Where?When autocomplete results are available use up and down arrows to review and enter to select. Touch device users, explore by touch or with swipe gestures.</p>\n<p><strong>Applications Engineering, Sr Engineer</strong></p>\n<p>Hsinchu, Taiwan</p>\n<p>Save</p>\n<p>Category: EngineeringHire Type: Employee</p>\n<p><strong>Job ID</strong> 15949<strong>Date posted</strong> 03/08/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a proactive, customer-oriented engineer passionate about advancing semiconductor technologies. You thrive in fast-paced environments and are eager to solve complex technical challenges, collaborating with leading foundries and design teams. You possess a strong foundation in ASIC design flow, VLSI, and CAD engineering, and are comfortable navigating the intricacies of EDA tools and physical design. Your communication skills enable you to build trust with customers, translating their needs into actionable solutions and ensuring seamless product implementation. You are resourceful, adaptable, and able to exercise sound judgment while tackling technical issues. Your creative approach to problem-solving and drive for excellence enable you to contribute meaningfully to both individual projects and broader team initiatives. You value diversity and inclusivity, and you are committed to continuous learning, staying current with industry trends and emerging technologies. By joining Synopsys, you seek to make a tangible impact on the future of high-performance silicon, and you are motivated by opportunities to grow, innovate, and collaborate in a global, supportive environment.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Managing and providing ICV runset support for key foundry customers, ensuring optimal product performance and customer satisfaction.</li>\n</ul>\n<ul>\n<li>Delivering post-sales technical expertise during the runset programming, implementation, and maintenance of Synopsys products.</li>\n</ul>\n<ul>\n<li>Implementing detailed customer installation requirements and customizing solutions to fit unique client environments.</li>\n</ul>\n<ul>\n<li>Ensuring client needs are met and that Synopsys solutions function according to technical specifications and industry standards.</li>\n</ul>\n<ul>\n<li>Collaborating with sales teams to provide pre-sales technical support, contributing to successful business development and customer onboarding.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving moderately complex technical issues</li>\n</ul>\n<ul>\n<li>Empowering customers to efficiently deploy and maximize the value of Synopsys EDA solutions in their design workflows.</li>\n</ul>\n<ul>\n<li>Enhancing customer satisfaction and strengthening long-term partnerships with key foundry clients.</li>\n</ul>\n<ul>\n<li>Driving successful product adoptions and implementations, contributing directly to Synopsys’ market leadership.</li>\n</ul>\n<ul>\n<li>Supporting the technical excellence of customer projects, enabling innovative chip design and verification outcomes.</li>\n</ul>\n<ul>\n<li>Facilitating knowledge transfer, helping customers understand and leverage advanced product features.</li>\n</ul>\n<ul>\n<li>Identifying opportunities for product improvements and feeding insights back to development teams for continuous innovation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Basic understanding of the design process, with a preference for Design Rule Checking (DRC).</li>\n</ul>\n<ul>\n<li>Solid grasp of ASIC design flow, VLSI concepts, and/or CAD engineering principles.</li>\n</ul>\n<ul>\n<li>Familiarity with competitive EDA tool products and expertise in areas such as Verification, Place and Route, Design Reuse, and/or Physical Design.</li>\n</ul>\n<ul>\n<li>Ability to manage projects from initiation through completion, delivering high-quality technical solutions.</li>\n</ul>\n<ul>\n<li>Creative problem-solving skills and the ability to exercise judgment in selecting methods and techniques to obtain solutions.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and effective communicator, able to build strong relationships with customers and internal teams.</li>\n</ul>\n<ul>\n<li>Resourceful and adaptable, thriving in dynamic, fast-paced environments.</li>\n</ul>\n<ul>\n<li>Detail-oriented with strong analytical skills and a commitment to delivering exceptional results.</li>\n</ul>\n<ul>\n<li>Open-minded and inclusive, embracing diverse perspectives and fostering an environment of belonging.</li>\n</ul>\n<ul>\n<li>Self-motivated and eager to learn, continuously seeking opportunities for growth and innovation.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the Customer Application Services team, a group of passionate engineers dedicated to delivering technical excellence and customer success. The team works closely with foundries, design teams, and sales professionals, providing deep expertise and support throughout the product lifecycle. You’ll collaborate in a culture of innovation, knowledge sharing, and mutual respect, where every member’s contribution is valued and celebrated.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_223485dd-7d5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/applications-engineering-sr-engineer/44408/92631659424","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC design flow","VLSI","CAD engineering","EDA tools","Physical design","Verification","Place and Route","Design Reuse"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:55.695Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design flow, VLSI, CAD engineering, EDA tools, Physical design, Verification, Place and Route, Design Reuse"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_db86d9ed-ba4"},"title":"R&D Engineering, Sr Architect","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>You Are:</p>\n<p>You are an accomplished R&amp;D Engineer with a passion for advanced packaging, auto routing, and physical design automation. Your strong programming skills and experience in EDA software development set you apart. You thrive in a dynamic environment and are always looking for innovative ways to push the boundaries of technology. You enjoy collaborating with cross-functional teams and have a knack for translating complex technical concepts into actionable solutions. Your expertise in physical design routing solutions, coupled with your ability to work with minimal oversight, makes you a key player in driving strategic goals. Your communication skills allow you to effectively influence both internal and external stakeholders, ensuring the successful implementation of cutting-edge solutions.</p>\n<p>What You’ll Be Doing:</p>\n<p>Leading R&amp;D projects focused on advanced packaging, auto routing, and physical design automation\nDeveloping and optimizing EDA software tools to enhance design efficiency\nCollaborating with cross-functional teams to integrate innovative solutions into existing workflows\nConducting research to identify new methodologies in chip design and verification\nProviding technical guidance and mentorship to junior team members\nPresenting findings and recommendations to senior management and stakeholders</p>\n<p>The Impact You Will Have:</p>\n<p>Driving innovations in advanced packaging and physical design automation\nEnhancing the efficiency and effectiveness of EDA software tools\nContributing to the development of high-performance silicon chips\nInfluencing the strategic direction of R&amp;D initiatives\nMentoring the next generation of engineers and fostering a culture of continuous learning\nStrengthening Synopsys’ position as a leader in the semiconductor industry</p>\n<p>What You’ll Need:</p>\n<p>15+ years of relevant experience\nStrong programming skills in languages such as C++, Python, or Java\nExtensive experience in EDA software development and computational geometry\nDeep understanding of advanced packaging and physical design methodologies\nProven track record of leading successful R&amp;D projects\nExcellent problem-solving and analytical abilities\nDemonstrated skills in computational geometry and design rule checking</p>\n<p>Who You Are:</p>\n<p>Innovative thinker with a passion for technology\nEffective communicator with strong interpersonal skills\nCollaborative team player who thrives in a dynamic environment\nDetail-oriented and committed to excellence\nAdaptable and open to new challenges</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll be joining a team of dedicated professionals focused on pushing the limits of what’s possible in chip design and verification. Our team values collaboration, creativity, and continuous improvement. Together, we strive to develop solutions that meet the evolving needs of the semiconductor industry and drive technological advancements.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness\nComprehensive medical and healthcare plans that work for you and your family.</li>\n<li>Time Away\nIn addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Family Support\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>ESPP\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Retirement Plans\nSave for your future with our retirement plans that vary by region and country.</li>\n<li>Compensation\nCompetitive salaries.</li>\n</ul>\n<p>Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_db86d9ed-ba4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/united-states/r-and-d-engineering-sr-architect/44408/92965324672","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$196000-$294000","x-skills-required":["C++","Python","Java","EDA software development","Computational geometry","Physical design routing solutions"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:44.833Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C++, Python, Java, EDA software development, Computational geometry, Physical design routing solutions","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":196000,"maxValue":294000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ae9d1be9-0e5"},"title":"Senior Staff Engineer - Solutions Engineering","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>We are seeking a Senior Staff Engineer - Solutions Engineering to join our team. As a Senior Staff Engineer, you will be responsible for serving as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs), working to enable IP as a product development platform, handling hands-on post-silicon test setups, collaborating on top-level physical design, board-level, and package-level designs, developing post-silicon reports, and conducting debug analysis.</p>\n<p>The successful candidate will have hands-on experience in post-silicon test setups, sound knowledge of Digital/AMS chip design and post-silicon debug, a BS or MS degree in Electrical Engineering with 6+ years of experience, understanding of top-level physical design, board-level, and package-level designs, and expertise in RTL development and physical design.</p>\n<p>As a Senior Staff Engineer, you will be part of the rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. This team is dedicated to conceptualizing, designing, and productizing state-of-the-art sensors that play a critical role in the silicon lifecycle monitoring process. Collaborate with a group of innovative and highly skilled professionals to drive the future of technology.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ae9d1be9-0e5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/plymouth/senior-staff-engineer-solutions-engineering/44408/92898575488","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL development","physical design","post-silicon debug","Digital/AMS chip design","top-level physical design","board-level design","package-level design"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:41.336Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Plymouth"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL development, physical design, post-silicon debug, Digital/AMS chip design, top-level physical design, board-level design, package-level design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bbadef47-3f6"},"title":"Solutions Engineering, Staff Engineer","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are an experienced and highly motivated individual with a passion for technology and innovation. You have a strong technical background in RTL, Physical Design, and post-silicon test and testability development. Your expertise in debugging and developing Process, Voltage, Temperature, Current, and Droop sensors is unparalleled. You thrive in a dynamic environment and excel in communication, teamwork, and leadership.</p>\n<p>As a Staff Engineer in our PVT IP group, you will be responsible for driving the successful development and deployment of PVT IP sensors. You will enhance the reliability and performance of Synopsys&#39; silicon lifecycle monitoring solutions, ensure high-quality product development through meticulous testing and debugging, and contribute to the continuous innovation in chip design and software security.</p>\n<p>Key responsibilities include serving as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs), working to enable IP as a product development platform, handling hands-on post-silicon test setups, collaborating on top-level physical design, board-level, and package-level designs, developing post-silicon reports, and conducting debug analysis.</p>\n<p>To succeed in this role, you will need hands-on experience in post-silicon test setups, sound knowledge of Digital/AMS chip design and post-silicon debug, a BS or MS degree in Electrical Engineering with 3+ years of experience, understanding of top-level physical design, board-level, and package-level designs, and expertise in RTL development and physical design.</p>\n<p>You will be part of a rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. This team is dedicated to conceptualizing, designing, and productizing state-of-the-art sensors that play a critical role in the silicon lifecycle monitoring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bbadef47-3f6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bhubaneswar/solutions-engineering-staff-engineer/44408/93159885424","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL development","Physical Design","Post-silicon test and testability development","Process, Voltage, Temperature, Current, and Droop sensors","Digital/AMS chip design","Post-silicon debug"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:04.520Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bhubaneswar"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL development, Physical Design, Post-silicon test and testability development, Process, Voltage, Temperature, Current, and Droop sensors, Digital/AMS chip design, Post-silicon debug"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f1a00bea-138"},"title":"R&D Engineering, Staff Engineer (EDA, GPU Acceleration)","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are an accomplished engineering leader with over 3-6 years of experience in developing large-scale applications, particularly within the EDA domain. Your expertise spans the entire lifecycle of solution development,from initial specification to hands-on implementation, customer engagement, and iterative refinement. You thrive in environments that demand both deep technical prowess and strong leadership, and you are passionate about mentoring the next generation of engineers. Your background in C/C++ development is robust, and you approach new languages and technologies with curiosity and adaptability, making you an ideal fit for our dynamic team. You having experience with CUDA, GPU acceleration and GPU architecture knowledge is plus.</p>\n<p>What You’ll Be Doing:</p>\n<p>Enabling GPU Acceleration for Fusion Compiler entire R2G flow. This includes GPU acceleration of each of the engine in R2G flow with new problem formulation to take advantage of GPU architectures. These engines include placement, global routing, detail routing, CTS, optimization, timer, extraction, legalizer and synthesis.</p>\n<p>Owning projects end-to-end,from requirements gathering and design specification to development, testing, and customer interaction,ensuring high-quality deliverables.</p>\n<p>Collaborating closely with cross-functional teams, including product management and product engineering.</p>\n<p>The Impact You Will Have:</p>\n<p>Delivering  GPU Accelerated Fusion Compiler, which will be game changing for chip design and implementation steps by reducing flow cycle times from weeks to days (or hours).</p>\n<p>Empowering Synopsys customers to achieve faster turn around time and accelerating their design cycles and reducing time to market.</p>\n<p>Elevating the technical excellence of the team by sharing best practices, fostering a culture of learning, and mentoring future leaders.</p>\n<p>Shaping the roadmap for Digital Implementation solutions, ensuring that Synopsys remains at the forefront of EDA technology.</p>\n<p>What You’ll Need:</p>\n<p>Minimum 3-6 years of hands-on experience in developing software projects, preferably in EDA or semiconductor domains.</p>\n<p>Expert proficiency in C/C++ development, with a proven track record of delivering robust, scalable solutions.</p>\n<p>Experience with physical design, placement, and routing flows in EDA tools.</p>\n<p>Experience with CUDA, GPU acceleration and GPU architecture knowledge is plus.</p>\n<p>Strong knowledge of software architecture, Design Thinking, and use of design patterns.</p>\n<p>Excellent communication skills for technical interactions.</p>\n<p>Who You Are:</p>\n<p>Innovative thinker who embraces new technologies and methodologies.</p>\n<p>Strong problem solver with a strategic mindset and attention to detail.</p>\n<p>Effective communicator, able to translate complex technical concepts for diverse audiences.</p>\n<p>Collaborative team player, eager to contribute and learn from others.</p>\n<p>Adaptable and resilient in the face of evolving challenges and requirements.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join the Fusion Compiler GPU Acceleration team in Synopsys Sunnyvale, CA (or Hillsboro, OR), a group of passionate engineers focused on developing industry-first and game changing GPU Accelerated Digital Implementation solution. This development is part of Nvidia/Synopsys GPU Acceleration collaboration. This team  is driving innovation in EDA and empowering customers worldwide by accelerating their design cycles and reducing time to market.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f1a00bea-138","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-staff-engineer-eda-gpu-acceleration/44408/93189758192","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":"$138000-$207000","x-skills-required":["C/C++ development","CUDA","GPU acceleration","GPU architecture knowledge","Physical design","Placement","Routing flows","Software architecture","Design Thinking","Use of design patterns"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:37.265Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C/C++ development, CUDA, GPU acceleration, GPU architecture knowledge, Physical design, Placement, Routing flows, Software architecture, Design Thinking, Use of design patterns","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":138000,"maxValue":207000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8bcaf6b7-774"},"title":"ASIC Digital Design, Senior Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p><strong>Responsibilities:</strong></p>\n<p>Define and develop ASIC RTL design and verification at both chip level and block level. Collaborate with cross-functional teams to design, implement, and verify PCIe interfaces. Perform RTL coding, synthesis, and simulation to ensure design functionality and performance. Conduct design reviews and provide technical guidance to junior engineers. Work closely with physical design teams to ensure seamless integration and optimization. Debug and resolve design issues to ensure timely delivery of high-quality products.</p>\n<p><strong>Impact:</strong></p>\n<p>Contribute to the development of high-performance silicon chips that power next-generation technologies. Enhance the functionality and performance of Synopsys&#39; PCIe solutions. Drive innovation and improve design methodologies within the team. Ensure the successful delivery of complex ASIC projects on time and within budget. Mentor and guide junior engineers, fostering a culture of continuous learning and development. Collaborate with cross-functional teams to deliver integrated and optimized solutions for our customers.</p>\n<p><strong>Requirements:</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, or a related field. Extensive experience in ASIC digital design and verification. Strong knowledge of PCIe protocols and interfaces. Proficiency in RTL coding (Verilog/SystemVerilog) and simulation tools. Experience with synthesis, timing analysis, and formal verification.</p>\n<p><strong>Team:</strong></p>\n<p>Join a dynamic and collaborative team of engineers dedicated to designing and delivering high-performance silicon solutions. Our team focuses on innovation, quality, and continuous improvement, working together to solve complex technical challenges and deliver industry-leading products.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8bcaf6b7-774","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/austin/asic-digital-design-senior-staff-engineer/44408/93286401456","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$138000-$208000","x-skills-required":["ASIC digital design","RTL coding","simulation tools","synthesis","timing analysis","formal verification","PCIe protocols","interfaces"],"x-skills-preferred":["chip architecture","circuit design","verification","physical design"],"datePosted":"2026-04-05T13:19:02.864Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital design, RTL coding, simulation tools, synthesis, timing analysis, formal verification, PCIe protocols, interfaces, chip architecture, circuit design, verification, physical design","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":138000,"maxValue":208000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5be91f86-bf9"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</p>\n<p>You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</p>\n<p>You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.</p>\n<p>You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.</p>\n<p>You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.</p>\n<p>You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.</p>\n<p>You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.</p>\n<p>You will mentor junior engineers and contribute to team knowledge sharing initiatives.</p>\n<p><strong>Impact</strong></p>\n<p>You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.</p>\n<p>You will advance Synopsys&#39; leadership in IP implementation at cutting-edge technology nodes.</p>\n<p>You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.</p>\n<p>You will facilitate seamless cross-site collaboration, ensuring global project success.</p>\n<p>You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.</p>\n<p>You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electronics, Electrical Engineering, or related field.</p>\n<p>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</p>\n<p>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</p>\n<p>Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.</p>\n<p>Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.</p>\n<p>Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.</p>\n<p>Strong analytical and debugging skills for addressing complex design challenges.</p>\n<p><strong>Team</strong></p>\n<p>You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.</p>\n<p>The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.</p>\n<p>Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5be91f86-bf9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IP implementation","Timing closure","Clock tree synthesis","Skew balancing","Mixed-signal IP integration","Scripting languages (Tcl, Perl, Python)","Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:24.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IP implementation, Timing closure, Clock tree synthesis, Skew balancing, Mixed-signal IP integration, Scripting languages (Tcl, Perl, Python), Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1d6b52c9-024"},"title":"Principal Engineer","description":"<p>As a Principal Engineer at Synopsys, you will be responsible for driving end-to-end SOC development, from architectural definition through post-silicon validation and customer delivery. You will provide technical leadership and mentorship to teams of micro-architects, RTL developers, and cross-functional partners. You will engage directly with customers, addressing their unique needs and delivering solutions tailored to their requirements.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Managing the full SOC development lifecycle, including micro-architecture, RTL design, verification, DFT, physical design, and tapeout management.</li>\n<li>Collaborating with partners on software, firmware, and packaged part solutions, ensuring seamless integration and delivery.</li>\n<li>Occasionally traveling and working on-site at customer premises to support project execution and strengthen customer relationships.</li>\n</ul>\n<p>As a Principal Engineer, you will shape Synopsys&#39; role as a trusted partner for advanced SOC design across multiple industries, including automotive, aerospace, and high-performance computing. You will advance the adoption of cutting-edge technologies and design methodologies in customer projects. You will mentor and develop engineering talent, fostering technical excellence and innovation within the team.</p>\n<p>To succeed in this role, you will need:</p>\n<ul>\n<li>BSEE, MSEE, or Ph.D. in Electrical and/or Computer Engineering.</li>\n<li>Minimum 10 years of experience in SOC-level architecture and RTL development.</li>\n<li>Proficiency in SOC system architecture, micro-architecture, RTL development, design verification, DFT, and tapeout management.</li>\n<li>Expertise in high-performance computing architectures for mobile, data center, automotive, and edge computing SOCs.</li>\n<li>In-depth knowledge of interconnect options (Arteris NOC, AMBA AXI, CXL, etc.) and SOC standard interfaces (PCIe, DDR, HBM, MIPI CSI/DSI, SPI, I2C).</li>\n<li>Implementation experience with CPU architectures (RISCV, ARC, X86, ARM).</li>\n<li>Hands-on experience with workflow tools (git, gitlab, github).</li>\n<li>Ability to travel and work on-site as needed; eligibility for government security clearances is a plus.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1d6b52c9-024","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/tokyo/soc-engineering-principal-engineer/44408/92568976576","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SOC system architecture","micro-architecture","RTL development","design verification","DFT","physical design","tapeout management","high-performance computing architectures","interconnect options","SOC standard interfaces","CPU architectures","workflow tools"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:10:43.521Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Tokyo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SOC system architecture, micro-architecture, RTL development, design verification, DFT, physical design, tapeout management, high-performance computing architectures, interconnect options, SOC standard interfaces, CPU architectures, workflow tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1760e65e-8ff"},"title":"Applications Engineering Architect (PPA)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a proactive, results-driven leader with a deep technical background in physical design and processor implementation. Your expertise is grounded in architecting high-performance, energy-efficient silicon solutions, and you thrive in fast-paced, collaborative environments. You possess a strong sense of ownership and are comfortable navigating ambiguity to deliver innovative solutions to complex engineering challenges.</p>\n<p>As an Applications Engineering Architect (PPA), you will be responsible for architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems, targeting aggressive power and performance goals for diverse end-user applications. You will develop and refine advanced EDA tools and design methodologies to support state-of-the-art processor implementations.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems</li>\n<li>Developing and refining advanced EDA tools and design methodologies</li>\n<li>Collaborating closely with key Synopsys customers to guide their development of processor-based platforms in advanced silicon technologies</li>\n<li>Partnering with Synopsys R&amp;D and marketing teams to influence and define future product roadmaps and features</li>\n<li>Working in synergy with leading IP partners to ensure seamless integration of EDA tools, methodologies, and IP</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Proven expertise in physical design and implementation of high-performance processors, SoCs, or processor-based subsystems</li>\n<li>In-depth experience with advanced EDA tools, flows, and methodologies for digital implementation</li>\n<li>Strong knowledge of silicon technologies at advanced nodes and associated design challenges</li>\n<li>Hands-on experience integrating IP and collaborating with IP vendors for seamless tool and methodology interoperability</li>\n<li>Track record of working directly with customers, understanding their requirements, and delivering tailored solutions</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off. We also provide opportunities for professional growth and development, including training and education programs, mentorship, and career advancement opportunities.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1760e65e-8ff","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-architect-ppa/44408/92048243568","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","processor implementation","EDA tools","digital implementation","silicon technologies","IP integration"],"x-skills-preferred":["Python","Tcl","Perl","power/performance/area trade-offs","optimization techniques"],"datePosted":"2026-03-09T11:06:19.000Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, processor implementation, EDA tools, digital implementation, silicon technologies, IP integration, Python, Tcl, Perl, power/performance/area trade-offs, optimization techniques"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_84c32509-79a"},"title":"ASIC Physical Design, Principal Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a visionary and seasoned engineering leader, driven by a passion for innovation in ASIC physical design. Seeking a highly motivated and innovative ASIC Physical Design Implementation Engineer to lead the Test Chip PHY development. You will lead a team of engineers to develop Test Chips for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with a focus on digital design.</p>\n<p>What You’ll Be Doing:</p>\n<p>Lead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles.</p>\n<p>Resource &amp; Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution.</p>\n<p>Floor planning &amp; Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture.</p>\n<p>Synthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</p>\n<p>Timing Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff.</p>\n<p>Design Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips.</p>\n<p>Block/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros.</p>\n<p>Tool Flow Enhancements &amp; Debug: Drive tool flow automation and debugging to improve productivity and design reliability.</p>\n<p>Collaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development</p>\n<p>Release &amp; Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists</p>\n<p>What You’ll Need:</p>\n<ul>\n<li>12+ years of proven experience in ASIC physical Design, with expertise in leading complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, LVS/DRC, and related methodologies.</li>\n<li>Demonstrated experience leading engineering teams and managing cross-functional projects in high-pressure environments.</li>\n<li>Familiarity with test chip methodology, IP integration, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as DC, PT, ICC2/FC, ICV, Calibre, RedHawk, and advanced technologies like FinFet.</li>\n<li>Strong communication, problem-solving, and project management skills.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Elevate Synopsys’ leadership in advanced ASIC and IP development by delivering high-performance, reliable test chips.</li>\n<li>Enable rapid validation and integration of DDR/HBM/UCIe protocols, supporting next-generation silicon innovation.</li>\n<li>Enhance cross-functional collaboration, accelerating project timelines and improving overall design quality.</li>\n<li>Drive process improvements through tool flow automation, setting new standards for productivity and design reliability.</li>\n<li>Ensure robust manufacturability and performance, reducing risk and increasing success rates in foundry tape-outs.</li>\n<li>Mentor and develop junior engineers, fostering a culture of technical excellence and continuous learning.</li>\n<li>Contribute to the creation of industry-leading mixed-signal IPs, elevating Synopsys’ portfolio and market position.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Innovative thinker with a passion for solving complex engineering challenges.</li>\n<li>Inspirational leader who empowers teams and fosters collaborative, inclusive environments.</li>\n<li>Meticulous and detail-oriented, committed to quality and design integrity.</li>\n<li>Adaptable and resilient, thriving in fast-paced, dynamic settings.</li>\n<li>Excellent communicator, able to articulate technical concepts to diverse audiences.</li>\n<li>Continuous learner, eager to stay at the forefront of technology and industry trends.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a highly skilled, multidisciplinary team focused on developing industry-leading test chips for cutting-edge protocols like DDR, HBM, and UCIe. The team values collaboration, innovation, and technical excellence, working closely with architecture, RTL, circuit, and verification experts to deliver best-in-class mixed-signal IP solutions. Together, you’ll shape the next generation of silicon technology and drive Synopsys’ continued success in the semiconductor industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>#LI-NK4</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.</p>\n<p>Back to nav</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our 401(k) and 401(k) matching program.</p>\n<ul>\n<li>### Other Benefits</li>\n</ul>\n<p>Flexible work arrangements, employee discounts, and more.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_84c32509-79a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/asic-physical-design-principal-engineer-15046/44408/91661594048","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$170,000-$255,000","x-skills-required":["ASIC physical design","CAD tools","FinFet","IP integration","test chip methodology","verification flows"],"x-skills-preferred":["leadership","project management","communication","problem-solving"],"datePosted":"2026-03-09T11:05:54.042Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough, Massachusetts"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, CAD tools, FinFet, IP integration, test chip methodology, verification flows, leadership, project management, communication, problem-solving","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":170000,"maxValue":255000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4b33752-a69"},"title":"Application Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.</p>\n<p>You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.</p>\n<p>You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.</p>\n<p>You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.</p>\n<p>The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.</p>\n<p>You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&amp;D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys&#39; reputation as a trusted partner and thought leader in the semiconductor industry.</p>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.</li>\n<li>Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).</li>\n<li>Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place &amp; Route, and timing analysis.</li>\n<li>Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.</li>\n<li>Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.</li>\n<li>Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.</li>\n<li>Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent communicator able to build trust and rapport with diverse stakeholders.</li>\n<li>Analytical thinker with strong troubleshooting and debugging skills.</li>\n<li>Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.</li>\n<li>Highly collaborative team player who thrives in fast-paced, multicultural environments.</li>\n<li>Self-motivated, innovative, and passionate about continuous learning and process improvement.</li>\n<li>Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, expert team within the Silicon Design &amp; Verification business at Synopsys, based in Hyderabad. The team is dedicated to driving customer success in high-impact projects, deploying advanced implementation flows, and shaping the future of silicon design. Collaboration, technical excellence, and a commitment to innovation are at the core of our culture. You’ll work closely with customers, R&amp;D, and field teams to deliver transformative solutions and advance industry-leading technologies.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4b33752-a69","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-staff-engineer/44408/92113189648","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Implementation Methodologies","Physical Design","Synopsys tools","RTL to GDS flows","Synthesis","Place & Route","Timing analysis","Scripting (TCL, Python, Unix, Perl)","Automation","Tool integration","Debugging"],"x-skills-preferred":["STA","Low Power Flows","Design Planning","Customer-facing roles"],"datePosted":"2026-03-09T11:05:14.988Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Implementation Methodologies, Physical Design, Synopsys tools, RTL to GDS flows, Synthesis, Place & Route, Timing analysis, Scripting (TCL, Python, Unix, Perl), Automation, Tool integration, Debugging, STA, Low Power Flows, Design Planning, Customer-facing roles"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4ed1875c-bd2"},"title":"Physical Design Lead (With STA & Timing Constraints Expertise)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</li>\n<li>Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.</li>\n<li>Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.</li>\n<li>Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power &amp; IR drop signoff to debug and resolve critical implementation bottlenecks.</li>\n<li>Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.</li>\n<li>Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock &amp; reset architecture improvements for enabling high speed timing closure, PPA improvements.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4ed1875c-bd2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/physical-design-lead-with-sta-and-timing-constraints-expertise-13350/44408/88575081136","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$209000-$313000","x-skills-required":["Physical Design","STA","Timing Constraints","RTL-GDSII","Synopsys tools","Scripting","Software skills"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:03:38.501Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, STA, Timing Constraints, RTL-GDSII, Synopsys tools, Scripting, Software skills","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":209000,"maxValue":313000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bb3c37e2-6df"},"title":"Applications Engineering, Sr Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category: Engineering</strong></p>\n<p><strong>Hire Type: Employee</strong></p>\n<p><strong>Job ID: 15559</strong></p>\n<p><strong>Remote Eligible: No</strong></p>\n<p><strong>Date Posted: 02/28/2026</strong></p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a highly skilled and passionate engineer, eager to make a tangible impact on the semiconductor industry by leveraging your expertise in design flows and customer applications. You thrive in collaborative and fast-paced environments, bringing both technical depth and adaptability to every challenge. Your ability to communicate complex ideas clearly to both technical and non-technical stakeholders makes you a trusted advisor and partner. You are committed to delivering exceptional customer experiences, always seeking innovative solutions that address client needs and drive success.</p>\n<p>With a solid foundation in ASIC design, VLSI, and CAD engineering, you continuously expand your knowledge to stay ahead of industry trends. You possess a keen analytical mind, capable of troubleshooting and resolving intricate issues efficiently. Your creative problem-solving skills and meticulous attention to detail ensure that projects are executed flawlessly from conception through completion. You enjoy mentoring others and contributing to moderately complex aspects of projects, enhancing team performance.</p>\n<p>You embrace diversity, respect different perspectives, and believe in the power of inclusion to foster innovation. Your dedication, resilience, and positive attitude enable you to thrive in dynamic environments, and you’re motivated by the opportunity to support key foundry customers and help shape the future of electronic design automation. If you’re ready to elevate your career and make a difference, Synopsys is the place for you.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.</li>\n</ul>\n<ul>\n<li>Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.</li>\n</ul>\n<ul>\n<li>Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.</li>\n</ul>\n<ul>\n<li>Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.</li>\n</ul>\n<ul>\n<li>Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.</li>\n</ul>\n<ul>\n<li>Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhancing customer satisfaction by delivering tailored, high-quality technical solutions and ongoing support.</li>\n</ul>\n<ul>\n<li>Driving successful adoption of Synopsys products within key foundries, solidifying long-term partnerships and business growth.</li>\n</ul>\n<ul>\n<li>Contributing to the continuous improvement of runset programming and installation processes, raising industry standards.</li>\n</ul>\n<ul>\n<li>Supporting the sales team with technical insights, helping to win new business and expand Synopsys’s market reach.</li>\n</ul>\n<ul>\n<li>Identifying opportunities for innovation and improvement in EDA tools, directly influencing product development and competitiveness.</li>\n</ul>\n<ul>\n<li>Mentoring junior team members and sharing best practices, fostering a collaborative and high-performing work environment.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.</li>\n</ul>\n<ul>\n<li>Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.</li>\n</ul>\n<ul>\n<li>Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.</li>\n</ul>\n<ul>\n<li>Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to manage projects from start to completion, contributing to moderately complex aspects of technical initiatives.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Creative and resourceful problem solver, able to think outside the box and address challenges proactively.</li>\n</ul>\n<ul>\n<li>Judicious decision-maker, skilled in selecting effective methods and techniques for optimal solutions.</li>\n</ul>\n<ul>\n<li>Collaborative team player with a strong sense of ownership and accountability.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient, comfortable navigating evolving priorities and customer requirements.</li>\n</ul>\n<ul>\n<li>Inclusive and respectful, valuing diverse perspectives and fostering a positive team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic Customer Application Services team based in Taiwan, dedicated to supporting key foundry partners and advancing Synopsys’s leadership in EDA solutions. The team is composed of experienced engineers and technical experts who collaborate closely with customers, sales, and product development groups. Together, you’ll tackle complex challenges, drive innovation, and ensure the successful implementation of industry-leading design automation tools.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine <strong>around the office</strong> can be like</p>\n<p>\\ Explore <strong>Hsinchu</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bb3c37e2-6df","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/applications-engineering-sr-staff-engineer/44408/92561062864","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC design","VLSI","CAD engineering","EDA tool products","verification","place and route","design reuse","physical design"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:00:39.696Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design, VLSI, CAD engineering, EDA tool products, verification, place and route, design reuse, physical design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_517e3008-238"},"title":"Physical Design Engineer","description":"<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$266K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.</p>\n<p><strong>About the Role</strong></p>\n<p>We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.</p>\n<p>You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Develop, build and own tools, flows and methodologies for physical implementation</li>\n<li>Own physical implementation of floorplan blocks from floorplanning to final signoff</li>\n<li>Collaborate with RTL designers to drive optimal block implementation solutions</li>\n<li>Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners</li>\n</ul>\n<p><strong>Qualifications:</strong></p>\n<ul>\n<li>BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development</li>\n<li>Demonstrated success in taping out complex silicon designs</li>\n<li>Hands-on experience with block physical implementation and PPA convergence</li>\n<li>Strong coding experience with python, bazel, TCL</li>\n<li>Strong experience building physical design tools, flows and methodologies</li>\n<li>Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.</li>\n<li>Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation</li>\n</ul>\n<p><strong>Bonus:</strong></p>\n<ul>\n<li>Experience with AI or HPC-focused chips</li>\n<li>Experience with optimizing PPA for high performance compute cores</li>\n<li>Hands-on experience with top-level design methodologies</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_517e3008-238","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/5a265d2b-683f-4cea-9b69-8e137e704ab3","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$266K – $445K","x-skills-required":["physical design","methodology development","python","bazel","TCL","EDA vendors","ASIC partners","microarchitecture","RTL design","physical design","circuit design","physical verification","timing closure"],"x-skills-preferred":["AI or HPC-focused chips","optimizing PPA for high performance compute cores","top-level design methodologies"],"datePosted":"2026-03-06T18:41:49.725Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, methodology development, python, bazel, TCL, EDA vendors, ASIC partners, microarchitecture, RTL design, physical design, circuit design, physical verification, timing closure, AI or HPC-focused chips, optimizing PPA for high performance compute cores, top-level design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":266000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2e9367c2-7d7"},"title":"SerDes IP's Applications Engineering, Sr Staff Engineer","description":"<p>We are seeking a highly motivated and experienced Sr Staff Engineer to join our SerDes IP&#39;s Applications Engineering team. The successful candidate will be responsible for providing technical guidance and hands-on support to customers integrating Synopsys Interface IP into their ASIC SoC/systems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems</li>\n<li>Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s and/or masters with a minimum 10+yrs of Industry experience or equivalent</li>\n<li>At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)</li>\n<li>Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure</li>\n<li>Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2e9367c2-7d7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/herzliya/serdes-ip-s-applications-engineering-sr-staff-engineer/44408/92304383936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP design","ASIC/SoC integration","customer-facing engineering roles","ASIC design flows","simulation/verification","RTL synthesis","floorplanning","physical design","timing closure","High Speed SerDes IPs","PCIe","ETH","USB"],"x-skills-preferred":[],"datePosted":"2026-03-06T07:38:03.021Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Herzliya, Tel Aviv, Israel"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP design, ASIC/SoC integration, customer-facing engineering roles, ASIC design flows, simulation/verification, RTL synthesis, floorplanning, physical design, timing closure, High Speed SerDes IPs, PCIe, ETH, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b455ed20-1e0"},"title":"Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist","description":"<p>We are seeking a highly skilled Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist to join our team. As a key member of our Silicon Design &amp; Verification team, you will be responsible for providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.</li>\n<li>Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.</li>\n<li>Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience with RTL to GDSII full flow and advanced node design methodologies.</li>\n<li>Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b455ed20-1e0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer-rtl2gds-application-specialist/44408/92176305600","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$157000-$235000","x-skills-required":["RTL to GDSII full flow","advanced node design methodologies","synthesis","physical design","static timing analysis","equivalence checking","parasitic extraction","DRC/LVS","power analysis"],"x-skills-preferred":["Perl","Tcl","Python","CAD automation methods","Design Compiler","ICC2","Fusion Compiler","Genus","Innovus","STA","IR drop analysis","Extraction","Formal verification"],"datePosted":"2026-03-06T07:26:03.775Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale, California"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL to GDSII full flow, advanced node design methodologies, synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, power analysis, Perl, Tcl, Python, CAD automation methods, Design Compiler, ICC2, Fusion Compiler, Genus, Innovus, STA, IR drop analysis, Extraction, Formal verification","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3bb7e3ce-9f9"},"title":"ASIC Physical Design, Principal Engineer","description":"<p>We are seeking a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. As an ASIC Physical Design, Principal Engineer, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</li>\n<li>Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.</li>\n<li>Providing technical guidance and mentorship.</li>\n<li>Continuously improving design methodologies and processes to enhance efficiency and quality.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>BE or MSEE with 10+ years of direct physical design experience.</li>\n<li>Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.</li>\n<li>Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3bb7e3ce-9f9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-principal-engineer-in-tan-binh-district/44408/91117302576","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","Mixed Signal IPs","Test Chips"],"x-skills-preferred":["RTL to GDS","Timing and Physical Sign-off","Cross-functional Team Collaboration"],"datePosted":"2026-03-06T07:24:06.055Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Tan Binh district, Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, Mixed Signal IPs, Test Chips, RTL to GDS, Timing and Physical Sign-off, Cross-functional Team Collaboration"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4259360b-f3d"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>We are seeking a highly motivated and experienced ASIC Physical Design, Sr Engineer to join our team. As a Sr Engineer, you will be responsible for leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off. You will collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals. You will also provide technical guidance and mentorship to junior engineers.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</li>\n<li>Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.</li>\n<li>Providing technical guidance and mentorship to junior engineers.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>BE or MSEE with 2+ years of direct physical design experience.</li>\n<li>Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.</li>\n<li>Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4259360b-f3d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-engineer-in-da-nang-ho-chi-minh-city/44408/91617487456","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","IC Design","Implementation Flows"],"x-skills-preferred":["RTL to GDSII","Physical Sign-off","Timing Closure"],"datePosted":"2026-03-06T07:23:34.348Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang/Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, IC Design, Implementation Flows, RTL to GDSII, Physical Sign-off, Timing Closure"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d67eb356-ada"},"title":"Sr Staff SoC Engineer(Backend)","description":"<p>We are seeking a Sr Staff SoC Engineer(Backend) to assist our customers successfully tape out from Netlist to GDS by using Synopsys EDA tools. The successful candidate will focus on design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS).</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>As a Sr Staff SoC Engineer(Backend), you will be working as a member of the customer&#39;s IC design team, leveraging their experience and Synopsys&#39; best practices to have immediate impact on their current project while transferring valuable knowledge for future projects.</p>\n<ul>\n<li>Assist customers in successfully tape out from Netlist to GDS by using Synopsys EDA tools</li>\n<li>Focus on design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS)</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Typically requires BSEE or higher with 5+ years in physical design implementation role</li>\n<li>Familiar with Floorplan, Place and route, DRC/LVS, IR drop, EM and Signal Integrity etc.</li>\n<li>Familiar with STA, Formal Verification and Synthesis is better</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d67eb356-ada","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/sr-staff-soc-engineer-backend/44408/91182619008","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["physical design implementation","EDA tools","design planning","floorplanning","place and route","parasitic extraction","signal integrity analysis","IR drop/EM analysis","physical verification"],"x-skills-preferred":["STA","Formal Verification","Synthesis"],"datePosted":"2026-03-06T07:22:10.304Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"physical design implementation, EDA tools, design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis, IR drop/EM analysis, physical verification, STA, Formal Verification, Synthesis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_358b5046-c5a"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<ul>\n<li>Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</li>\n<li>Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.</li>\n<li>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</li>\n<li>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_358b5046-c5a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183376","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IPs","Timing closure","Physical design tools"],"x-skills-preferred":["Scripting languages (Tcl, Perl, Python)","Automation and workflow optimization"],"datePosted":"2026-03-04T17:09:16.214Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IPs, Timing closure, Physical design tools, Scripting languages (Tcl, Perl, Python), Automation and workflow optimization"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cc644248-b48"},"title":"Physical Design Sr Staff Engineer - PnR","description":"<p>Opening. This role exists to develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<ul>\n<li>Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.</li>\n</ul>\n<ul>\n<li>Drive flow development and optimization to improve design quality and predictability.</li>\n</ul>\n<ul>\n<li>Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).</li>\n</ul>\n<ul>\n<li>Contribute to the adoption and integration of advanced technologies and tool features in design implementation.</li>\n</ul>\n<ul>\n<li>Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.</li>\n</ul>\n<ul>\n<li>Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.</p>\n<p>Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.</p>\n<p>Enhance the predictability and simplicity of implementation processes for complex interface IPs.</p>\n<p>Accelerate the adoption of next-generation design technologies and tools across the industry.</p>\n<p>Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.</p>\n<p>Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.</p>\n<p><strong>What you’ll need</strong></p>\n<ul>\n<li><strong>Minimum 7years</strong> of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why you’ll love this role</strong></p>\n<ul>\n<li>Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.</li>\n</ul>\n<ul>\n<li>Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.</li>\n</ul>\n<ul>\n<li>Participate in professional development opportunities to enhance your skills and expertise.</li>\n</ul>\n<ul>\n<li>Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n</ul>\n<ul>\n<li>Time Away</li>\n</ul>\n<ul>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n</ul>\n<ul>\n<li>Family Support</li>\n</ul>\n<ul>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n</ul>\n<ul>\n<li>ESPP</li>\n</ul>\n<ul>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n</ul>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<ul>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n</ul>\n<ul>\n<li>Compensation</li>\n</ul>\n<ul>\n<li>Competitive salaries.</li>\n</ul>\n<ul>\n<li>Awards</li>\n</ul>\n<ul>\n<li>We&#39;re proud to receive several recognitions.</li>\n</ul>\n<ul>\n<li>Explore the Possibilities with Synopsys</li>\n</ul>\n<ul>\n<li>Search Synopsys Careers</li>\n</ul>\n<ul>\n<li>Join our Talent Community</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9110ed56-39c"},"title":"R&D Engineering, Sr Staff Engineer ICV","description":"<p>Opening. This role exists to manage and provide ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.</p>\n<ul>\n<li>Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.</li>\n<li>Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.</li>\n<li>Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.</li>\n<li>Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.</li>\n<li>Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.</li>\n<li>Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.</li>\n<li>Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.</li>\n<li>Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.</li>\n<li>Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.</li>\n</ul>\n<p><strong>What you&#39;ll be doing</strong></p>\n<p>You will be working as a Sr Staff Engineer in the R&amp;D Engineering team, responsible for delivering post-sales technical expertise and managing ICV runset support for key foundry partners.</p>\n<p><strong>Why this matters</strong></p>\n<p>This role is critical in ensuring the successful implementation of Synopsys solutions and meeting customer needs.</p>\n<p><strong>Why you&#39;ll love it</strong></p>\n<p>You will have the opportunity to work with a talented team of engineers and contribute to the development of cutting-edge EDA tools.</p>\n<p><strong>What you&#39;ll need</strong></p>\n<ul>\n<li>5+ years of experience in EDA tool development, with a focus on ASIC design flows, VLSI, and/or CAD engineering principles.</li>\n<li>Strong understanding of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.</li>\n<li>Excellent communication and problem-solving skills, with the ability to convey technical concepts clearly to diverse audiences.</li>\n<li>Experience working with foundry partners and delivering post-sales technical expertise.</li>\n</ul>\n<p><strong>What you&#39;ll get</strong></p>\n<ul>\n<li>Competitive salary and benefits package.</li>\n<li>Opportunity to work with a talented team of engineers and contribute to the development of cutting-edge EDA tools.</li>\n<li>Professional development opportunities, including training and mentorship.</li>\n</ul>\n<p><strong>How to apply</strong></p>\n<p>If you are a motivated and experienced engineer looking for a new challenge, please submit your application, including your resume and a cover letter, to [insert contact information].</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9110ed56-39c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer-icv/44408/92333269952","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"Competitive salary and benefits package","x-skills-required":["ASIC design flows","VLSI","CAD engineering principles","EDA tool development","Verification","Place and route","Design reuse","Physical design"],"x-skills-preferred":["Foundry partner experience","Post-sales technical expertise","Excellent communication and problem-solving skills"],"datePosted":"2026-03-04T17:06:44.108Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design flows, VLSI, CAD engineering principles, EDA tool development, Verification, Place and route, Design reuse, Physical design, Foundry partner experience, Post-sales technical expertise, Excellent communication and problem-solving skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_509e3a3b-0fb"},"title":"ASIC Physical Design, Sr Staff","description":"<p>Opening. This role is a key member of the Interface IP Design Methodology team, working with global teams to define best practice ASIC design standards and flows. The team is responsible for next-generation SerDes and Memory interface controllers, PHYs, and subsystems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys&#39; best in class tools and technologies.</p>\n<p>Work with leading edge designs and teams to drive the industry best PPA for IP designs.</p>\n<p>Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place &amp; route, timing and power (incl. EM/IR) optimization and analysis.</p>\n<p>Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.</p>\n<p>Work as a liaison between EDAG tool and IP design teams.</p>\n<p>Continuously improve and refine design processes to enhance efficiency and performance.</p>\n<p><strong>What you need</strong></p>\n<p>BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.</p>\n<p>Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.</p>\n<p>Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place &amp; Route tools.</p>\n<p>Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.</p>\n<p>Good analysis, debugging, and problem-solving skills.</p>\n<p>Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.</p>\n<p>Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.</p>\n<p>Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_509e3a3b-0fb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-staff/44408/91568840304","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["BS or MS in EE","10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs","Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions","Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools","Ability to facilitate cross-functional collaboration","Good analysis, debugging, and problem-solving skills","Solid written and verbal communication skills"],"x-skills-preferred":["Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools)","Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR"],"datePosted":"2026-02-11T16:09:21.948Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BS or MS in EE, 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs, Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions, Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools, Ability to facilitate cross-functional collaboration, Good analysis, debugging, and problem-solving skills, Solid written and verbal communication skills, Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools), Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5c3446af-1a5"},"title":"Sr /Staff Applications Engineer( Backend)","description":"<p>Opening. Our team is responsible for designing and developing cutting-edge semiconductor solutions. We work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Provide advanced technical support for EDA PnR tools, addressing complex customer issues and ensuring customer satisfaction.</p>\n<p>Take ownership of PPA (Performance, Power, Area) optimization initiatives, working directly with customers to drive improvements as needed.</p>\n<p>Serve as a primary point of contact for key accounts, engaging directly with customers to understand requirements, address escalations, and ensure successful adoption of solutions.</p>\n<p>Collaborate with regional managers and teams across APAC, US, India and other geographies to coordinate support activities and share best practices.</p>\n<p>Actively contribute to strategies that secure and expand market share by understanding competitive landscape and building strong customer relationships.</p>\n<p>Develop and share technical documentation, lead knowledge transfer, and mentor junior team members.</p>\n<p><strong>What you need</strong></p>\n<ul>\n<li>5+ years of Physical Design or related work experience</li>\n<li>Strong hands-on expertise with EDA PnR tools</li>\n<li>Proven track record of supporting customer projects and solving complex technical issues</li>\n<li>Experience optimizing PPA metrics and driving technical success in customer environments</li>\n<li>Excellent communication skills in English; able to work cross-functionally and cross-regionally</li>\n<li>Ability to manage relationships with both customers and internal stakeholders</li>\n<li>Experience in business development, account management, or market engagement is a plus</li>\n<li>Demonstrated leadership in mentoring, onboarding, or leading technical initiatives</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5c3446af-1a5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/sr-staff-applications-engineer-backend/44408/91160260512","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Physical Design","EDA PnR tools","Customer Support","PPA optimization","Technical Documentation","Knowledge Transfer","Mentorship"],"x-skills-preferred":["Business Development","Account Management","Market Engagement","Leadership"],"datePosted":"2026-02-04T16:09:46.966Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, EDA PnR tools, Customer Support, PPA optimization, Technical Documentation, Knowledge Transfer, Mentorship, Business Development, Account Management, Market Engagement, Leadership"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_97deabd5-0f0"},"title":"Senior Physical Design Engineer","description":"<p>You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.</p>\n<ul>\n<li>Demonstrating the unique advantages and capabilities of Synopsys&#39; industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<p>Bachelor&#39;s and/or Master&#39;s degree in Electrical Engineering or a related field.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_97deabd5-0f0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer-rtl-to-gds-fusion-compiler/44408/89670252864","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$157,000-$235,000","x-skills-required":["8-10 years of experience with the complete RTL-to-GDS physical design flow","Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus","In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies"],"x-skills-preferred":["Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.","Excellent communicator, able to clearly articulate technical concepts to diverse audiences."],"datePosted":"2025-12-22T11:58:13.476Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brackley"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"8-10 years of experience with the complete RTL-to-GDS physical design flow, Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus, In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies, Innovative, resourceful, and proactive in driving technical solutions and continuous improvement., Excellent communicator, able to clearly articulate technical concepts to diverse audiences.","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}}]}