This position offers a unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working, and creative individual to architect and productize next generation power and performance controllers.

Responsibilities:

• Develop test methodologies of next generation power and thermal management features and solutions working with multi-functional teams across the company.
• Drive board design requirements, FW/SW design requirements to characterize the silicon
• Create methodologies for deployment of features into products.
• Work alongside system architects, designers, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability authorities, ATE engineers, and silicon operations, in a fast-paced, high-energy, collaborative work environment to bring industry-defining products to market.
• Train and mentor highly motivated engineers to solve complex challenges

Requirements:

• B. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience)
• 8+ years of experience in silicon bring-up, validation, and productization.
• Experience with control systems, power/thermal controllers and management.
• Expertise and deep understanding in the areas of silicon power, transistor/device physics, power modeling and measurement, active power management
• Proficiency in Python, Perl or C programming languages is a plus
• Self-starter with strong skills in multi-tasking, influencing, communication, presentation, and consensus-building
• Enthusiastic, responsive, and keen on process improvement

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The Core Technology Production Support team supports a suite of business-critical financial applications used by Middle Office, Operations, Treasury, and Trading. These platforms are central to the firm's PnL, risk, cash, trade processing, and regulatory reporting workflows.

Principal Responsibilities:

• End to end ownership of the production environment
• Infrastructure management
• Release planning and deployment
• Incident and problem management, including root cause analysis
• Capacity Planning / BCP Testing
• Build strong relationships with development and end-users/clients
• Foster the DevOps culture
• Focus on client service and delivery
• Become the go-to person for your area of responsibility
• Build subject matter expertise
• Create and maintain high quality documentation and runbooks
• Cross train other Support team members

Qualifications/Skills Required:

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field.
• Minimum 2+ years’ experience supporting an enterprise environment
• Must have previous experience supporting business facing applications
• Strong scripting skills in one of the following: Python (preferred), PowerShell, Perl, etc.
• Excellent SQL skills and knowledge of various database systems
• Must be able to run and understand complex queries
• Ability to support both Windows and Unix/Linux environments

Preferred Skills:

• Experience working in a trading environment
• Exposure to the following:

• CI/CD (Jenkins/Octopus/Artifactory)
• Metrics/KPIs (Datadog/Influx/Tableau)
• Kafka
• Kubernetes
• AI (MCP/Agents)

The estimated base salary range for this position is $100,000 to $175,000, which is specific to New York and may change in the future.

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Location: Dublin, Ireland

Job Description:

As a Principal Engineer at Intercom, you will have the opportunity to lead the definition and execution of key strategic initiatives. You will work autonomously and be accountable for strategic execution in part of the engineering organization. You will build both back-end and front-end systems, and work closely with designers, product managers, researchers, and data analysts. You will coach and mentor other engineers and partner closely with the Group Engineering Managers on technical strategy and leadership.

As an experienced engineer, you will have a mastery of domain knowledge and work as a leader within the R&D org to drive key strategic projects. You will provide assessments of project progress, risks, and challenges to engineering leadership to help guide resource allocation and prioritization. You will contribute to our technical architecture as we grow, scaling to service requests from all our customers' customers. You will care about agility as much as you care for scalability and availability, with continuous deployment keeping us focused on incremental releases.

You will contribute to all phases of software development, including ideation, prototyping, design, and implementation. This role has a mix of both hands-on development as well as lead/architecture work. You will build using the best tools in the industry, investing heavily in AI-powered developer tools that remove friction and help you focus on solving meaningful problems.

You will play an active role in hiring, mentoring, and career development of other engineers. You will raise the bar for technical standards, performance, reliability, and operational excellence.

What skills do I need?

You will ideally have built an exciting SaaS product in your previous roles and loved the satisfaction that comes with knowing that people around the world are using something you've created. You will have significant, demonstrated impact that your work has had on the product and/or the teams. You will have deep knowledge of a high-level programming language, such as Ruby, Python, or Perl, and experience with distributed systems. You will have 2+ years of experience as the primary technical leader for a team.

Benefits

We are a well-treated bunch, with awesome benefits! If there's something important to you that's not on this list, talk to us!

• Competitive salary and equity in a fast-growing start-up
• We serve lunch every weekday, plus a variety of snack foods and a fully stocked kitchen
• Regular compensation reviews - we reward great work!
• Pension scheme & match up to 4%
• Peace of mind with life assurance, as well as comprehensive health and dental insurance for you and your dependents
• Flexible paid time off policy
• Paid maternity leave, as well as 6 weeks paternity leave for fathers, to let you spend valuable time with your loved ones
• If you're cycling, we've got you covered on the Cycle-to-Work Scheme. With secure bike storage too
• MacBooks are our standard, but we're happy to get you whatever equipment helps you get your job done

Policies

Intercom has a hybrid working policy. We believe that working in person helps us stay connected, collaborate easier and create a great culture while still providing flexibility to work from home. We expect employees to be in the office at least three days per week.

We have a radically open and accepting culture at Intercom. We avoid spending time on divisive subjects to foster a safe and cohesive work environment for everyone. As an organization, our policy is to not advocate on behalf of the company or our employees on any social or political topics out of our internal or external communications. We respect personal opinion and expression on these topics on personal social platforms on personal time, and do not challenge or confront anyone for their views on non-work related topics. Our goal is to focus on doing incredible work to achieve our goals and unite the company through our core values.

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We are looking for a Principal Engineer to join our team at Intercom. As a Principal Engineer, you will lead the definition and execution of key strategic initiatives, working autonomously and being accountable for strategic execution in part of the engineering organization.

You will build both back-end and front-end systems, and work closely with designers, product managers, researchers, and data analysts. You will coach and mentor other engineers and partner closely with the Group Engineering Managers on technical strategy and leadership.

Responsibilities:

• Have a mastery of domain knowledge and work as a leader within the R&D org to drive key strategic projects.

• Provide assessments of project progress, risks and challenges to engineering leadership to help guide resource allocation and prioritisation.

• Contribute to our technical architecture as we grow. We scale to service requests from all our customers' customers. We're growing and so are they.

• Care about agility as much you care for scalability and availability. Continuous deployment keeps us focused on incremental releases. Even our biggest technical achievements roll out piece by piece, feature flagged out of sight.

• Contribute to all phases of software development including ideation, prototyping, design and implementation. This role has a mix of both hands-on development as well as lead/architecture work.

• Build using the best tools in the industry. We invest heavily in AI-powered developer tools that remove friction and help you focus on solving meaningful problems.

• Play an active role in hiring, mentoring and career development of other engineers

• Raise the bar for technical standards, performance, reliability, and operational excellence

Requirements:

• Ideally, you've built an exciting SaaS product in your previous roles and loved the satisfaction that comes with knowing that people around the world are using something you've created

• Significant, demonstrated impact that your work has had on the product and/or the teams

• Deep knowledge of a high-level programming language (for example, Ruby, Python, Perl etc.) but it doesn't need to be a language that we use here! Great people are effective and learn what we use quickly (or introduce us to better ways of working)

• You will have experience with Distributed systems

• 2+ years of experience as the primary technical leader for a team

• Experience collaborating directly with technical leaders, product teams and designers, and a proven track record of delivering value to customers or users. Engineers at Intercom are pragmatists who work closely with others on cross-disciplinary teams and have a strong sense of product strategy

Benefits:

• Competitive salary and equity in a fast-growing start-up

• We serve lunch every weekday, plus a variety of snack foods and a fully stocked kitchen

• Regular compensation reviews - we reward great work!

• Pension scheme & match up to 4%

• Peace of mind with life assurance, as well as comprehensive health and dental insurance for you and your dependents

• Flexible paid time off policy

• Paid maternity leave, as well as 6 weeks paternity leave for fathers, to let you spend valuable time with your loved ones

• MacBooks are our standard, but we’re happy to get you whatever equipment helps you get your job done

Policies:

• Intercom has a hybrid working policy. We believe that working in person helps us stay connected, collaborate easier and create a great culture while still providing flexibility to work from home. We expect employees to be in the office at least three days per week.

• We have a radically open and accepting culture at Intercom. We avoid spending time on divisive subjects to foster a safe and cohesive work environment for everyone. As an organization, our policy is to not advocate on behalf of the company or our employees on any social or political topics out of our internal or external communications. We respect personal opinion and expression on these topics on personal social platforms on personal time, and do not challenge or confront anyone for their views on non-work related topics. Our goal is to focus on doing incredible work to achieve our goals and unite the company through our core values.

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Support creation of services estimates to implement the proposed solution. Review services estimates to ensure project scope can be successfully delivered as outlined - technical risk is appropriately mitigated and timelines follow staffing guidelines. Develop co-delivery proposals by identifying and engaging appropriate partners. Drive New Product Introduction (NPI) across PS by training Engagement Managers and developing associated assets such as scope modules, SKUs, success stories and enablement toolkits.

Minimum REQUIRED Knowledge, Skills, and Abilities:

• 5+ years of overall IT / software development experience, solution design and technical architecture experience
• 2+ years of Okta implementation experience
• 3+ years of consulting experience
• 3+ years driving application architecture design
• 3+ years of experience with (IAM) architectures
• Experience with employee and customer identity use cases: HR driven identity, Active Directory, SSO, SaaS application integrations.
• Experience with Identity Governance and Privileged Access Management use cases.
• Demonstrated ability to work and interact with high-level customer executives and technical resources.
• Experience in supporting discovery workshops to derive customer requirements and specifications.
• Experience in developing functional specifications and system design specifications for customer engagements.
• Strong knowledge of Security Architecture, Design and Operations, LDAP, Active Directory, SSO, SAML, OIDC, RBAC, OAuth, JSON, REST.
• Experience integrating with a multitude of On-Prem and SaaS based products.
• Exhibits confidence and a deep understanding of emerging industry practices when solving business problems.
• Identifies critical issues with ease.
• Effectively communicates technical information to non-technical audiences.
• Manages customer expectations effectively.
• Application design experience.
• Clear and Dynamic Communication.
• Ability to travel up to 50%

Highly Desirable Knowledge, Skills, and Abilities:

• Knowledge of software development security and cryptography.
• Familiarity with IAM solution providers.
• Experience with API Gateways, CASB, and Reverse Proxies (NGINX)
• Proficiency with various open-source software and development tools
• Proficiency in one or more of the following: .Net, Ruby, Java, Python or Perl

Education and Certification:

• A Bachelor’s degree (or equivalent) in Computer Science, Information Technology or related discipline required.
• Okta Certified Technical Architect or a combination of Okta Certified Consultant and Okta Certified Developer is a plus.
• CISSP certification is a plus.
• TOGAF certification is a plus.

OTE range for this position for candidates located in the San Francisco Bay area is between $176,000-$242,000 USD. Below is the annual On Target Compensation (OTE) range for candidates located in California (excluding San Francisco Bay Area), Colorado, Illinois, New York and Washington. Your actual OTE, which is inclusive of base salary and incentive compensation, will depend on factors such as your skills, qualifications, experience, and work location. In addition, Okta offers equity (where applicable) and benefits, including health, dental and vision insurance, 401(k), flexible spending account, and paid leave (including PTO and parental leave) in accordance with our applicable plans and policies.

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This role focuses on building, deploying, and managing internal Windows and Linux infrastructure while collaborating with other teams to develop scalable solutions.

Responsibilities:

• Building, managing, and supporting complex application stacks on Windows and Linux Servers.
• Providing Windows and Linux troubleshooting and technical support.
• Deploy, configure and support VMware technologies, including vCenter, ESX and Horizon.
• Use Puppet Enterprise to automate and manage configurations.
• Working with other engineering teams and third-party vendors to implement scalable solutions.
• Ensuring compliance by collaborating with internal audit and compliance teams.
• Developing and maintaining standard operating procedures.
• Participating in a 24/7 on-call support rotation.
• Managing and monitoring all installed Windows and Linux systems and infrastructure.
• Installing, configuring, testing, and maintaining operating systems and system management tools.
• Proactively ensuring high levels of system availability and reliability.
• Monitoring and optimizing application performance, identifying bottlenecks, and collaborating with developers to implement solutions.
• Writing and maintaining custom scripts to improve system efficiency and automation.

Required Qualifications:

• Deep understanding of infrastructure management and automation
• 3 to 5 years of experience in the following:
• Systems Engineering for Corporate Infrastructure.
• Managing large-scale Windows and Linux server environments.
• Virtualization at scale.
• Configuration Management.
• Managing scalable storage solutions, preferably NetApp.
• Developing and maintaining performance metrics for systems.
• Strong understanding of Puppet Enterprise and Puppet Open Source.
• Strong understanding of basic networking concepts.
• Proficient with using Puppet to automate and manage configurations.
• Ability to translate business needs into technical solutions.
• Outstanding analytical and problem-solving skills.
• Strong written and verbal communication skills.
• Experience writing technical design documents and maintaining documentation.
• Familiarity with working in a source-controlled environment.
• Proficiency in scripting languages such as Bash, Python, or Perl.
• Experience with VMware services, including VMware data center virtualization and VMware Horizon.

Basic Qualifications:

• Familiarity with DevOps practices and CI/CD tools.
• Knowledge of orchestration tools.

Compensation and Benefits:

$162,000 - $226,000

Base salary is just one part of our total rewards package at xAI, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.

ITAR Requirements:

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

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As a Senior RTL/Synthesis Digital Design Engineer, you will be responsible for architecting and developing RTL for high-bandwidth PHY IP and test chips. You will define synthesis constraints, resolve STA and simulation issues, and collaborate with verification, controller, and lab teams.

Key responsibilities include:

• Performing logical and physical synthesis, formal verification, and quality checks
• Analysing timing violations and generating reports
• Mentoring junior engineers and supporting digital flow development

The ideal candidate will have a strong background in RTL design and synthesis, with expertise in industry tools such as VCS, Verdi, Spyglass, and Synopsys sign-off. You should also have good English communication skills and be able to work effectively in a team.

At Synopsys, we value talented individuals who are passionate about technology and problem-solving. We offer a comprehensive benefits package, including health and wellness programs, time away, family support, and competitive compensation.

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Your responsibilities will include:

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
• Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
• Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
• Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
• Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
• Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

To be successful in this role, you will need:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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The role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.

The impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.

To be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).

You will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.

Join a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.

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As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.

You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.

What You’ll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

Benefits: At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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As a Sr. Manager of R&D Engineering, you will lead a team of engineers in developing cutting-edge CMOS embedded memory technologies. You will be responsible for designing architecture and circuit implementation for ultra-high-speed, ultra-low-power, or high-density designs. You will also perform schematic entry, circuit simulation, layout planning, and supervision, as well as verify and validate designs to ensure high quality and performance.

The ideal candidate will have a strong background in memory compiler development, with a minimum of 8-10 years of experience in CMOS memory design, circuit simulation, and memory layout design. You will also have experience with layout parasitic extraction and verification tools, as well as programming skills in C-Shell, Perl, C++, or JavaScript.

As a leader, you will be responsible for mentoring and guiding a team of engineers, enhancing workflows and methodologies, and driving project success. You will also be expected to communicate effectively with cross-functional teams, including CAD and Frontend engineers, to automate memory compilers and generate EDA models.

At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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As a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team

Impact:

• Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses
• Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market
• Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps
• Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges
• Contribute to the development of next-generation verification methodologies and best practices within Synopsys
• Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Who You Are:

• An analytical thinker with strong problem-solving abilities and meticulous attention to detail
• A collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

The Team You’ll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You Are:

You are an Automation Engineer/Software Developer who develops scripts, tools, and workflows to automate routine design tasks, enhancing efficiency, precision, and standardization. With a strong foundation in Software Development lifecycle, Software testing and deployment. You are creating methodologies and documentation for the users you support.

Your problem-solving skills and proficiency in UNIX/Linux and programming languages make you a valuable team player.

Your strong communication skills in English enable you to effectively document methods and training materials, ensuring your team can leverage new tools and flows to increase efficiency. You are proactive in providing feedback to improve internal tools and are committed to streamlining design processes and reducing time-to-market.

What You’ll Be Doing:

• Design, develop, troubleshoot, or debug software tools for integrated circuits.
• Develop automation tools, data pipelines, workflows for Analog design teams, to improve project methodologies and lifecycle efficiency.
• Providing feedback to internal tools teams to enhance tool functionality and usability.
• Documenting methods, creating documentation, and training materials for internal designers.
• Collaborating with cross-functional teams to ensure seamless integration and optimization of design tools.

The Impact You Will Have:

• Ensuring the successful implementation of new design methodologies and tools within the team.

• Enhancing the overall efficiency of analog design processes within Synopsys.

• Reducing time-to-market for high-performance silicon chips and software content.

• Driving innovation by providing valuable feedback to improve internal design tools and flows.

• Contributing to the development of cutting-edge technology that shapes the future of the industry.

What You’ll Need:

• Bachelor’s degree in software engineering/electrical engineering or similar field and 2 years of related experience.
• Experience with OOP languages, Python is preferred.
• Experience with CI/CD tools and workflows.
• Familiarity with UNIX/Linux operating systems and shell scripting,
• Experience with Tcl, Perl, Bash, JavaScript is a plus.
• Experience with latest GenAI tools development is a big plus.
• Experience with EDA tools for schematic entry, physical layout, design verification and circuit simulations is a big plus.
• Prior experience working with VLSI design methodology is big plus.

Who You Are:

• Excellent communication skills in English.
• A team player with a collaborative mindset.
• Proactive in debugging and resolving issues independently.
• Skilled in creating clear and concise documentation.

The Team You’ll Be A Part Of:

You will be part of a dynamic team dedicated to streamlining design processes and reducing time-to-market. This team focuses on developing, testing, improving and training designers on cutting-edge flows and tools at Synopsys to enhance analog design efficiency. Your role will involve significant collaboration with cross-functional teams to foster a culture of continuous improvement and innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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The successful candidate will have a BS/MS/PhD in Electronics Engineering or Telecommunications and 2+ years of experience in RTL design for ASIC or PHY IP. You will have experience with VCS, Verdi, Spyglass, Perl/TCL/Python and knowledge of clock domain crossing, APB, JTAG. Good English communication skills are essential.

As a member of our team, you will advance industry-leading high bandwidth interface IP, ensure robust design and verification processes, drive innovation in RTL design and workflows, and enhance productivity through automation.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

As a Principal STA Engineer, you will be responsible for owning full-chip and block-level STA sign-off across all PVT corners and operational modes. You will drive timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.

Responsibilities

• Owning full-chip and block-level STA sign-off across all PVT corners and operational modes.
• Driving timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.
• Analyzing and resolving setup/hold violations, noise, signal integrity (SI), OCV, and derates.
• Defining and validating timing margins, guard-bands, and sign-off criteria for advanced node designs.
• Managing complexities at 7nm, 5nm, and 3nm nodes, including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution.
• Developing and reviewing SDC constraints (clocks, IO delays, exceptions) for MCMM designs.
• Building scalable timing methodologies and driving constraint validation and consistency across teams.
• Utilizing STA tools (Primetime, Tempus) and scripting (Tcl/Python) for automation and flow efficiency.
• Leading timing reviews and sign-off meetings with cross-functional stakeholders.

The Impact You Will Have

• Ensuring successful tapeouts and robust silicon performance at advanced technology nodes.
• Driving innovation in timing sign-off methodologies, influencing industry standards and best practices.
• Reducing time-to-market by achieving efficient timing closure and minimizing design iterations.
• Enhancing cross-functional collaboration and knowledge sharing within Synopsys engineering teams.
• Mentoring and developing junior engineers, building a stronger and more resilient team.
• Contributing to architectural decisions that improve timing convergence and silicon reliability.
• Streamlining timing analysis workflows through automation, improving productivity and accuracy.

What You’ll Need

• B.Eng, or MS in Electrical Engineering or a related field.
• 10–15+ years of experience in STA and timing sign-off for SoCs.
• Proven record of successful tapeouts in advanced nodes (7nm, 5nm, 3nm).
• Expertise in STA tools (Primetime, Tempus) and scripting languages (Tcl, Python, Perl).
• Deep understanding of EM/IR and reliability impacts on timing.
• Experience with full-chip integration and hierarchical STA methodologies.
• Ability to develop scalable timing methodologies for MCMM designs.

Who You Are

• Technical leader and mentor, passionate about knowledge sharing.
• Collaborative communicator, able to lead cross-functional teams and drive consensus.
• Detail-oriented and analytical, with a relentless focus on quality and accuracy.
• Innovative thinker, eager to explore new approaches and technologies.
• Adaptable, capable of navigating fast-paced and evolving engineering environments.
• Confident decision-maker, able to advocate for best practices and influence architectural choices.

The Team You’ll Be A Part Of

You will join a dynamic, highly skilled SOC engineering team dedicated to delivering world-class silicon solutions at the forefront of semiconductor technology.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a passionate and detail-oriented engineering professional who thrives in collaborative environments and enjoys working at the intersection of technology and customer engagement. You possess a deep understanding of VLSI and Design for Testability (DFT) methodologies, and you are eager to use your expertise to drive innovation in semiconductor design.

Collaborating with leading semiconductor design companies to understand their engineering methodologies and unique challenges. Partnering with Account and R&D teams to develop, implement, and optimize stable and scalable tool solutions tailored to customer needs. Gathering and refining technical requirements, providing regular updates, and ensuring alignment across cross-functional teams. Applying advanced Design for Testability (DFT) concepts, including scan insertion, to enhance the reliability and manufacturability of customer designs. Delivering impactful presentations and hands-on demonstrations to customers, highlighting the value and capabilities of Synopsys solutions. Monitoring industry developments and integrating the latest advancements into customer engagements and tool methodologies. Automating workflows and customizing solutions using scripting languages such as TCL, Python, or Perl.

Empowering semiconductor companies to streamline their design processes and achieve higher quality outcomes. Driving customer satisfaction by delivering robust, scalable, and innovative solutions that address real-world engineering challenges. Enhancing the adoption and effectiveness of Synopsys toolsets through expert guidance and technical support. Contributing to the evolution of industry best practices in Design for Testability and automation. Facilitating strong partnerships between Synopsys and its customers, fostering long-term collaboration and success. Enabling faster time-to-market and improved product reliability for customer designs. Helping Synopsys maintain its leadership position in semiconductor innovation and technology advancement.

Master’s degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or related field. 3+ years of relevant experience in semiconductor design, DFT, or related domains. Strong understanding of VLSI design principles and DFT methodologies. Expertise in DFT scan insertion and related verification techniques. Proficiency with scripting languages such as TCL, Python, or Perl for automation and tool customization. Experience with semiconductor design tools and tool flows is highly desirable.

Excellent communicator, able to present complex technical concepts clearly to diverse audiences. Collaborative team player who thrives in cross-functional environments. Analytical thinker with strong problem-solving skills and a proactive approach. Adaptable and resilient, comfortable working in a fast-paced and dynamic industry. Customer-focused, always seeking to deliver value and build positive relationships. Continuous learner, passionate about staying at the forefront of industry trends and technologies.

You’ll join a dynamic, highly skilled team of Application Engineers and Product Specialists dedicated to advancing semiconductor design methodologies and delivering value to customers. The team collaborates closely with Account Managers and R&D experts, ensuring that customer requirements are met with innovative, reliable, and scalable solutions. Together, you will contribute to Synopsys’ reputation for excellence, support each other’s growth, and drive the future of technological innovation in the semiconductor industry.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.

To be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

As a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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Our Hsinchu, Taiwan site is home to a vibrant, collaborative team developing cutting-edge solutions for multi-die systems and advanced packaging. Synopsys powers breakthroughs in AI, cloud computing, 5G, IoT, and automotive, delivering industry-leading tools for chip design and software security.

Responsibilities

• Designing, developing, and delivering software solutions for physical layout automation in advanced packaging and multi-die systems.
• Contributing to technical specifications, implementing robust and efficient code, and applying test-driven development practices.
• Debugging and resolving complex issues collaboratively, employing systematic approaches and leveraging your expertise in computational geometry.
• Ensuring software meets strict quality, performance, and reliability standards required by industry-leading customers.
• Supporting product deployment, releases, and troubleshooting customer issues to ensure seamless adoption and satisfaction.
• Collaborating with cross-functional, global teams to deliver innovative EDA solutions that advance Synopsys' technology leadership.
• Continuously learning and integrating new technologies and methodologies to enhance product capabilities and efficiency.

Impact

• Driving innovation in physical design automation for advanced packaging, enabling the creation of high-performance, next-generation silicon chips.
• Empowering leading technology companies to accelerate their chip design cycles and achieve superior outcomes.
• Contributing to Synopsys' reputation as a pioneer in EDA solutions, strengthening our market leadership and customer trust.
• Improving software reliability and performance, directly impacting customer productivity and success.
• Facilitating the adoption of cutting-edge design methodologies and multi-die systems across the semiconductor industry.
• Mentoring and collaborating with global teammates, fostering knowledge sharing and continuous improvement.
• Enhancing the scalability and adaptability of Synopsys tools to meet evolving industry demands.

Requirements

• Master's degree in Computer Science, Electrical Engineering, or a related field.
• 8+ years of professional software development experience, ideally within EDA or physical design/layout automation.
• Strong proficiency in C++ or other object-oriented programming languages, with solid understanding of algorithms and data structures.
• Experience with computational geometry and software development workflows/tools.
• Exceptional debugging skills and systematic problem-solving abilities.
• Proficiency in Linux; scripting experience (e.g., Tcl, Perl, or similar) preferred.
• Strong written and verbal communication skills in English (intermediate or higher).

Who You Are

• Analytical thinker with outstanding attention to detail.
• Quick learner and self-starter, comfortable with ambiguity and change.
• Collaborative team player who thrives in diverse, global environments.
• Effective communicator who can explain complex ideas clearly to technical and non-technical audiences.
• Adaptable and resilient, able to manage multiple priorities and deadlines.
• Driven by curiosity and a passion for continuous improvement.

Team

You'll join Synopsys' EDA Group R&D team, a dynamic, innovative group focused on developing industry-leading solutions for physical layout automation and advanced packaging. Our team collaborates across global locations, sharing expertise and driving technical excellence. We value creativity, initiative, and a commitment to delivering best-in-class software that shapes the future of chip design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements. As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment. Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions. You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team. Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

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You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key Responsibilities:

• Develop emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers.
• Engage in software development using C/C++ and synthesizable RTL development with Verilog.
• Verify solutions to ensure high performance and reliability.
• Interact with customers during the deployment and debug phases to ensure smooth implementation.
• Collaborate with cross-functional teams to integrate emulation solutions.
• Maintain and enhance existing emulation solutions to meet evolving industry standards.

Impact:

• Drive the development of advanced emulation solutions that meet industry standards.
• Enhance the performance and reliability of semiconductor products through innovative solutions.
• Ensure customer satisfaction by providing robust and efficient deployment support.
• Contribute to the continuous improvement of Synopsys' emulation technologies.
• Support the adoption of new protocols and standards in the semiconductor industry.

Requirements:

• 5+ years of relevant experience
• In-depth knowledge of PCIe, CXL, and UCIe protocols.
• Proficiency in C/C++ programming and object-oriented programming concepts.
• Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog.
• Experience with scripting languages like Python, Perl, or TCL.
• Familiarity with ARM architecture and UVM/functional verification is a plus.

Who You Are:

• A collaborative team player with excellent communication skills.
• A problem-solver with a keen eye for detail and a passion for innovation.
• Adaptable and able to work effectively in a fast-paced, dynamic environment.
• Customer-focused, with the ability to handle deployment and debugging challenges efficiently.
• Committed to continuous learning and staying updated with industry advancements.

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As a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.

Key responsibilities include: Planning tests, checklists, coverage, and assertion planning. Creating detailed verification environments from functional specifications. Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. Writing test cases, checkers, and coverage that implement the verification test plan. Debugging simulations, including those of real signals modeled using SystemVerilog for analog. Performing RTL, GLS, and co-simulations and ensuring coverage closure. Participating in technical reviews and contributing actively. Providing customer support with the bring-up of IP in customer simulation environments. Following and improving development processes to ensure high-quality output.

Requirements include: BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 2+ years of experience in design verification. Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

Ideal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written. A great team player, willing to support others. Self-motivated and highly enthusiastic about technology and solving problems.

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As a DFT Applications Engineer, Staff, you will collaborate with semiconductor design companies to understand their methodologies, challenges, and requirements. You will work closely with Account and R&D teams to develop and implement stable, scalable tool solutions tailored to customer needs.

Responsibilities:

• Collaborate with semiconductor design companies to understand their methodologies, challenges, and requirements.
• Work closely with Account and R&D teams to develop and implement stable, scalable tool solutions tailored to customer needs.
• Gather detailed requirements and provide regular updates on solution progress to internal stakeholders and customers.
• Demonstrate expertise in Design for Testability (DFT), including scan insertion, and deliver impactful presentations to customers.
• Conduct technical demonstrations and training sessions, showcasing the benefits and capabilities of Synopsys solutions.
• Stay abreast of industry advancements, continuously updating your knowledge to ensure best-in-class solutions.
• Contribute to the development of automation and custom scripts to enhance tool functionality and customer productivity.

Impact:

• Enable customers to achieve higher quality and reliability in their semiconductor designs through advanced DFT methodologies.
• Drive customer satisfaction by delivering tailored, scalable, and robust solutions that address unique design challenges.
• Strengthen Synopsys' reputation as a trusted partner in the semiconductor industry by providing expert guidance and support.
• Accelerate adoption of Synopsys tools and technologies, contributing to the company’s growth and market leadership.
• Foster innovation by integrating latest industry trends and methodologies into customer solutions.
• Promote cross-team collaboration, ensuring seamless communication and alignment between Account, R&D, and customer teams.
• Support diversity and inclusion initiatives by contributing your unique perspective and fostering a welcoming work environment.

Requirements:

• Master’s degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant experience in semiconductor design or related areas.
• Strong understanding of VLSI and Design for Testability (DFT) concepts and methodologies.
• In-depth knowledge and practical experience with DFT scan insertion.
• Familiarity with semiconductor design tools and scripting languages (TCL, Python, Perl) for automation and customization.
• Excellent communication and presentation skills, with a proven ability to interact effectively with customers and internal teams.
• Ability to work collaboratively in a cross-functional team environment.
• Strong problem-solving skills and adaptability in a fast-paced, dynamic setting.

Who You Are:

• Innovative thinker with a customer-centric approach.
• Collaborative and open-minded team player.
• Proactive learner, eager to stay ahead of industry trends.
• Effective communicator, able to simplify complex technical topics.
• Resilient and adaptable, thriving in dynamic environments.
• Committed to diversity, inclusion, and fostering a supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a dedicated engineering team in Bangalore focused on delivering advanced solutions to semiconductor design companies. Our team values collaboration, innovation, and continuous learning, working closely with Account and R&D departments to ensure customer success. We foster a supportive environment where every member’s expertise and perspective contribute to our shared goals.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We currently have 614 open roles

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a passionate and detail-oriented early-career engineer eager to make a real impact in high-tech software development. With a strong foundation in computer science or software engineering, you’re excited by the challenge of working on large-scale, technically sophisticated simulation platforms like Systems Tool Kit (STK), Orbit Determination Tool Kit (ODTK), and Behavior Execution Engine (BEE).

What You’ll Be Doing:

• Designing, implementing, and executing functional, regression, performance, and API tests in both manual and automated environments.

• Developing and maintaining automated test suites at the application and source-code levels to ensure comprehensive coverage.

• Expanding and improving test coverage across a diverse set of features, platforms, and configurations.

• Monitoring daily test results, analyzing failures, and conducting root cause analysis to drive product quality improvements.

• Contributing to and maintaining shared test frameworks, infrastructure, and CI-driven quality processes.

• Collaborating closely with software developers, QA engineers, and domain experts to ensure testability, reliability, and product excellence throughout the development lifecycle.

The Impact You Will Have:

• Ensuring high-quality releases of complex simulation software critical to aerospace and engineering customers worldwide.

• Increasing test automation and coverage to accelerate product development cycles and minimize release risk.

• Identifying and resolving defects early, directly improving software reliability.

• Enhancing CI/CD pipelines and test infrastructure, enabling faster feedback loops.

• Collaborating with cross-disciplinary teams to build robust, scalable, and maintainable software solutions.

What You’ll Need:

• Bachelor’s degree in Computer Science, Software Engineering, Systems Engineering, or a related field.

• Strong programming experience in Python, C#, and/or Java, with an ability to quickly learn new languages as needed.

• Proficiency with scripting languages such as Perl, Bash, or PowerShell.

• Solid understanding of software design principles, debugging, and analytical problem-solving techniques.

• Experience working in both Windows and Linux environments.

• Familiarity with automated test frameworks (e.g., NUnit, JUnit) and CI/CD pipelines is a plus.

• Knowledge of software architecture, APIs, or distributed systems is beneficial.

Who You Are:

• Collaborative team player who values open communication and mutual support.

• Detail-oriented and organized, with a persistent drive for quality and process improvement.

• Analytical thinker with strong troubleshooting and root cause analysis skills.

• Adaptable, resilient, and eager to learn in a dynamic and evolving technical landscape.

• Effective communicator, able to translate complex technical issues for diverse audiences.

• Self-motivated and proactive, with a genuine passion for technology and innovation.

The Team You’ll Be A Part Of:

You’ll join a dynamic, multidisciplinary team dedicated to advancing STK (Systems Tool Kit), a commercial mission modeling software used by thousands worldwide. The team is composed of experts in communications, radar, software engineering, and mission analysis, collaborating closely to deliver impactful solutions to some of the most challenging problems in aerospace, defense, and beyond.

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As a Staff ASIC Digital Design Engineer, you will be part of our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.

Key responsibilities include:

Creating and debugging test benches and test cases Running RTL and gate-level simulations Supporting application engineers and customers on HBM/DDR PHY topics Contributing to technical documentation Driving product improvements based on customer feedback

The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

ASIC RTL design and verification experience Verilog, PERL, TCL, Python skills Static timing analysis and synthesis knowledge Simulation and debugging abilities HBM/DDR protocol experience is an asset

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.

With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.

Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.

You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.

Responsibilities

• Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.

• Define synthesis constraints and resolve STA and gate-level simulation issues.

• Collaborate with verification, controller, and lab teams for design and debugging.

• Support RTL to GDS flow during logic implementation.

• Lead projects and train junior engineers.

• Work with customers to resolve technical RTL issues.

The Impact You Will Have

• Deliver robust RTL designs for advanced silicon solutions.

• Drive successful project completion and tape-outs.

• Enhance design quality and verification efficiency.

• Support customer success and strengthen Synopsys’ reputation.

• Mentor and grow engineering talent within the team.

• Contribute to digital flow improvements and innovation.

What You’ll Need

• BS/MS/PhD in Electronics Engineering or Telecommunications.

• 5+ years of RTL design experience for ASIC or PHY IP.

• Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).

• Knowledge of clock domain crossing, APB, JTAG protocols.

• Strong English communication skills.

Who You Are

• Responsible, result-oriented, and self-motivated.

• Collaborative and proactive problem solver.

• Effective communicator and mentor.

The Team You’ll Be A Part Of

Join a collaborative engineering team delivering innovative PHY IP solutions.

Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits.

Your recruiter will provide more details about salary and benefits during the hiring process.

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Responsibilities:

• Manage a team and develop SRAM/Register file /TCAM /ROM architectures and circuit implementation techniques.
• Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation.
• Designing and implementing optimum low-power and area-efficient embedded memory (SRAM, register files, etc.) circuits and architectures.
• Learn and apply skills in memory compilers having Transistor level circuit Design.
• Resolves a wide range of issues in creative ways
• Inter-team interaction
• Customer focus
• Frequently networks with senior internal and external personnel in own area of expertise
• Experience of FinFet Technology for Memory Design
• Can coordinate, facilitate, and monitor the daily activities of a small to large group of support resources within their section or project team
• With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities
• Proactively addresses and communicates issues impacting productivity

As a Manager, the individual will be involved in challenging projects and drive it to completion in record time.

You will quickly ramp on the existing flow, understand the challenges, and produce the work plan.

Your expertise in deep submicron technology and Finfet, SRAM design, processor design, Digital design flow and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team.

You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule.

Skills/Experience:

• 10yrs+ Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation.
• BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from premium institute/university
• Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations.
• Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometre technology nodes
• Mastery in scripting using Perl, python for automation

Fundamentals:

• Understanding of RC circuit of 1st and 2nd order.
• Basics of Digital design (realization of Boolean function using Gates, Mux etc)
• Fundamentals of Transfer function and its analysis for stability etc.
• Strong CMOS fundamentals
• Knowledge of CMOS fabrication
• Good digital design knowledge
• Exposure to basic Analog fundamentals

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

• Health & Wellness: Comprehensive medical and healthcare plans that work for you and your family.
• Time Away: In addition to company holidays, we have ETO and FTO Programs.
• Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Retirement Plans: Save for your future with our retirement plans that vary by region and country.
• Compensation: Competitive salaries.

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DevOps Engineer II

This is a hybrid position in our Canonsburg, Pennsylvania office.

You Are:

You are a motivated DevOps professional with a solid foundation in build management, scripting, and version control. You enjoy collaborating with others, learning new technologies, and solving technical challenges. You are adaptable, eager to grow your skills, and committed to supporting reliable and efficient software releases in a fast-paced environment.

What You’ll Be Doing:

• Maintaining, monitoring, documenting, and testing product builds and packaging to ensure quality releases.
• Preparing, configuring, deploying, and maintaining build agents to support continuous integration and delivery pipelines.
• Conducting system tests to assess the security, performance, and reliability of build systems and processes.
• Collaborating with developers to identify code and testing issues using tools such as TotalView, and reporting findings promptly.
• Working with IT to maintain DevOps infrastructure and manage necessary packages for compiling, linking, and testing software.
• Adjusting builds and packaging in partnership with development teams to meet evolving requirements and project goals.
• Participating in Azure DevOps trainings to enhance your skills and knowledge in modern DevOps practices.
• Operating under direct supervision, with regular feedback and mentorship from experienced staff and the DevOps Manager.

The Impact You Will Have:

• Ensure the reliability and quality of software releases that power cutting-edge engineering simulations worldwide.
• Support the development of robust DevOps processes that accelerate product delivery and innovation.
• Improve build and deployment efficiency, enabling teams to focus on solving complex engineering problems.
• Contribute to a culture of operational excellence and continuous improvement within Synopsys.
• Facilitate collaboration across development, IT, and DevOps teams to drive successful project outcomes.
• Help extend simulation software to modern HPC chipsets, supporting large model simulations on clusters.

What You’ll Need:

• Bachelor's Degree in Engineering, Computer Science, or a related field with 2 years of professional experience or a Master’s Degree.
• Experience with source code versioning tools such as Git along with CI/CD practices for building, testing, and release of applications.
• Proficient in automation scripting languages (PowerShell, Python, Perl, Bash).
• Knowledge of CMake, Azure DevOps, and programming languages (C/C++, C#).
• Understanding of Linux and/or Windows operating systems.
• Experience working with compilers such as Microsoft Visual Studio, GCC, or Intel.
• Willingness to learn about modern HPC chipsets and scalable simulation environments.
• Exposure and working knowledge of ARM64 architecture and supporting compilers.
• Knowledge of security best practices and vulnerability remediation for source code and applications.

Who You Are:

• Detail-oriented and proactive in identifying and resolving issues.
• Collaborative team player with strong communication skills.
• Adaptable and open to learning new technologies and processes.
• Analytical thinker who enjoys troubleshooting and optimizing systems.
• Self-motivated with a growth mindset, receptive to mentorship and feedback.
• Committed to delivering high-quality results in a fast-paced environment.

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This role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

Key responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

The ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.

As a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.

In this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.

Synopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking an experienced SerDes Analog Behavioral Modeling & Validation Engineer to join our team.

As a key member of our engineering team, you will be responsible for developing and refining behavioral models for high-speed SerDes blocks, collaborating with analog teams for SPICE-vs-model correlation and sign-off, and working with digital verification teams on edge-case coverage.

Responsibilities

• Collaborate with analog teams for SPICE-vs-model correlation and sign-off.
• Develop and refine behavioral models for high-speed SerDes blocks.
• Capture calibration, adaptation, and impairments in models.
• Work with digital verification teams on edge-case coverage.
• Automate comparison flows and improve model fidelity.
• Embed realistic non-idealities and verify behavioral netlists.

Impact

• Deliver high-trust models, reducing mixed-signal bugs.
• Enable realistic digital verification and improve coverage.
• Strengthen Synopsys' reputation for robust connectivity IP.
• Catch issues early and accelerate debug cycles.
• Foster collaboration between analog, modeling, and DV teams.

Requirements

• BSc, MSc, or PhD in Electrical/Computer Engineering with 5+ years experience.
• Expertise in SerDes analog blocks and modeling impairments.
• Fluency with SPICE tools and waveform analysis.
• Strong scripting/programming in Python, TCL, Perl, C/C++.
• Experience automating comparisons and reporting.

Team

You'll join a multidisciplinary group focused on modeling, validation, and verification of high-speed SerDes IP,bridging analog and digital domains for industry-leading solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Accelerate the adoption of industry-leading formal verification solutions, enabling customers to achieve robust, high-quality silicon designs. Strengthen Synopsys' reputation as a trusted partner for verification innovation and excellence. Drive customer success by delivering tailored consulting services and assertion IPs that address complex verification challenges. Enhance productivity and efficiency for customers through advanced formal methodologies and flows. Influence the direction of formal verification technology by collaborating with R&D and Product Management teams. Foster a culture of technical excellence and inclusion within your team, empowering members to grow and contribute meaningfully. Enable strategic customers to meet critical industry requirements such as design security, automotive safety, and verification signoff.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.

Key responsibilities include:

• Proposing and developing advanced layout design techniques and methodologies
• Running verification on existing designs to assess PDK update impacts
• Creating innovative scripts to minimize rework
• Collaborating with multiple organizations and teams across global time zones

The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).

You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.

You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.

You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.

You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.

You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.

You will mentor junior engineers and contribute to team knowledge sharing initiatives.

Impact

You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.

You will advance Synopsys' leadership in IP implementation at cutting-edge technology nodes.

You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.

You will facilitate seamless cross-site collaboration, ensuring global project success.

You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.

You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.

Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field.

3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).

Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.

Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.

Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.

Strong analytical and debugging skills for addressing complex design challenges.

Team

You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.

The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.

Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include designing and analysing algorithms for end-to-end timing constraint management, driving the success and evolution of Synopsys' constraint flow and tools, collaborating within a highly skilled engineering team to deliver innovative solutions for static timing analysis (STA) during design and optimisation, and designing, developing, troubleshooting, and debugging advanced software programs for constraint generation and verification.

The ideal candidate will have a B.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute, 8 years of experience with strong foundational knowledge of programming fundamentals, including data structures, sorting, searching algorithms, and numerical methods, ability to read and analyse code in C/C++, exceptional debugging skills and proficiency in scripting languages (such as Python, Perl, or TCL), demonstrated analytical and problem-solving skills, with a keen attention to detail, independent judgment in selecting methods and techniques to obtain technical solutions, experience with Synopsys Static Timing Analysis (STA) tools and EDA tool/CAD flow development (preferred), and experience with Synopsys Design Constraints (SDC) is a strong plus.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. The total rewards include both monetary and non-monetary offerings.

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Key responsibilities include:

• Strong problem-solving skills and the ability to debug complex software issues in large-scale systems.
• 2–5 years of industry experience in software development or EDA-related R&D roles.
• Ability to contribute independently to feature development, bug fixes, and performance improvements.
• Good communication skills and the ability to collaborate effectively within a cross-functional team.

Ideal candidates will have proficiency in C/C++ development, with strong fundamentals in data structures and algorithms. Experience working on Linux platforms and familiarity with build systems, debugging tools, and development workflows on Linux is a plus. Exposure to scripting languages such as Tcl, Perl, or Python will be an added advantage.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Coordinate partners, distributor, and retailers by projects.

Support Key retailers to drive more sell through revenue.

Centralized the CORSAIR elements follow by HQ policy and apply into all the local marketing tools, coherent with NPI global launch, and investment plan.

Online direct focus on shopee, PCHOME, MOMO for A+ content, graphic design and bundle campaigns of revenue growth.

Content proof - manage on all the product content in Chinese both online and offline to centralize the right and correct information and product features through partners, customers, distributors, and e-tailers.

Retail display- To strengthen CORSAIR displays across all retailers' stores. To plan and execute so all Corsair product lines are displayed in a way for demand generation against competitors. To allow better product positioning, signboard access, shelf displays, gaming displays and endcaps across all retailers. To make more dynamic displays according to message with changing displays across all retail.

Channel Inventory control- To make sure the enough stocks of the major retailers, manage POS data by weekly.

Sell through- Work with distributors to develop CORSAIR channel customers and drive sell through by projects/promos.

Plan and strategy- Execute solution selling to enlarge our values to customer

Market information- survey the competitors' information among the channels including marketing activity, price, promos, ..etc. and leverage their strength to complete the alliance and results by projects.

Product training- To educate the customers(sub-disty, secondary, e-tailers) to complete the selling features and product knowledge

Price control – Daily analysis, including all major key skus, pricing is where it should be, and competitive analysis including competitor promotions

Work with Etailers and Retailers on banners, art, video marketing, bundle programs, A+content, etc.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.

With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.

You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.

Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.

As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.

Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.

You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.

Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.

Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.

Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.

Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.

Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.

Contribute to the development of next-generation verification methodologies and best practices within Synopsys.

Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.

5-8 years of hands-on experience in the Physical Verification (PV) domain.

Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.

Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.

Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.

Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.

Exposure to competitive EDA tools and awareness of their strengths and limitations.

An analytical thinker with strong problem-solving abilities and meticulous attention to detail.

A collaborative team player who fosters knowledge sharing and mentorship.

Effective communicator, capable of translating technical concepts to diverse audiences.

Adaptable and proactive, with a passion for continuous learning and innovation.

Customer-focused, with a commitment to delivering high-quality solutions on time.

Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.

Work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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At Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.

Key Responsibilities:

• Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
• Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.
• Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.
• Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).
• Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.
• Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys' product lines.

Impact:

• Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.
• Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.
• Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys' tools, driving industry-leading outcomes.
• Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.
• Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.
• Strengthen Synopsys' position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.

Requirements:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.
• 5+ years of experience in chip design, EDA, or related fields.
• Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).
• Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.
• Solid understanding of Unix/Linux environments and design flow automation.
• Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.
• Familiarity with low power design techniques, computer architecture, and machine learning principles.

Who We're Looking For:

• A creative problem solver who approaches challenges with curiosity and resilience.
• An effective communicator who collaborates well with multidisciplinary teams.
• Detail-oriented with a passion for quality and continuous improvement.
• Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.
• Committed to learning, growth, and sharing knowledge with others.

The Team You'll Be A Part Of:

You'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Staff Engineer, Application Engineering (AE), you will work on latest Synopsys implementation technologies (AI-ML Implementation, Physical Synthesis RTL-GDS, Multi Source CTS, Indesign Fusion technologies etc.) to solve complex PPA challenges Synopsys customers face.

Responsibilities:

• Work on developing and debugging RTL-GDS implementation methodologies and flows.
• Provide technical solutions by identifying the design and/or EDA tool issues and providing appropriate solutions for customers.
• Effectively translate the findings into requirements for R&D to improve both tool behaviors with enhancements as adaptive long-term solutions.
• Involved in the deployment of new technologies on the latest EDA versions and enabling customers to migrate to newer versions achieving the best PPA.
• Come up with proactive knowledge of customers' pain point and come up with innovative solutions to address the same.
• Closely interacting with Synopsys R&D team and product development team to develop future technologies.

Requirements:

• At least 5+ years of experience in Physical Implementation RTL-GDS.
• Candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs.
• Proficiency in Synopsys implementation tools is an advantage.
• The person must be self-motivated and dedicated with excellent debug skills.
• Requires proficiency in scripting (tcl / unix / perl).
• Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Join the world's largest asset manager and elevate your career in valuations governance. As a Valuations Governance Associate, you will play a key role in supporting the investment valuation function for private, illiquid investments. You will work closely with investment teams, external valuation providers, and auditors to ensure accurate and timely valuations.

Team Overview

The Private Valuation Team within Alternative Operations supports the investment valuation function for private, illiquid investments. The team focuses on adding value by providing valuation oversight and coordination of valuations and supporting documentation.

Role Responsibility

• Prepare valuation documentation for private equity, private debt, and other alternative investments.
• Support monthly and quarterly valuation cycles.
• Manage workflow of data to 3rd party valuation firms; working with investment teams to ensure all relevant information is incorporated into valuations.
• Provide high-quality client service externally and internally. Address inquiries, perform controls, problem solve, and mitigate risks for clients and internal BlackRock partners.
• Initiate and help drive platform and process innovations to support expanding business needs, minimise risk, enhance quality, and navigate the changing markets.
• Review and tie out of valuation templates received from third-party service providers. Communicate any comments and coordinate sign-off in coordination with Investment, Pricing, and Fund Administration teams.
• Review legal documents to determine rights associated with new securities purchased.
• Prepare materials to be provided to the Valuation Committee and presenting findings to Pricing Committees and other management as necessary.
• Liaise with independent auditors. Provide support for valuations and answer questions as necessary in a controlled and efficient manner.
• Perform a review of fair value reporting provided by underlying managers and Co-Investment sponsors.
• Operate as part of a global team.

Experience

• Bachelor's degree is required, with a preference for Accounting or Finance.
• 2 to 5 years of relevant experience, private investment valuation experience preferred.
• Solid understanding of ASC 820 and IFRS 13, familiarity with PWERM, OPM, and Current Value valuation techniques preferred.
• Ability to work with and manage financial data and build summarised reports.
• Experience building, testing, and implementing valuation models.
• Natural standout colleague able to work in an innovative, ambitious, and fast-paced environment while maintaining attention to detail.
• Excellent verbal and written communication skills combined with agile critical thinking and a problem-solving mindset.
• Ability to quickly learn the intricacies of complex financial instruments.
• Working knowledge of Bloomberg, Reuters, Interactive Data, and MS Office Suite as well as SQL, Unix commands, PERL, etc. is an advantage.

Our benefits

To help you stay energized, engaged, and inspired, we offer a wide range of employee benefits including: retirement investment and tools designed to help you in building a sound financial future; access to education reimbursement; comprehensive resources to support your physical health and emotional well-being; family support programs; and Flexible Time Off (FTO) so you can relax, recharge, and be there for the people you care about.

Our hybrid work model

BlackRock's hybrid work model is designed to enable a culture of collaboration and apprenticeship that enriches the experience of our employees, while supporting flexibility for all. Employees are currently required to work at least 4 days in the office per week, with the flexibility to work from home 1 day a week. Some business groups may require more time in the office due to their roles and responsibilities. We remain focused on increasing the impactful moments that arise when we work together in person – aligned with our commitment to performance and innovation. As a new joiner, you can count on this hybrid model to accelerate your learning and onboarding experience here at BlackRock.

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Aladdin Data - Solutions manages the continuous changes and development of Aladdin’s enterprise analytics data assets and production solutions and is responsible for the implementation of data and analytics solutions for BlackRock businesses and Aladdin clients.

The Aladdin Data platforms and services are designed to deliver industry leading investment data and risk analytics content to the Aladdin community, including BlackRock as the largest client. The primary users include investors, risk managers, compliance officials, investment operations, and technology teams for broader organisation applications. We are proud to supply the data products and solutions to meet the evolving needs of portfolio management, risk and performance analysis, investment compliance, regulatory reporting, client reporting and beyond.

Our Data Implementation team of data solutions specialists covers end-to-end Aladdin data flows from vendor and client input data sets transformed and enriched into security, portfolio, benchmark, and financial analytics outputs for new and expanding Aladdin clients. The team works directly with clients and Aladdin Client Transformation specialists to understand client dependencies, business objectives and custom use cases to ensure Aladdin’s data and analytics are effectively enhanced, deployed, and adopted across each function and organisation.

Our clients cover global, multi-asset managers or owners allocating across fixed income, equity, private markets, and derivatives. The team provides the data specialties across asset classes and data domains for the successful whole-portfolio modelling. Successful Aladdin data implementation specialists develop and excel in many cross-functional skills including client communication, project management, business analysis as well as hands-on data analysis and technology system configuration. Innovation is at the core of Aladdin’s culture, and the team is continuously solutioning for our clients and re-engineering our processes.

At the forefront of evolving market and industry data needs, with each successful projects, we drive continuous developments and transformation initiatives to expand our solutions and advance our data products capabilities.

Role Description: The team is looking for experienced investment data specialists to enhance and expand our capabilities to capture the growth opportunities with a strong business pipeline. The successful candidates will contribute to or be directly responsible for one or multiple projects, across all data domains and capabilities.

Responsibilities include:

• Drive client engagement, scope of work review, requirements collection and project planning for the data management workstream of new Aladdin implementations

• Manage data workstream progress and communications with clients and partners to ensure successful delivery of critical milestones along the project plan.

• Collaborate with client investment, technology, and data professionals to ensure alignment and clarity of data scope, mapping, normalization, and implementation approaches.

• Educate and guide clients on Aladdin data conventions and target state data management workflows inclusive of on-site training for client data teams.

• Use standard interfaces and configurable elements to facilitate the onboarding of client data from clients directly and/or third-party data providers.

• Partner with front-office and investment process practice leads to configure investment portfolio structure, benchmark assignments, and establish proper risk analytics deliverables.

• Manage systematic data reconciliation and reviews and drive the resolution of issues with internal data owners, external vendors, and/or the development of solutions with clients and partners.

• Partner with Analytics Stewards to ensure valuation and risk analytics results are comprehensive and up to market and modelling standard.

• Manage client requirements, provide critical business, and technical analysis to development partners in data stewards, production solutions and engineering functions for new data and solutions development. Provide validation and directly manage the client UAT.

• Create dedicated client documentation with standard templates and partner with Data Operations to transition new clients into production support.

Qualifications and skillsets:

We are looking for quick learners, independent thinkers with new perspectives to challenge the way we operate and help prototype new solutions we can ultimately deploy to a standard implementation playbook. Individuals with strong technical and analytical interests and skills would find the data implementation practice best in supporting their continuous developments through the ownership of critical client project elements as well as organisational initiatives to constantly evolve the platform and best practice, leveraging data and technology.

· Bachelor’s Degree is required, with preference to business, technology, or engineering focus.

· 3-5 years of experience either as an investment/data technology implementation specialist or with direct relevant user, development, service, or operation experiences.

· Familiarity with investment data and analytics is required; Private markets or derivative specialties is a plus.

· Strong attention to details and focus on high quality delivery.

· Comfortable working with clients and partners at all levels of the business.

· Relentless desire for understanding how processes work and entrepreneurial drive to learn new skills and technologies.

· Strong track record of successfully handling and completing large and complex projects. Critical thinking and demonstratable experience using technology to solve problems at scale.

· Shown ability to work well independently or as part of a team in an innovative, ambitious, and fast-paced environment, run multiple tasks, adapt to change, and work well under tight time restraints.

· Excellent verbal and written communication, collaboration, and relationship-building skills

· Working experience with Python, SQL preferred. Knowledge of UNIX, PERL, Java is a plus.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15411

Remote Eligible

No

Date Posted

02/23/2026

Alternate Job Titles:

• Staff Applications Engineer, Digital Implementation

• Staff AE – RTL-to-GDS Solutions

• Senior Digital Design Flow Engineer

• Customer Success Engineer – Physical Design

• Staff Field Applications Engineer – EDA

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced engineering professional with a passion for digital design flows and a drive to see customers succeed. You thrive at the intersection of deep technical problem-solving and collaborative partnership, always eager to tackle challenges that span RTL handoff to physical signoff. Your expertise in RTL-to-GDS flows allows you to confidently lead technical engagements, while your curiosity and commitment to learning keep you at the forefront of evolving methodologies and tools.

You are self-driven, organized, and able to independently manage complex projects, always maintaining a strong sense of ownership over deliverables. You communicate clearly and effectively, whether you are guiding customers through best practices, collaborating with R&D, or translating customer requirements into actionable feature requests. Your analytical skills help you quickly understand diverse customer scenarios, and your adaptability enables you to develop innovative solutions for unique challenges.

You value teamwork and are motivated by the opportunity to influence both customer success and product evolution. You believe in continuous improvement, for yourself and for the solutions you support. If you are eager to make a tangible impact on the next generation of digital design, we invite you to join us.

What You’ll Be Doing:

• Serve as the primary technical advisor for customers implementing Synopsys’ RTL-to-GDS (R2G) solution, including synthesis, physical implementation, and signoff flows.

• Lead customer onboarding, technical evaluations, benchmarking, and full production deployments across advanced technology nodes.

• Analyze complex customer challenges and deliver tailored solutions using deep expertise in digital implementation flows.

• Develop and optimize RTL-to-GDS methodologies, including floorplanning, placement, clock tree synthesis, routing, and signoff correlation.

• Collaborate with global Applications Engineering, R&D, and Product Management teams to enhance methodologies and influence tool development.

• Provide technical guidance and best practices to customers while ensuring successful project delivery and adoption of Synopsys tools.

• Troubleshoot and triage tool issues, provide reproducible testcases, and advocate for customer-driven enhancements.

The Impact You Will Have:

• Drive successful adoption and expansion of Synopsys’ digital implementation toolchain across key customer accounts.

• Enable customers to achieve optimal PPA (Power, Performance, Area) and signoff closure on complex projects.

• Serve as the voice of the customer, directly influencing tool enhancements and product roadmap evolution.

• Accelerate customer productivity and innovation by delivering robust methodologies and automation solutions.

• Foster long-term, trusted relationships with customers, contributing to Synopsys’ industry leadership and growth.

• Enhance cross-functional collaboration within Synopsys, driving continuous improvement in product quality and support.

• Champion best practices and knowledge sharing within the Applications Engineering community.

What You’ll Need:

• Proven expertise in RTL-to-GDS flows, including digital synthesis (Design Compiler/Fusion Compiler), physical implementation (ICC2/Fusion Compiler), and static timing analysis (PrimeTime).

• Hands-on experience with advanced node design, floorplanning, PPA optimization, and signoff-driven closure.

• Strong proficiency in scripting languages (Tcl, Python, Perl) for flow automation and customization.

• Ability to independently own technical deliverables, lead customer evaluations, and drive production deployments.

• Deep understanding of digital design methodologies, process technology challenges, and EDA tool ecosystems.

Who You Are:

• Analytical and methodical, able to evaluate diverse customer scenarios and devise effective solutions.

• Exceptional communicator, comfortable engaging with both internal teams and external partners.

• Self-motivated and accountable, thriving with moderate supervision and a high degree of autonomy.

• Collaborative team player, eager to share knowledge and learn from others.

• Customer-focused, energetic, and adaptable to fast-paced, evolving environments.

The Team You’ll Be A Part Of:

You’ll join a dynamic, globally distributed Applications Engineering team at Synopsys, dedicated to driving customer success in digital implementation. Our team works closely with R&D, Product Management, and field engineers to deliver innovative solutions, optimize design flows, and influence product direction. We foster a culture of collaboration, continuous learning, and knowledge sharing, empowering each other to solve complex challenges and achieve excellence for our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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We are seeking a proactive, results-driven leader with a deep technical background in physical design and processor implementation. Your expertise is grounded in architecting high-performance, energy-efficient silicon solutions, and you thrive in fast-paced, collaborative environments. You possess a strong sense of ownership and are comfortable navigating ambiguity to deliver innovative solutions to complex engineering challenges.

As an Applications Engineering Architect (PPA), you will be responsible for architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems, targeting aggressive power and performance goals for diverse end-user applications. You will develop and refine advanced EDA tools and design methodologies to support state-of-the-art processor implementations.

Key Responsibilities:

• Architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems
• Developing and refining advanced EDA tools and design methodologies
• Collaborating closely with key Synopsys customers to guide their development of processor-based platforms in advanced silicon technologies
• Partnering with Synopsys R&D and marketing teams to influence and define future product roadmaps and features
• Working in synergy with leading IP partners to ensure seamless integration of EDA tools, methodologies, and IP

Requirements:

• Proven expertise in physical design and implementation of high-performance processors, SoCs, or processor-based subsystems
• In-depth experience with advanced EDA tools, flows, and methodologies for digital implementation
• Strong knowledge of silicon technologies at advanced nodes and associated design challenges
• Hands-on experience integrating IP and collaborating with IP vendors for seamless tool and methodology interoperability
• Track record of working directly with customers, understanding their requirements, and delivering tailored solutions

We offer a comprehensive range of health, wellness, and financial benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off. We also provide opportunities for professional growth and development, including training and education programs, mentorship, and career advancement opportunities.

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Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.

You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.

Technical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.

You bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You’ll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Fostering technical excellence and knowledge sharing across the organization.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Directly impact customer success by providing guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You’ll Need:

• 8+ years of experience in Firmware, ASIC design, verification, system validation, and technical roles.
• Be results driven
• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
• In-depth knowledge of system-level validation for high-speed interface PHY
• Proven track record of working cross-functionally and driving issues to closure
• Knowledge of mixed-signal design
• Experience in working in cross-functional collaborations
• Be an excellent communicator and a beacon for change

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.

You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.

You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.

You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.

The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.

You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys' reputation as a trusted partner and thought leader in the semiconductor industry.

What You'll Need:

• B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.
• Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).
• Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place & Route, and timing analysis.
• Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.
• Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.
• Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.
• Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.

Who You Are:

• Excellent communicator able to build trust and rapport with diverse stakeholders.
• Analytical thinker with strong troubleshooting and debugging skills.
• Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.
• Highly collaborative team player who thrives in fast-paced, multicultural environments.
• Self-motivated, innovative, and passionate about continuous learning and process improvement.
• Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.

The Team You’ll Be A Part Of:

You will join a dynamic, expert team within the Silicon Design & Verification business at Synopsys, based in Hyderabad. The team is dedicated to driving customer success in high-impact projects, deploying advanced implementation flows, and shaping the future of silicon design. Collaboration, technical excellence, and a commitment to innovation are at the core of our culture. You’ll work closely with customers, R&D, and field teams to deliver transformative solutions and advance industry-leading technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk.

You Are:

You are a talented Firmware Development Engineer with a passion for embedded systems and software innovation. You thrive in environments where high-speed and precision matter, bringing a strong programming background and an aptitude for developing reliable, scalable firmware solutions. Your expertise in C programming and familiarity with scripting languages such as Perl, TCL, or Python make you a versatile contributor. You are experienced in developing firmware for complex embedded systems and high-speed interfaces, and you take pride in rigorous problem-solving and debugging. You enjoy collaborating with hardware engineers to ensure seamless integration between firmware and hardware, and you are skilled at navigating verification and emulation environments to enhance product quality. Your attention to detail and commitment to delivering robust, high-quality firmware are matched by your ability to adapt to new challenges in a fast-moving industry. You value diversity and inclusion, and you are comfortable working in a dynamic, multicultural team. Whether you are mentoring junior engineers, spearheading integration efforts, or contributing to pre-silicon environments, you consistently demonstrate initiative, innovation, and a collaborative spirit. If you are excited to power the Era of Smart Everything and help shape tomorrow’s breakthroughs, you’ll find your place at Synopsys.

What You’ll Be Doing:

• Designing and implementing firmware for high-speed PHY IPs using C programming.
• Developing and maintaining software development environments and tools to streamline workflows.
• Collaborating with hardware engineers to ensure firmware compatibility and optimized integration with hardware designs.
• Conducting rigorous unit testing and debugging to ensure high-quality firmware performance
• Utilizing verification and emulation environments to enhance the integration process and support pre-silicon development.
• Documenting design processes, maintaining code quality, and ensuring compliance with industry standards.
• Staying current with emerging technologies in embedded systems and high-speed interfaces.

The Impact You Will Have:

• Accelerating the integration of advanced capabilities into SoCs through robust firmware development.
• Enhancing product reliability, performance, and time-to-market for customers in diverse industries.
• Supporting the development of differentiated products that power innovations like AI, 5G, IoT, and self-driving cars.
• Reducing risk and optimizing project outcomes by leveraging your expertise in embedded systems and high-speed interfaces.
• Driving cross-functional collaboration between software and hardware teams to deliver seamless solutions.
• Contributing to Synopsys’ leadership in silicon IP and embedded technology by delivering high-quality, scalable firmware.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Strong programming skills in C and familiarity with software development methodologies.
• Experience with scripting languages such as Perl, TCL, or Python.
• Proven experience in firmware development for complex embedded systems or high-speed interfaces.
• Excellent problem-solving and debugging skills, especially in unit testing and integration scenarios.
• Knowledge of high-speed interface protocols such as DDR, LPDDR (preferred).
• Experience with pre-silicon environments, including verification or emulation (preferred).

Who You Are:

• Analytical, detail-oriented, and committed to delivering high-quality results.
• Collaborative and effective communicator, able to work across diverse teams and disciplines.
• Adaptable and eager to learn new technologies and methodologies.
• Proactive, with a passion for innovation and continuous improvement.
• Inclusive and respectful, supporting a diverse and multicultural work environment.

The Team You’ll Be A Part Of:

You will join a vibrant Silicon IP engineering team dedicated to developing and integrating advanced firmware for high-speed interfaces. The team consists of experts in embedded systems, software, and hardware design, working together to solve complex challenges and deliver industry-leading solutions. Collaboration, innovation, and a commitment to excellence define the team’s culture as they support customers in bringing differentiated products to market quickly and efficiently.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted 02/24/2026

Category EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.

What You’ll Be Doing:

• Developing robust functional verification environments (test benches) for high-speed PHY IPs.
• Creating comprehensive test plans and detailed test cases to ensure thorough coverage.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Executing simulations, generating both random and focused stimuli, and performing coverage analysis to validate design functionality.
• Building architectural and micro-architectural understanding of complex digital design blocks under verification.
• Collaborating with cross-functional engineering teams to resolve issues and optimize verification strategies.
• Contributing to process improvements and sharing best practices within the team.

The Impact You Will Have:

• Accelerate the integration of advanced capabilities into SoCs, enabling customers to meet performance, power, and size requirements.
• Ensure the delivery of differentiated, high-quality silicon IP products with reduced risk and faster time-to-market.
• Drive innovation in verification methodologies that support the development of next-generation technologies, including AI, cloud, 5G, and IoT.
• Enhance the reliability and functionality of high-speed digital interfaces, powering smart devices across industries.
• Support Synopsys’ leadership in chip design and software security by maintaining rigorous verification standards.
• Contribute to a culture of inclusion and excellence, mentoring junior engineers and promoting diversity within the team.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Solid background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Experience with industry-standard development and verification tools and methodologies.
• Excellent diagnostic and problem-solving skills for identifying and resolving verification issues.
• Preferred: Experience with formal verification, System Verilog Assertions, and code/functional coverage implementation and analysis.
• Preferred: Familiarity with scripting languages such as Perl, TCL, and Shell scripting.
• Preferred: Knowledge of high-speed interface protocols such as DDR and LPDDR.

Who You Are:

• Detail-oriented and analytical thinker with a proactive approach to problem-solving.
• Effective communicator who thrives in collaborative and diverse team environments.
• Adaptable and eager to learn new technologies and methodologies.
• Resourceful and resilient in overcoming technical challenges.
• Committed to fostering inclusion, respect, and continuous improvement within the workplace.

The Team You’ll Be A Part Of:

You will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

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Workplace Resources, Sr Director

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.

You Are:

You are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.

What You’ll Be Doing:

• Developing functional verification environments (test benches) for complex digital design blocks.
• Creating comprehensive test plans and test cases to ensure thorough coverage and robust design validation.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Performing simulations, generating random and focused stimulus, and conducting coverage analysis to verify functionality.
• Building architecture and micro-architecture knowledge of digital blocks under test to drive effective verification strategies.
• Collaborating with cross-functional teams to share insights and resolve issues throughout the pre-silicon verification process.
• Utilizing industry-standard verification tools and methodologies to enhance efficiency and quality.

The Impact You Will Have:

• Ensuring the reliability and performance of high-speed PHY IPs through rigorous pre-silicon functional verification.
• Accelerating product time-to-market by identifying and resolving design issues early in the development cycle.
• Reducing risk for customers by delivering thoroughly verified and differentiated silicon IP solutions.
• Supporting the development of next-generation products that power innovations in AI, 5G, IoT, and more.
• Contributing technical expertise to the team, fostering a culture of continuous improvement and learning.
• Promoting collaboration and knowledge sharing across engineering teams to achieve collective goals.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Excellent diagnostic and problem-solving skills for debugging and optimizing verification flows.
• Experience with industry-standard development and verification tools and methodologies.
• Familiarity with scripting languages such as Perl, TCL, and Shell scripting (preferred).
• Experience with formal verification, System Verilog Assertions, and code/functional coverage analysis (preferred).
• Knowledge of high-speed interface protocols such as DDR and LPDDR (preferred).

Who You Are:

• Analytical thinker with a strong eagerness to learn and grow.
• Dynamic personality, energizing and motivating team members.
• Strong communicator, able to collaborate effectively in diverse environments.
• Self-motivated leader, capable of driving verification activities independently and as part of a team.
• Detail-oriented, ensuring thorough validation and quality in all deliverables.

The Team You’ll Be A Part Of:

You will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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The impact you will have is accelerating time-to-market for Synopsys customers through robust, automated design flows. You will elevate the quality, reliability, and scalability of EDA methodologies and toolchains across multiple projects and technology nodes. You will influence the roadmap and strategic direction of Synopsys' automation and methodology offerings. You will empower engineering teams with state-of-the-art tools, training, and support to maximize productivity and innovation. You will enhance collaboration between R&D, application engineers, and customers by standardizing best practices and methodologies. You will reduce engineering overhead and manual intervention through data-driven process improvements and automation.

You will need 10+ years of experience in EDA methodology, CAD automation, or semiconductor process development (analog, mixed-signal, or digital domains). You will have proven leadership, mentoring, and project management skills in a cross-functional engineering environment. You will have deep hands-on expertise with industry-standard EDA tools (e.g., Synopsys Custom Compiler, Cadence Virtuoso, Calibre, ICV, or similar). You will have strong programming and scripting skills in Python, Perl, TCL, Shell, SKILL, or related languages, with a focus on automation and tool integration.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.

A technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.

You bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You'll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Mentoring and coaching engineering teams, fostering technical excellence and knowledge sharing across the organization.
• Collaborating with cross-functional groups and customers to resolve challenges, ensure quality design, and meet aggressive project milestones.
• Driving continuous improvement in functional and performance testing on hardware and test-chips, and leading architectural refinements based on analysis.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Driving cross-team synergy, technical mentorship, and a culture of continuous learning and inclusivity.
• Directly impact customer success by providing expert guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You'll Need:

• 15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.

• Be results driven

• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.

• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.

• In-depth knowledge of system-level validation for high-speed interface PHY

• Proven track record of working cross-functionally and driving issues to closure

• Knowledge of mixed-signal design

• Experience in working in cross-functional collaborations

• Be an excellent communicator and a beacon for change

• Excellent debugging, analytical, and problem-solving skills

• Working knowledge of scripting in languages such as Python and/or Perl

• Good understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon

• Good interpersonal skills, ability & desire to work as a standout colleague

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness
• Time Away
• Family Support
• ESPP
• Retirement Plans
• Compensation

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You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.

What You’ll Be Doing:

• Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.
• Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.
• Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.
• Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.
• Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
• Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.
• Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.

The Impact You Will Have:

• Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.
• Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.
• Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.
• Enhance the efficiency and productivity of the design team through automation and process improvements.
• Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.
• Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.

What You’ll Need:

• Master’s degree in Electrical/Electronic Engineering or a related field.
• Strong understanding of CMOS-based block level circuit design and SRAM architectures.
• Solid grasp of digital circuit design and VLSI process concepts.
• Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.
• Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.
• Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.
• Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.

Who You Are:

• Innovative thinker with a strong desire to learn and explore new technologies.
• Detail-oriented and analytical, capable of tackling complex technical challenges.
• Collaborative team player who values diverse perspectives and open communication.
• Effective communicator able to present ideas clearly and work across global teams.
• Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.
• Proactive problem solver who takes ownership of projects and drives results.

The Team You’ll Be A Part Of:

You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.

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Responsibilities:

• Set up specific environments and tools for localization
• Identify and extract localizable content from complex formats
• Convert final translated assets back to original formats
• Automate asset transfer from and to customers portals
• Troubleshooting issues coming from production, originating from translation process
• Contribute actively to the design, development and deployment of new production processes
• Development of tools for production
• Customize localization workflows and facilitate integration of localization tools with different source content repositories
• Review and anticipate potential globalization issues for new features, locales and technology
• Analysis of web sites and applications for localization potential and time/material requirements
• Ensure compliance with clients requirements and integrity of data
• Provide support to operations and sales management
• Work with other developers and engineers to implement technical solutions for end-to-end localization processes
• Review business requirements and identify technical design that is required to meet the business needs

Benefits:

• Full-time, permanent employment
• In-office working pattern
• Support services employment type
• IT & Infosec area of work

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Responsibilities:

• Set up specific environments and tools for localization
• Identify and extract localizable content from complex formats
• Convert final translated assets back to original formats
• Automate asset transfer from and to customers' portals
• Troubleshoot issues coming from production, originating from translation process
• Contribute actively to the design, development, and deployment of new production processes
• Develop tools for production
• Customize localization workflows and facilitate integration of localization tools with different source content repositories
• Review and anticipate potential globalization issues for new features, locales, and technology
• Analyze web sites and applications for localization potential and time/material requirements
• Ensure compliance with clients' requirements and integrity of data
• Provide support to operations and sales management
• Work with other developers and engineers to implement technical solutions for end-to-end localization processes
• Review business requirements and identify technical design that is required to meet the business needs

Requirements:

• University degree in computer science or equivalent background
• At least 2 to 3 years experience in software development
• Knowledge of programming languages (VB, VBA, C#, Java), scripting (Python, Perl, JavaScript) and markup languages (XML, HTML, XLIFF); confidence with API programming
• Experience writing SQL queries is a plus
• Advanced knowledge of regular expressions and text manipulation
• Excellent knowledge of most important CAT tools on the market (memoQ, XTM, Memsource, Wordbee, etc.)
• Advanced knowledge of internationalization good practices and experience with internationalization of web and mobile applications
• Knowledge of multilingual localization issues and procedures (managing characters set and encoding, text direction, text strings sorting and handling)
• Knowledge of Machine Translation technology is a plus
• Able to communicate effectively with stakeholders who have varying levels of technical expertise
• Fluent in English
• Passion for global solutions, international customers, and teamwork
• Focus on automation
• Good problem-solving skills combined with strong analytical abilities to find creative solutions
• Team player
• Strong time management, organizational, and support skills
• Strongly service-oriented, to efficiently support internal and external customers

Benefits:

• Company Pension Scheme
• Private Medical Insurance Scheme
• Employee Share Scheme
• Annual Bonus

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You are a passionate and versatile engineering professional who thrives in a dynamic, fast-paced environment. With a deep technical acumen and a knack for creative problem-solving, you are driven to deliver innovative solutions that address complex challenges. You have a proven track record in application engineering, accompanied by a strong understanding of EDA tools, chip design flows, and customer-centric solution delivery.

Responsibilities

• Collaborating with customers to understand their technical challenges and providing comprehensive solutions using Synopsys tools and platforms.
• Driving the adoption and integration of EDA tools in customer design flows, ensuring optimal utilization and performance.
• Developing and delivering technical workshops, training sessions, and product demonstrations tailored to customer needs.
• Partnering with R&D and product management teams to influence product direction and resolve complex technical issues.
• Authoring and maintaining technical documentation, application notes, and best practice guides.
• Providing pre- and post-sales technical support, including troubleshooting, bug tracking, and solution development.
• Mentoring and guiding junior engineers, fostering a culture of technical excellence and innovation.

Impact

• Accelerating customer success by ensuring seamless deployment and integration of Synopsys solutions.
• Enhancing product quality and usability through direct feedback and collaboration with R&D teams.
• Expanding Synopsys' footprint in key accounts by demonstrating technical excellence and building strong customer relationships.
• Reducing design cycle times and improving overall productivity for our customers.
• Contributing to the growth of Synopsys' technical community through knowledge sharing and mentoring.
• Influencing future product innovations by identifying emerging customer needs and market trends.

Requirements

• Strong expertise in ASIC/FPGA design and verification methodologies.
• Hands-on experience with industry-leading EDA tools such as synthesis, simulation, and formal verification platforms.
• Proficiency in scripting languages (e.g., Python, Perl, TCL) and automation frameworks.
• Solid understanding of digital design, SoC architectures, and semiconductor manufacturing processes.
• Ability to analyze and resolve complex technical issues quickly and effectively.

Team

You'll join an accomplished team of application engineering experts at the forefront of EDA and semiconductor innovation. Our team partners closely with customers, R&D, and product management to deliver world-class solutions and technical support. We foster a collaborative, inclusive culture that encourages continuous learning, knowledge sharing, and professional growth.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15995

Remote Eligible

No

Date Posted

03/05/2026

Alternate Job Titles:

• Staff ASIC Digital Design Engineer

• Staff DFT Engineer

• Staff SoC Testability Engineer

We Are:

At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.

You Are:

You are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.

What You’ll Be Doing:

• Define and implement DFT architecture for IP designs

• Perform SCAN insertion and ATPG simulation

• Analyze and improve test coverage

• Develop STA DFT timing constraints

• Prepare DFT integration guidelines for SoC

• Conduct quality checks and FMEDA/DFMEA analysis

The Impact You Will Have:

• Enhance product reliability and quality

• Support functional safety standards (ISO26262, FUSA)

• Streamline SoC integration

• Reduce debug cycles and time-to-market

• Mentor peers

• Drive innovation in test methodology

What You’ll Need:

• BS/MS/PhD in Electronics or related field

• 5+ years DFT design experience

• Expertise in Scan insertion, ATPG, JTAG

• Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)

• Scripting (Perl, TCL, Python) is a plus

Who You Are:

• Responsible and collaborative

• Excellent English communication

• Team player and problem solver

The Team You’ll Be A Part Of:

Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are: You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

Responsibilities: Develop and validate DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team. Stay up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Impact: Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. Contribute to the development of next-generation verification methodologies and best practices within Synopsys. Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

Requirements: B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field. 5-8 years of hands-on experience in the Physical Verification (PV) domain. Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS. Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development. Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements. Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks. Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are: An analytical thinker with strong problem-solving abilities and meticulous attention to detail. A collaborative team player who fosters knowledge sharing and mentorship. Effective communicator, capable of translating technical concepts to diverse audiences. Adaptable and proactive, with a passion for continuous learning and innovation. Customer-focused, with a commitment to delivering high-quality solutions on time. Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You’ll Be A Part Of: You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

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What you'll do

• Reviewing and analyzing customer and partner feedback to enhance product and solution performance.
• Collaborating with R&D to shape technical roadmaps, specifications, and validation processes for product improvements.
• Diagnosing, troubleshooting, and resolving complex technical issues on-site and remotely for customer installations.

What you need

• BS or MS in Electrical or Computer Engineering.
• 6-8 years of relevant experience in the semiconductor industry.
• Hands-on expertise with Place & Route (P&R), extraction, Static Timing Analysis (STA), and Engineering Change Order (ECO) tools.

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What you'll do

• Design and implement SoC solutions using Synopsys EDA tools and IP.
• Advise customer design and CAD teams.

What you need

• BS/MS/PhD in relevant engineering fields.
• 7+ years in Place & Route with Fusion Compiler/ICC2.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

• Develop firmware for next-generation PAM4 Serdes spanning multiple protocols like PCIe and Ethernet.
• Collaborate closely with systems, analog design, digital design, verification, and lab teams during firmware development and debugging.

What you need

• Bachelor’s, Master’s, or PhD degree in Computer Engineering, Electrical Engineering, or equivalent with relevant industry experience.

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What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

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What you'll do

• Providing expert support and training to customers on PrimeTime, PrimeClosure, and PrimeShield, ensuring optimal use and maximum productivity.
• Independently coordinating and supporting multiple customer designs through tape-out, verifying designs meet or exceed customer expectations.

What you need

• Bachelor’s degree in Electrical Engineering with a minimum of 12 years of experience, or a Master’s degree with at least 8 years of experience.
• In-depth understanding of timing, power, statistical and electromigration characterization, and signal integrity in advanced SoC design.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.

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What you'll do

As a HBM Design Verification Engineer, Principal, you will be responsible for developing verification strategies and plans for ASIC/SoC projects, defining and implementing testbench architecture and methodologies, building testbench infrastructure and verification components, and creating verification item lists, coverage models, and checkers.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 10–15+ years of relevant experience

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What you'll do

• Partnering with design teams to define verification requirements
• Developing test plans from specifications
• Building and maintaining UVM testbenches and agents

What you need

• B.Sc./M.Sc. in a relevant engineering field
• 10+ years in ASIC/UVM verification

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What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 7 to 10+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Exposure to Verilog/System Verilog and AMS concepts or circuit design (coursework, labs, or hands-on experience).

Why this matters

As a Mixed-Signal AMS Co-Simulation Verification Engineer, you will play a critical role in ensuring the quality and reliability of our high-performance SERDES and mixed-signal IP, which powers AI, automotive, cloud, and mobile applications at massive scale.

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What you'll do

• Collaborating with R&D teams to drive product development and advanced HPC reference flow development for wide deployment.
• Demonstrating differentiated PPA results on CPU/GPU/NPU designs to showcase our technology's superiority.

What you need

• BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience.
• Hands-on experience with synthesis and place and route (P&R) tools.

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What you'll do

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.

What you need

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.

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What you'll do

As a Sr Staff Engineer, you will be responsible for designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.

What you need

• MS/PhD in Computer Science, Electrical Engineering, or related field from a reputed institute, with 10+ years of relevant experience.
• Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.
• Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.
• Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.
• Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).
• Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Why this matters

• Accelerate the development of industry-leading prototyping systems, enabling faster time-to-market for cutting-edge ASIC designs.
• Enhance the functionality and reliability of Synopsys' HAPS and ProtoCompiler products through innovative hardware and software solutions.
• Drive customer satisfaction by delivering robust, scalable, and user-friendly prototyping tools that meet diverse engineering needs.
• Contribute to Synopsys' reputation as a leader in verification and prototyping technology, influencing industry standards and practices.

What you'll be doing

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.
• Developing and maintaining complex EDA software for high-performance prototyping systems.
• Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.
• Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.
• Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.
• Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.
• Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.
• Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.

Why you'll love this role

• Opportunity to work on cutting-edge projects and technologies.
• Collaborative and dynamic work environment.
• Professional growth and development opportunities.
• Recognition and rewards for outstanding performance.
• Comprehensive benefits and compensation package.

What you'll need to succeed

• Strong technical skills and knowledge in digital design, verification, and prototyping.
• Excellent problem-solving and debugging skills.
• Strong communication and collaboration skills.
• Ability to work independently and as part of a team.
• Adaptability and flexibility in a fast-paced environment.

How to apply

• If you're ready to make a meaningful impact and help shape the next generation of prototyping systems, Synopsys is the place for you.
• Apply now to join our team of talented engineers and contribute to the development of industry-leading prototyping solutions.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• Time away, including company holidays, ETO, and FTO programs.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP, with a 15% discount on Synopsys common stock.
• Retirement plans, varying by region and country.
• Competitive salaries.

How we hire

• We're proud to be an equal opportunities employer and welcome applications from diverse candidates.
• Our hiring process typically involves a phone screen, followed by an interview with the hiring team.
• We're committed to providing a supportive and inclusive work environment, where everyone has the opportunity to grow and succeed.

Join our team

• If you're passionate about innovation and technology, and want to be part of a dynamic and collaborative team, apply now to join Synopsys.
• We can't wait to hear from you!

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What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 2 - 4 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 6-12 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

• Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).
• Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

What you need

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
• 3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).
• Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

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What you'll do

Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.

• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.

• Drive flow development and optimization to improve design quality and predictability.

• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).

• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.

• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.

• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.

What you need

• Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why this matters

Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.

Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.

Enhance the predictability and simplicity of implementation processes for complex interface IPs.

Accelerate the adoption of next-generation design technologies and tools across the industry.

Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.

Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.

What you’ll need

• Minimum 7years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why you’ll love this role

• Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.

• Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.

• Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.

• Participate in professional development opportunities to enhance your skills and expertise.

• Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

• In addition to company holidays, we have ETO and FTO Programs.

• Family Support

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

• Save for your future with our retirement plans that vary by region and country.

• Compensation

• Competitive salaries.

• Awards

• We're proud to receive several recognitions.

• Explore the Possibilities with Synopsys

• Search Synopsys Careers

• Join our Talent Community

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What you'll do

As a Staff Engineer, you will be responsible for designing and developing advanced embedded memories (SRAM, ROM, Register File).

• Design and develop advanced embedded memories (SRAM, ROM, Register File).
• Lead circuit implementation, simulation, and layout supervision.
• Collaborate with CAD and frontend teams for compiler automation and verification.
• Drivebitcell development and reliability analysis.
• Mentor junior engineers and lead projects.

What you need

• Bachelor’s/Master’s in Electrical Engineering or related field.
• 5-8 years’ experience in embedded CMOS memory design.
• Expertise in SRAM bit cell design, testing, and analysis.
• Proficiency with layout, simulation, and verification tools.
• Programming in C-Shell, Perl; C++/JavaScript a plus.

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What you'll do

You will be responsible for independently owning and driving full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.

• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.

What you need

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.

• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).

• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.

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What you'll do

Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.

• Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.

What you need

• MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.

Why this matters

Advance high-speed connectivity for enterprise and hyperscale applications worldwide.

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What you'll do

• Work close with customers to understand new requests or customization feature from customer’s PRD/MRD
• Provide integration training to customers and conduct reviews on their major SoC milestones
• Provide feedback to Synopsys R&D for customization feature or continuous IIP product improvements
• Participate in IIP design reviews to align development with future customer needs
• Creativity and Innovation is highly inspired: such as developing small tools to simplify daily jobs or improving efficiency; authoring application notes for gate-level simulation, silicon debug and physical implementation.

What you need

• Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science
• Minimum 5 years of Analog or Mixed signal IP or ASIC Design/Verification/Applications experience is required
• Hands-on experience on circuit design, RTL coding, simulation, synthesis, static timing check, equivalence check, etc.
• Domain knowledge PCI Express, CXL, Ethernet protocols
• Creative results are oriented with the ability to manage multiple tasks concurrently.
• Good verbal and written communication skills in English and ability to interact with customer
• High degree of self-motivation and personal responsibility
• Good inference, reasoning and problem-solving skills, and attention to details

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What you'll do

Intro.

• Performs development activities, including the design, implementation, maintenance, testing and documentation of software modules and sub-systems
• Learns and employs best practices
• Performs bug verification, release testing and beta support for assigned products
• Researches problems discovered by QA or product support and develops solutions

What you need

• BS in Electrical Engineering, or related field with 5 years’ experience
• Experience with EDA solution, EDA companies, semiconductor design companies, semiconductor foundries

Why this matters

One paragraph about career impact and value.

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What you'll do

You will serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling. You will provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.

• Serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling.
• Provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.
• Lead product demonstrations, evaluations, and proof-of-concept projects that showcase PrimeLib's capabilities in real-world scenarios.

What you need

• BS/MS in Electrical Engineering, Computer Engineering, or a related field (PhD preferred).
• 8+ years of experience in semiconductor design, library characterization, or EDA application engineering.
• Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries.
• Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators.
• Advanced scripting skills (Python, Perl, TCL) for automation and flow customization.
• Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models).
• Excellent verbal and written communication skills, with a proven ability to present complex technical concepts to varied audiences.

Why this matters

Accelerate customer adoption and success with PrimeLib, directly influencing the design of next-generation semiconductor products.

What you’ll be doing

• Serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling.
• Provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.
• Lead product demonstrations, evaluations, and proof-of-concept projects that showcase PrimeLib's capabilities in real-world scenarios.
• Troubleshoot and resolve complex technical challenges related to timing, power, and signal integrity modeling.
• Collaborate with R&D and product teams to influence the PrimeLib roadmap, advocating for customer needs and emerging technology trends.
• Develop and deliver technical training, best practices, and documentation to empower both customers and internal teams.
• Represent Synopsys and PrimeLib at industry conferences, technical forums, and customer workshops.

The Impact You Will Have

• Accelerate customer adoption and success with PrimeLib, directly influencing the design of next-generation semiconductor products.
• Drive technical excellence and innovation by bridging customer requirements and R&D advancements.
• Enhance Synopsys’ reputation as a trusted technology partner and thought leader in library characterization and EDA solutions.
• Shape the evolution of PrimeLib by capturing and relaying key customer insights to product development teams.
• Facilitate knowledge sharing and best practices that elevate the capabilities of customers and colleagues alike.
• Promote the adoption of advanced semiconductor process technologies through expert technical support and guidance.
• Build lasting relationships with Tier-1 semiconductor companies and industry leaders.

What You’ll Need

• BS/MS in Electrical Engineering, Computer Engineering, or a related field (PhD preferred).
• 8+ years of experience in semiconductor design, library characterization, or EDA application engineering.
• Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries.
• Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators.
• Advanced scripting skills (Python, Perl, TCL) for automation and flow customization.
• Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models).
• Excellent verbal and written communication skills, with a proven ability to present complex technical concepts to varied audiences.

The Team You’ll Be A Part Of

You will join a dynamic, high-impact Customer Application Services team focused on enabling customer success with Synopsys’ PrimeLib product. Our team works closely with R&D, product management, and global customers to deliver technical excellence, foster innovation, and drive the adoption of industry-leading library characterization solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP.
• Planning tests, checklists, coverage, and assertion planning.
• Creating detailed verification environments from functional specifications.
• Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
• Writing test cases, checkers, and coverage that implement the verification test plan.
• Debugging simulations, including those of real signals modeled using SystemVerilog for analog.
• Performing RTL, GLS, and co-simulations and ensuring coverage closure.
• Participating in technical reviews and contributing actively.
• Providing customer support with the bring-up of IP in customer simulation environments.
• Following and improving development processes to ensure high-quality output.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
• 8+ years of experience in design verification.
• Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).
• Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.
• Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

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What you'll do

Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.

Performing verification tasks for IP cores, including test planning and environment coding at both unit and system levels.

Developing and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.

Managing regression and ensuring adherence to verification methodologies.

Collaborating closely with RTL designers and a global team of verification engineers.

Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

What you need

BSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.

Experience in architecting verification environments for complex serial protocols.

Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.

Expertise in verification methodologies such as VMM, OVM, and UVM.

Knowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.

Familiarity with Verilog and scripting languages such as Perl, TCL, and Python.

Experience with IP design and verification processes, including VIP development.

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What you'll do

Develop reusable verification environments and testbenches using UVM.

• Plan, maintain, and execute verification strategies for ASIC/SoC projects.

• Create test cases, set up and run regressions, and close coverage.

What you need

Minimum 6 years' SoC/ASIC verification experience.

• Strong SystemVerilog (UVM preferred) skills.

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What you'll do

Working on Functional Verification and Design Implementation.

• Using tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools.

• Leveraging your understanding of advanced process nodes.

• Utilizing your scripting skills to automate processes.

What you need

BS with 3-5 years of direct hands-on experience.

• Proficiency in design closure.

• Experience with tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools will be added value.

• Knowledge of Python, Perl, and TCL scripting languages.

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