The Air Dominance and Strike Aerodynamics Engineering Team is responsible for the advanced aerodynamic design and analysis for Group 5 air vehicles and missile platforms. As a Senior Aerodynamics Engineer, you will own the full development lifecycle, from conceptual design to flight test planning, execution, and analysis, ensuring high-performance, resilient, and scalable systems that meet the demands of complex, contested environments.

RESPONSIBILITIES

• Aerodynamic design of unmanned air vehicles/missiles at conceptual, preliminary, and detail design maturities
• Aerodynamic analysis of unmanned air vehicles, using both low and high order methods, including analysis tool development and improvement as needed
• Stability and control analysis
• Aircraft performance modeling and simulation
• Aerodynamic loads generation
• Wind tunnel test planning, execution, and analysis
• Flight test planning, execution, and analysis

REQUIRED QUALIFICATIONS

• BS or higher degree in Aerospace Engineering
• 8+ work experience as an individual contributing engineer
• Experience with aircraft performance and analysis predictions
• Competent in a variety of aerodynamic analysis techniques including hand calculations, vortex, lattice methods, panel methods, and computational fluid dynamics (CFD)
• Wind tunnel and flight test experience including data acquisition, data analysis, and project coordination
• Strong programming skills in higher-level languages (e.g., MATLAB, Python) for internal tool development in a version-controlled environment
• Experience preparing formal documentation (i.e., specifications, test procedures, technical reports, etc.)
• Passion for defending the United States and her allies
• Eligible to obtain and maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• StarCCM+ experience
• Ice accretion or icing analysis experience
• Missile DATCOM, OTIS, or DYMOS
• Experience with transonic and supersonic flow regimes
• Active U.S. Secret security clearance

BENEFITS

Anduril offers top-tier benefits for full-time employees, including:

• Healthcare Benefits
• Income Protection
• Generous time off
• Family Planning & Parenting Support
• Mental Health Resources
• Professional Development
• Commuter Benefits
• Relocation Assistance
• Retirement Savings Plan

PROTECTING YOURSELF FROM RECRUITMENT SCAMS

Anduril is committed to maintaining the integrity of our Talent acquisition process and the security of our candidates. We've observed a rise in sophisticated phishing and fraudulent schemes where individuals impersonate Anduril representatives, luring job seekers with false interviews or job offers. These scammers often attempt to extract payment or sensitive personal information.

To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind:

• No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. Our legitimate recruitment is entirely free for candidates.
• Please always verify communications:
• Direct from Anduril: If you receive an email from one of our recruiters, it will only come from an @anduril.com address.
• Via Agency Partner: If contacted by a recruiting agency for an Anduril role, their email will clearly identify their agency. If you suspect any suspicious activity, please verify the agency's authenticity by reaching out to contact@anduril.com.
• Exercise Caution with Unsolicited Outreach: If you receive any communication that appears suspicious, contains grammatical errors, or makes unusual requests, do not engage. Always confirm the sender's email domain is @anduril.com before providing any personal information or clicking on links.
• What to Do If You Suspect Fraud: Should you encounter any questionable or fraudulent outreach claiming to be from Anduril, please report it immediately to contact@anduril.com. Your proactive caution is invaluable in protecting your personal information and upholding the security and trustworthiness of our recruitment efforts.

DATA PRIVACY

Anduril is committed to protecting the privacy of our candidates and employees. We collect and use personal data in accordance with applicable laws and regulations. For more information, please refer to our Privacy Policy.

We are an equal opportunities employer and welcome applications from diverse candidates. We are committed to creating an inclusive workplace where everyone feels valued, respected, and supported.

If you have any questions or concerns about this role or our application process, please don't hesitate to reach out to us at contact@anduril.com.

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This position is ideal for a mechanical or aerospace engineer with a passion for cutting-edge aircraft design, multi-disciplinary systems integration, and iterative prototyping in a fast-paced defense technology environment.

Responsibilities:

Assist in the conceptual and preliminary design of Shield AI's UAV platforms, ensuring optimal aerodynamic and structural configurations. Support aircraft sizing, weight estimation, and trade studies to evaluate different airframe configurations. Work with multi-disciplinary engineering teams (mechanical, electrical, propulsion, avionics) to ensure seamless system integration. Develop and refine 3D CAD models of aircraft structures, subsystems, and flight-critical components. Perform basic aerodynamic and structural analysis using computational tools to assess feasibility and performance impacts. Participate in design reviews, system trade studies, and prototype development efforts. Support rapid prototyping and wind tunnel testing of scaled models to validate design concepts. Assist in requirements development, documentation, and verification planning for aircraft subsystems. Ensure designs comply with manufacturing feasibility, mission requirements, and aerospace industry standards. Work closely with manufacturing and production teams to transition designs from concept to prototype and full-scale production.

Required qualifications:

Bachelor's degree in Aerospace, Mechanical, or Systems Engineering (or related field). 5 years of experience in aircraft design, configuration layout, or airframe integration. Proficiency in CAD modeling (NX, SolidWorks, or similar) for airframe and structural design. Basic understanding of aircraft aerodynamics, structures, and propulsion system integration. Ability to perform basic FEA, CFD, or weight & balance assessments. Strong problem-solving skills, attention to detail, and ability to work in cross-functional teams. Excellent communication and technical documentation skills. Active Secret clearance

Preferred qualifications:

Master's degree in Aerospace, Mechanical, or Systems Engineering (or related field). Experience with unmanned aerial vehicle (UAV) design or aircraft conceptual design. Familiarity with aircraft performance modeling, stability & control, and flight dynamics. Hands-on experience with rapid prototyping, wind tunnel testing, or flight hardware development. Knowledge of manufacturing techniques, composite materials, and aerospace structural design principles. Experience working in a fast-paced, high-tech startup or defense environment. Active TS clearance or ability to gain a TS clearance.

$136,730 - $205,096 a year

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We currently have 614 open roles

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a technically accomplished and strategically minded architect who thrives at the intersection of technology and business. You bring a deep passion for power and performance analysis technologies and system-level validation, and are adept at translating complex technical concepts into actionable product strategies and compelling business opportunities.

Drive the full lifecycle of power and performance analysis solutions,from ideation and design through development, launch, and market adoption.

Develop and execute long-term product and technology roadmaps that align with customer needs and corporate strategy.

Serve as the domain and product expert for power and performance analysis solutions, with a focus on use-case-driven development.

Develop Product Requirements Documents (PRDs) based on customer use cases and translate them into detailed feature definitions in collaboration with Product Engineering (PE) and Product Management (PM) teams.

Guide product management on release content, prioritization, and readiness reviews in coordination with R&D and PE teams.

Define and co-create Application Engineering (AE) training materials for use case enablement.

Conduct technical win/loss analyses and competitive benchmarking to inform product positioning and roadmap decisions.

Create technical collateral including blogs, whitepapers, demos, and presentations to support go-to-market efforts.

Engage with customers and field teams to gather feedback, validate product direction, and ensure alignment with market needs.

Lead strategic initiatives and cross-functional projects that deliver measurable business impact.

Shape the strategic direction and long-term success of Synopsys’ Power and Performance Analysis Solutions portfolio.

Drive customer-centric innovation that positions Synopsys as a market leader in power modeling and validation technologies.

Influence industry standards and market trends through active participation in technical forums and standards bodies.

Accelerate revenue growth by identifying new market opportunities and developing effective go-to-market strategies.

Enhance cross-functional collaboration, ensuring seamless product execution and high customer satisfaction.

Foster a culture of innovation, learning, and continuous improvement within the organization.

Build strategic partnerships and new market entry models to differentiate Synopsys’ offerings.

Anticipate and address future market needs, ensuring ongoing competitiveness and relevance.

Deep technical expertise in power & performance modeling, emulation platforms, RTL simulation, and power-aware design flows.

5+ years of experience in technical product management, preferably in EDA, semiconductor, or system design domains.

Proven ability to define and execute product strategies based on technical use cases and market trends.

Strong analytical skills, with experience in market analysis, business planning, and competitive assessment.

Excellent verbal and written communication skills, including the ability to present and influence at all organizational levels.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (MBA preferred).

A collaborative and inclusive leader who inspires trust and drives results through cross-functional teamwork.

Strategic thinker with the ability to anticipate future trends and proactively shape product direction.

Customer-focused, with a passion for understanding and solving complex customer challenges.

Excellent communicator, adept at tailoring messages to diverse audiences and building strong relationships.

Resilient, adaptable, and comfortable navigating ambiguity in a fast-paced, dynamic environment.

Committed to fostering a culture of learning, innovation, and continuous improvement.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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About the Team

We build foundational AI infrastructure that enables large-scale training and inference across diverse workloads and rapidly evolving hardware generations. Our work directly shapes how AI systems are designed, deployed, and scaled today and into the future. Engineers on this team operate with end-to-end ownership, deep technical rigor, and a strong bias toward real-world impact.

Microsoft Superintelligence Team

Microsoft Superintelligence team’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

This role is part of Microsoft AI’s Superintelligence Team. The MAIST is a startup-like team inside Microsoft AI, created to push the boundaries of AI toward Humanist Superintelligence—ultra-capable systems that remain controllable, safety-aligned, and anchored to human values. Our mission is to create AI that amplifies human potential while ensuring humanity remains firmly in control. We aim to deliver breakthroughs that benefit society—advancing science, education, and global well-being. We’re also fortunate to partner with incredible product teams giving our models the chance to reach billions of users and create immense positive impact. If you’re a brilliant, highly-ambitious and low ego individual, you’ll fit right in—come and join us as we work on our next generation of models!

Responsibilities

Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks. Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements. Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems. Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps. Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations. Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs. Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams. Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

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We pursue this mission through deep hardware–software co-design, combining rigorous systems thinking with hands-on engineering. The team invests heavily in understanding real production workloads large-scale training, inference, and emerging multimodal models and translating those insights into concrete improvements across the stack: from kernels, runtimes, and distributed systems, all the way down to silicon-level trade-offs and datacenter-scale architectures.

This role sits at the boundary between exploration and production. You will work closely with internal infrastructure, hardware, compiler, and product teams, as well as external partners across the hardware and systems ecosystem. Our operating model emphasizes rapid ideation and prototyping, followed by disciplined execution to drive high-leverage ideas into production systems that operate at massive scale.

In addition to delivering real-world impact on large-scale AI platforms, the team actively contributes to the broader research and engineering community. Our work aligns closely with leading communities in ML systems, distributed systems, computer architecture, and high-performance computing, and we regularly publish, prototype, and open-source impactful technologies where appropriate.

Microsoft Superintelligence Team Microsoft Superintelligence team’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

This role is part of Microsoft AI’s Superintelligence Team. The MAIST is a startup-like team inside Microsoft AI, created to push the boundaries of AI toward Humanist Superintelligence—ultra-capable systems that remain controllable, safety-aligned, and anchored to human values. Our mission is to create AI that amplifies human potential while ensuring humanity remains firmly in control. We aim to deliver breakthroughs that benefit society—advancing science, education, and global well-being. We’re also fortunate to partner with incredible product teams giving our models the chance to reach billions of users and create immense positive impact.

Responsibilities Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks.

Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements.

Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems.

Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps.

Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations.

Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs.

Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams.

Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

Qualifications Bachelor’s Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Additional or Preferred Qualifications Master’s Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR Bachelor’s Degree in Computer Science or related technical field AND 12+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Strong background in one or more of the following areas: AI accelerator or GPU architectures Distributed systems and large-scale AI training/inference High-performance computing (HPC) and collective communications ML systems, runtimes, or compilers Performance modeling, benchmarking, and systems analysis Hardware–software co-design for AI workloads Proficiency in systems-level programming (e.g., C/C++, CUDA, Python) and performance-critical software development.

Proven ability to work across organizational boundaries and influence technical decisions involving multiple stakeholders. Experience designing or operating large-scale AI clusters for training or inference. Deep familiarity with LLMs, multimodal models, or recommendation systems, and their systems-level implications. Experience with accelerator interconnects and communication stacks (e.g., NCCL, MPI, RDMA, high-speed Ethernet or InfiniBand). Background in performance modeling and capacity planning for future hardware generations. Prior experience contributing to or leading hardware roadmaps, silicon bring-up, or platform architecture reviews. Publications, patents, or open-source contributions in systems, architecture, or ML systems are a plus.

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As a Paid Acquisition Specialist at Cursor, you will be responsible for owning and scaling paid acquisition across various channels, including Google Ads, LinkedIn, Meta, Reddit, YouTube, and emerging developer-focused platforms. Your primary goal will be to build and optimize full-funnel campaigns that drive qualified signups, pipeline, and revenue, not just clicks.

You will develop channel strategy across search, paid social, retargeting, and experimentation budgets, and test ad copy and creative angles tailored to technical audiences. You will also partner closely with creative, content, and product marketing to ship high-performing ad concepts and landing page iterations.

Your responsibilities will include managing campaign structure, keyword strategy, audience segmentation, and bidding to improve CAC and payback. You will own measurement and attribution, with support from ops and engineering: tracking setup, conversion quality, offline conversion imports, and incrementality testing.

You will analyse performance trends and communicate results clearly through dashboards, reporting, and weekly insights. You will run structured experiments to identify new growth levers (new audiences, formats, offers, onboarding flows), and collaborate with sales, lifecycle, and data teams to improve lead quality and conversion rates downstream.

You may be a fit if

We are actively hiring for both senior and junior roles. To be a good fit for this position, you should have proven ability to manage meaningful monthly budgets and scale spend efficiently while maintaining performance.

You should have deep expertise in Google Ads (Search, YouTube, Performance Max) and at least one major paid social platform. You should also have strong understanding of funnel metrics: CAC, LTV, payback period, and conversion rates.

Experience with analytics and attribution tools is also required. You should have highly analytical mindset with comfort in spreadsheets, cohort analysis, and performance modeling. You should be able to move fast, test often, and iterate based on data and user insight.

Benefits

• Competitive salary
• Opportunity to work with a talented team
• Flexible working hours
• Professional development opportunities

How to apply

To apply for this position, please submit your resume, cover letter, and any relevant work samples. We look forward to hearing from you!

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Design Verification Engineer

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry-standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $342K – $555K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

As an Engineer on our hardware optimization and co-design team, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and machine learning engineers to understand their unique needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with various vendors to develop and influence future hardware architectures towards efficient training and inference on our models. If you are excited about efficiently distributing a large language model across devices, dealing with and optimizing system-wide/rack-wide networking bottlenecks and eventually tailoring the compute pipe and memory hierarchy of the hardware platform, simulating workloads at different abstractions and working closely with our partners, this is the perfect opportunity!

In this role, you will:

• Co-design future hardware for programmability and performance with our hardware vendors

• Assist hardware vendors in developing optimal kernels and add support for it in our compiler

• Develop performance estimates for critical kernels for different hardware configurations and drive decisions on compute core and memory hierarchy features

• Build system performance models at different abstraction levels and carry out analysis to drive decisions on scale up, scale out, front end networking

• Work with machine learning engineers, kernel engineers and compiler developers to understand their vision and needs from high performance accelerators

• Manage communication and coordination with internal and external partners

• Influence the roadmap of hardware partners to optimize them for OpenAI’s workloads.

• Evaluate potential partners’ accelerators and platforms.

• As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.

You might thrive in this role if you have:

• 4+ years of industry experience, including experience harnessing compute at scale and optimizing ML platform code to run efficiently on target hardware.

• Strong experience in software/hardware co-design

• Deep understanding of GPU and/or other AI accelerators

• Experience with CUDA, Triton or a related accelerator programming language

• Experience driving Machine Learning accuracy with low precision formats

• Experience with system performance modeling and analysis to optimize ML model deployment

• Strong coding skills in C/C++ and Python

• Are familiar with the fundamentals of deep learning computing and chip architecture/microarchitecture.

These attributes are nice to have:

• PhD in Computer Science and Engineering with a specialization in Computer Architecture, Parallel Computing. Compilers or other Systems

• Strong understanding of LLMs and challenges related to their training and inference

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $295K – $380K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

The Kernels team at OpenAI builds the low-level software that accelerates our most ambitious AI research.

We work at the boundary of hardware and software, developing high-performance kernels, distributed system optimizations, and runtime improvements to make large-scale training and inference more efficient.

Our work enables OpenAI to push the limits by ensuring models - from LLMs to recommender systems - to run reliably on advanced supercomputing platforms. That includes adapting our software stack to new types of accelerators, tuning system performance end-to-end, and removing bottlenecks across every layer of the stack.

About the Role

On the Accelerators team, you will help OpenAI evaluate and bring up new compute platforms that can support large-scale AI training and inference.

Your work will range from prototyping system software on new accelerators to enabling performance optimizations across our AI workloads.

You’ll work across the stack, collaborating with both hardware and software aspects - working on kernels, sharding strategies, scaling across distributed systems, and performance modeling.

You'll help adapt OpenAI's software stack to non-traditional hardware and drive efficiency improvements in core AI workloads. This is not a compiler-focused role, rather bridging ML algorithms with system performance - especially at scale.

In this role, you will:

• Prototype and enable OpenAI's AI software stack on new, exploratory accelerator platforms.

• Optimize large-scale model performance (LLMs, recommender systems, distributed AI workloads) for diverse hardware environments.

• Develop kernels, sharding mechanisms, and system scaling strategies tailored to emerging accelerators.

• Collaborate on optimizations at the model code level (e.g. PyTorch) and below to enhance performance on non-traditional hardware.

Perform system-level performance modeling, debug bottlenecks, and drive end-to-end optimization.

• Work with hardware teams and vendors to evaluate alternatives to existing platforms and adapt the software stack to their architectures.

• Contribute to runtime improvements, compute/communication overlapping, and scaling efforts for frontier AI workloads.

You might thrive in this role if you have:

• 3+ years of experience working on AI infrastructure, including kernels, systems, or hardware-software co-design

• Hands-on experience with accelerator platforms for AI at data center scale (e.g., TPUs, custom silicon, exploratory architectures).

• Strong understanding of kernels, sharding, runtime systems, or distributed scaling techniques.

• Familiarity with optimizing LLMs, CNNs, or recommender models for hardware efficiency.

• Experience with performance modeling, system debugging, and software stack adaptation for novel architectures.

• Exposure to mobile accelerators is welcome, but experience enabling data center-scale AI hardware is preferred.

• Ability to operate across multiple levels of the stack, rapidly prototype solutions, and navigate ambiguity in early hardware bring-up phases

• Interest in shaping the future of AI compute through exploration of alternatives to mainstream accelerators.

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