{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/perc"},"x-facet":{"type":"skill","slug":"perc","display":"PERC","count":6},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1c6ce84f-f8a"},"title":"Analog I/O Staff Circuit Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognized for your ability to balance technical depth with practical implementation.</p>\n<p>You bring a strong foundation in FinFet, FDSOI, and BCD technologies, and you are excited by the prospect of owning projects end-to-end--from conceptual design through to silicon qualification. Your approach is meticulous and data-driven, ensuring each design meets the highest standards of quality and reliability.</p>\n<p>Continuous learning excites you, and you embrace opportunities to mentor others, share knowledge, and contribute to a culture of technical excellence. You are motivated by the impact your designs have on real-world products and are committed to delivering robust, scalable, and innovative solutions for Synopsys&#39; worldwide customers.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes.</li>\n</ul>\n<ul>\n<li>Owning the full lifecycle of ESD structures--from schematic design, simulation, and layout to silicon qualification and production release.</li>\n</ul>\n<ul>\n<li>Leading and executing I/O development, including I/O ring design, review, and optimization for performance and robustness.</li>\n</ul>\n<ul>\n<li>Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements.</li>\n</ul>\n<ul>\n<li>Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity.</li>\n</ul>\n<ul>\n<li>Applying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality.</li>\n</ul>\n<ul>\n<li>Collaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Elevating the reliability and performance of Synopsys&#39; interface IPs, directly influencing the success of global semiconductor customers.</li>\n</ul>\n<ul>\n<li>Driving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry.</li>\n</ul>\n<ul>\n<li>Reducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions.</li>\n</ul>\n<ul>\n<li>Accelerating time-to-market for customer products through efficient and high-quality design practices.</li>\n</ul>\n<ul>\n<li>Fostering a culture of technical excellence and continuous improvement within the analog design team.</li>\n</ul>\n<ul>\n<li>Building strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.</li>\n</ul>\n<ul>\n<li>Proven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness.</li>\n</ul>\n<ul>\n<li>Hands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries.</li>\n</ul>\n<ul>\n<li>Strong background in ESD and Latch-Up qualification methodologies, including testchip development and validation.</li>\n</ul>\n<ul>\n<li>Proficiency in ESD simulation, ESD network construction, and use of industry-standard tools.</li>\n</ul>\n<ul>\n<li>Comprehensive understanding of PERC rules and practical experience with PERC verification tools.</li>\n</ul>\n<ul>\n<li>Experience working with cross-functional teams including foundry, design, and layout groups.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>An analytical thinker with excellent problem-solving skills and keen attention to detail.</li>\n</ul>\n<ul>\n<li>A collaborative team player who values diversity, inclusion, and open communication.</li>\n</ul>\n<ul>\n<li>A proactive learner who stays current with industry trends and emerging technologies.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical information to diverse audiences.</li>\n</ul>\n<ul>\n<li>A results-driven individual who is adaptable, resilient, and comfortable with fast-paced, high-impact work.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You&#39;ll join a passionate, multidisciplinary team of analog and mixed-signal engineers dedicated to advancing Synopsys&#39; interface IP portfolio. The team is focused on delivering robust, innovative, and high-quality solutions that meet the rigorous demands of a global customer base. Collaboration, continuous improvement, and technical mentorship are at the core of our culture, ensuring you&#39;ll have the support and opportunities needed to thrive and grow.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1c6ce84f-f8a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-i-o-staff-circuit-design-engineer/44408/94448919616?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["FinFet","FDSOI","BCD","ESD","Latch-Up","PERC","ASIC","IP verification","Analog circuit design","I/O development","ESD/LU robustness","Foundry-provided PERC rules","PERC check tools","ESD simulation","ESD network construction","Industry-standard tools","Cross-functional teams"],"x-skills-preferred":[],"datePosted":"2026-04-28T15:08:11.021Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"FinFet, FDSOI, BCD, ESD, Latch-Up, PERC, ASIC, IP verification, Analog circuit design, I/O development, ESD/LU robustness, Foundry-provided PERC rules, PERC check tools, ESD simulation, ESD network construction, Industry-standard tools, Cross-functional teams"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1a49fd5b-a39"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You will also have expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and bond-pad/IO frame design.</p>\n<p>If you are a proactive problem solver, ready to lead, mentor, and make a tangible impact in a dynamic, fast-paced environment, we encourage you to apply for this exciting opportunity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7181ae65-d2c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93942161264?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical layout design","advanced process nodes","deep submicron effects","advanced floorplan techniques","process technologies","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad/IO frame design"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:10:05.687Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical layout design, advanced process nodes, deep submicron effects, advanced floorplan techniques, process technologies, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad/IO frame design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8ec6d1f4-b98"},"title":"Layout Design, Staff Engineer","description":"<p>We are seeking a highly skilled Layout Design, Staff Engineer to join our team in Bengaluru. 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You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.</p>\n<p>If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.</p>\n<p>Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.</p>\n<p>Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.</p>\n<p>Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.</p>\n<p>Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.</p>\n<p>Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.</p>\n<p>Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.</p>\n<p>Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.</p>\n<p>Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.</p>\n<p>Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.</p>\n<p>Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.</p>\n<p>Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.</p>\n<p>Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.</p>\n<p>Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.</p>\n<p>Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.</p>\n<p>Shaping the future of chip design and verification technologies through your expertise and leadership.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_41cabece-785","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-supervisor/44408/93269033008?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["deep submicron effects","advanced floorplanning techniques","CMOS","FinFET","GAA","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:15.106Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"deep submicron effects, advanced floorplanning techniques, CMOS, FinFET, GAA, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements"}]}